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| VIPer50-E SMPS PRIMARY I.C. General Features Type VIPer50-E VDSS 620V In 1.5A RDS(on) 5 PENTAWATT HV PENTAWATT HV (022Y) ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz CURRENT MODE CONTROL SOFT START AND SHUTDOWN CONTROL AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET "BLUE ANGEL" NORM (<1w TOTAL POWER CONSUMPTION) INTERNALLY TRIMMED ZENER REFERENCE UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS INTEGRATED START-UP SUPPLY OVER-TEMPERATURE PROTECTION LOW STAND-BY CURRENT ADJUSTABLE CURRENT LIMITATION Description VIPer50-E, made using VIPower M0 Technology, combines on the same silicon chip a state-of-theart PWM circuit together with an optimized, high voltage, Vertical Power MOSFET (620V/ 1.5A). Typical applications cover offline power supplies with a secondary power capability of 25W in wide range condition and 50W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components. OSC DRAIN Block Diagram ON/OFF OSCILLATOR SECURITY LATCH VDD PWM LATCH S R1 FF Q R2 R3 UVLO LOGIC R/S FF S Q OVERTEMP. DETECTOR 0.5V _ ++ _ 0.5 V ERROR _ AMPLIFIER 13 V + + _ 1.7 s DELAY 250 ns BLANKING 2 V/A CURRENT AMPLIFIER COMP SOURCE FC00291 4.5 V September 2005 Rev 1 1/29 www.st.com 29 VIPer50-E Contents 1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 3 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 3.3 3.4 3.5 Drain Pin (Integrated Power MOSFET Drain): . . . . . . . . . . . . . . . . . . . . . . . . 8 Source Pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDD Pin (Power Supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Compensation Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OSC Pin (Oscillator Frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 Typical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Current Mode Topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Stand-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 High Voltage Start-up Current Suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transconductance Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External Clock Synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Primary Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operation Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/29 VIPer50-E 6 Electrical Over Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Electrical Over Stress Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 9 10 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3/29 1 Electrical Data VIPer50-E 1 1.1 Table 1. Electrical Data Maximum Rating Absolute Maximum Rating Parameter Continuous Drain-Source Voltage (TJ = 25 to 125C) Maximum Current Supply Voltage Voltage Range Input Voltage Range Input Maximum Continuous Current Electrostatic Discharge (R = 1.5k; C = 100pF) Avalanche Drain-Source Current, Repetitive or Not Repetitive (TC = 100C; Pulse width limited by TJ max; < 1%) Power Dissipation at TC= 25C Junction Operating Temperature Storage Temperature Value -0.3 to 620 Internally limited 0 to 15 0 to VDD 0 to 5 2 4000 1.5 Unit V A V V V mA V A Symbol VDS ID VDD VOSC VCOMP ICOMP VESD ID(AR) PTOT TJ TSTG 60 Internally limited -65 to 150 W C C 4/29 VIPer50-E 1 Electrical Data 1.2 Electrical Characteristics TJ = 25C; V DD = 13V, unless otherwise specified Table 2. Symbol BVDS IDSS Power Section Parameter Drain-Source Voltage Off-State Drain Current Static Drain-Source On Resistance Fall Time Rise Time Output Capacitance Test Conditions ID = 1mA; VCOMP = 0V VCOMP = 0V; T j = 125C VDS = 620V ID = 1A ID = 1A; TJ= 100C ID = 0.2A; VIN =300V (1)Figure 7 ID = 1A; VIN = 300V (1)Figure 7 VDS = 25V 100 50 120 2.3 1 5.0 9 mA Min 620 Typ Max Unit V RDS(on) tf tr Coss ns ns pF (1) On Inductive Load, Clamped. Table 3. Symbol IDDch IDD0 IDD1 IDD2 VDDoff VDDon VDDhyst Supply Section Parameter Start-Up Charging Current Test Conditions VDD = 5V; VDS = 35V (see Figure 6)(see Figure 11) Operating Supply Current VDD = 12V; FSW = 0kHz (see Figure 6) Operating Supply Current Operating Supply Current Undervoltage Shutdown Undervoltage Reset Hysteresis Start-up VDD = 12V; Fsw = 100kHz VDD = 12V; Fsw = 200kHz (see Figure 6) (see Figure 6) (see Figure 6) 2.4 7.5 14 16 8 11 3 9 12 mA mA V V V 12 16 mA Min Typ -2 Max Unit mA Table 4. Symbol FSW Oscillator Section Parameter Oscillator Frequency Total Variation Test Conditions` RT=8.2K; CT=2.4nF VDD=9 to 15V; with RT 1%; CT 5% (see Figure 10)(see Figure 14) Min 90 Typ 100 Max 110 Unit KHz VOSCIH VOSCIL Oscillator Peak Voltage Oscillator Valley Voltage 7.1 3.7 V V 5/29 1 Electrical Data VIPer50-E Table 5. Symbol VDDREG VDDreg GBW Error Amplifier Section Parameter VDD Regulation Point Total Variation Unity Gain Bandwidth Test Conditions` ICOMP=0mA (see Figure 5) TJ = 0 to 100C From Input =VDD to Output = VCOMP COMP pin is open (see Figure 15) Min 12.6 Typ 13 2 150 Max 13.4 Unit V % KHz AVOL Gm VCOMPLO VCOMPHI ICOMPLO ICOMPHI Open Loop Voltage Gain DC Transconductance Output Low Level Output High Level COMP pin is open (see Figure 15) VCOMP=2.5V(see Figure 5) ICOMP=-400A; V DD=14V ICOMP=400A; VDD=12V 45 1.1 52 1.5 0.2 4.5 -600 600 1.9 dB mA/V V V A A Output Low Current Capability VCOMP=2.5V; VDD=14V Output High Current Capability VCOMP=2.5V; VDD=12V Table 6. Symbol HID VCOMPoff IDpeak td tb ton(min) PWM Comparator Section Parameter VCOMP / IDPEAK VCOMP Offset Peak Current Limitation Test Conditions` VCOMP = 1 to 3 V IDPEAK = 10mA VDD = 12V; COMP pin open 1.5 Min 1.4 Typ 2 0.5 2 250 250 350 360 1200 2.7 Max 2.6 Unit V/A V A ns ns ns Current Sense Delay to Turn- ID = 0.5A Off Blanking Time Minimum On Time Table 7. Symbol VCOMPth tDISsu Ttsd Thyst Shutdown and Overtemperature Section Parameter Restart Threshold Disable Set Up Time Thermal Shutdown Temperature Test Conditions` (see Figure 8) (see Figure 8) (see Figure 8) 140 Min Typ 0.5 1.7 170 40 5 Max Unit V s C C Thermal Shutdown Hysteresis (see Figure 8) 6/29 VIPer50-E 2 Thermal Data 2 Table 8. Thermal Data Thermal data Parameter Thermal Resistance Junction-case Thermal Resistance Ambient-case Max Max PENTAWATT HV 1.9 60 Unit C/W C/W Symbol RthJC RthJA 7/29 3 Pin Description VIPer50-E 3 3.1 Pin Description Drain Pin (Integrated Power MOSFET Drain): Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. 3.2 Source Pin: Power MOSFET source pin. Primary side circuit common ground connection. 3.3 VDD Pin (Power Supply): This pin provides two functions : It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the VDD voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again. This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. 3.4 Compensation Pin This pin provides two functions : It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation in case of negligible output power or open load condition. 8/29 VIPer50-E 3 Pin Description 3.5 OSC Pin (Oscillator Frequency): An Rt-Ct network must be connected on that to define the switching frequency. Note that despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It provides also a synchronisation capability, when connected to an external frequency source. Figure 1. Connection Diagrams (Top View) PENTAWATT HV PENTAWATT HV (022Y) Figure 2. Current and Voltage Convention IDD ID VDD DRAIN IOSC OSC 13V + COMP SOURCE VDD VDS ICOMP VOSC VCOMP FC00020 9/29 4 Typical Circuit VIPer50-E 4 Figure 3. Typical Circuit Offline Power Supply With Auxiliary Supply Feedback F1 TR2 BR1 TR1 D1 C2 R1 C3 D3 C10 R7 C4 GND C1 AC IN D2 L2 +Vcc R9 C7 C9 R2 VDD DRAIN OSC 13V C5 + COMP SOURCE C6 C11 VIPer50 R3 FC00301 Figure 4. Offline Power Supply With Optocoupler Feedback F1 TR2 BR1 TR1 D1 C2 R1 C3 D3 C10 R7 C4 GND C7 C9 D2 L2 +Vcc C1 AC IN R9 R2 VDD DRAIN OSC U1 VIPer100 13V C5 + COMP SOURCE C11 C6 R3 ISO1 R6 R4 C8 U2 R5 FC00091 10/29 VIPer50-E 5 Operation Description 5 5.1 Operation Description Current Mode Topology: The current mode control method, like the one integrated in the VIPer50-E, uses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in case there is a short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. 5.2 Stand-by Mode Stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by : 1 2 F P STBY = -- L P I STBY SW 2 Where: LP is the primary inductance of the transformer. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : ( t b + t d )V IN I STBY = ----------------------------Lp tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. 11/29 5 Operation Description VIPer50-E As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level, forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines. This mode of operation allows the VIPer50-E to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system when working in stand-by mode. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.The normal operation resumes automatically when the power gets back to higher levels than PSTBY. 5.3 High Voltage Start-up Current Suorce An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on (see Figure 11). In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the device goes back to the inactive state where the internal circuits are in standby mode and the start-up current source is activated. The converter enters a endless start-up cycle, with a startup duty cycle defined by the ratio of charging current towards discharging when the VIPer100E tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage. This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: It DD SS C VD D > -------------------V DD hyst where: IDD is the consumption current on the VDD pin when switching. Refer to specified I DD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. 12/29 VIPer50-E 5 Operation Description VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. 5.4 Transconductance Error Amplifier The VIPer50-E includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (V DD). Thus: l COMP G m = -----------------V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: CO MP 1 COMP Z CO MP = -------------------- = ------- x -----------------------I Gm V DD COMP V V This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP where Gm value for VIPer50-E is 1.5 mA/V typically. Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately, according to the following equation (very similar to the one above): F(S) = Gm x Z(S) The error amplifier frequency response is reported in Figure 10. for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330K. More complex impedance can be connected on the COMP pin to achieve different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20 As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to avoid any high frequency interference. Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. 13/29 5 Operation Description VIPer50-E 5.5 External Clock Synchronization: The OSC pin provides a synchronisation capability when connected to an external frequency source. Figure 21 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. 5.6 Primary Peak Current Limitation The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: V COMP - 0.5 I D PEAK = ------------------------------H ID where: R1 + R 2 V COMP = 0.6 x -----------------R2 The suggested value for R1+R2 is in the range of 220K. 5.7 Over-Temperature Protection Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140C, while the typical value is 170C. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40C below the shutdown value (see Figure 13) 14/29 VIPer50-E 5 Operation Description 5.8 Operation Pictures VDD Regulation Point Figure 6. Undervoltage Lockout Figure 5. ICOMP ICOMPHI Slope = Gmin m A/V IDD IDD0 VDD 0 ICOMPLO VDDreg FC00150 VDDhyst VDDoff IDDch VDS= 35 V Fsw = 0 VDDon VDD FC00170 Figure 7. Transition Time Figure 8. Shutdown Action VOSC ID VCOMP tDISsu t 10% Ipeak t VDS 90% VD VCOMPth t ID 10% VD t tf tr FC00160 t ENABLE ENABLE DISABLE FC00060 Figure 9. Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation 1.15 FC00180 FC00190 BVDSS (Normalized) (%) 1 0 1.1 -1 1.05 -2 -3 1 -4 -5 0 20 40 60 80 100 120 Temperature (C) 0.95 0 20 40 60 80 100 120 140 Temperature (C) 15/29 5 Operation Description VIPer50-E Figure 11. Behaviour of the high voltage current source at start-up VDD VDDon VDDoff 2 mA 15 mA CVDD VDD 1 mA 15 mA 3 mA DRAIN Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIPer50 SOURCE Start up duty cycle ~ 12% FC00320 Figure 12. Start-Up Waveforms 16/29 Figure 13. Over-temperature Protection VIPer50-E T T ts c J 0000000000000000000000000000 000 000 00 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 0000 00000 0000 0000 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000 00 0 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000 00000 0000000000000000 0000 00000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000 00 0 00000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000 000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 SC 1 0 1 9 1 T t s d -T h y s t V dd on V dd off V co m p Vdd Id t t t t 5 Operation Description 17/29 5 Operation Description VIPer50-E Figure 14. Oscillator For R t > 1.2k and Ct 40KHz 550 2.3 F SW = ---------- 1 - ------------------R t - 150 RtCt CLK Ct ~360 Rt O SC VDD FC 00050 Ct Forbidden area 880 Ct(nF) = 22nF 15nF Fsw(kHz) Forbidden area 40kHz Fsw FC00030 Oscillator frequency vs Rt and Ct 1,000 Ct = 1.5 nF 500 Ct = 2.7 nF Frequency (kHz) 300 200 Ct = 4.7 nF Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (k) 18/29 VIPer50-E Figure 15. Error Amplifier frequency Response FC00200 5 Operation Description 60 RCOMP = + RCOMP = 270k Voltage Gain (dB) 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 Figure 16. Error Amplifier Phase Response FC00210 200 RCOMP = + 150 Phase () 100 50 0 (50) 0.001 RCOMP = 270k RCOMP = 82k RCOMP = 27k RCOMP = 12k 0.01 0.1 1 10 Frequency (kHz) 100 1,000 19/29 5 Operation Description VIPer50-E Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down D2 VIPer50 VDD DRAIN D3 R1 VDD VIPer50 DRAIN OSC 13V + COMP SOURCE R3 D1 Q2 OSC 13V + COMP SOURCE AUXILIARY WINDING R2 R3 R2 C4 R1 R4 Shutdown + C3 C1 + C2 Q1 D1 FC00331 FC00340 Figure 19. Typical Compensation Network VIPer50 VDD OSC 13V DRAIN Figure 20. Slope Compensation + COMP SOURCE R2 R1 VIPer5 0 VD D D RAIN OS C 13V + C OM P SO UR CE C2 R1 C1 C1 Q1 C2 C3 R3 FC00351 Figure 21. External Clock Sinchronisation FC 00361 Figure 22. Current Limitation Circuit Example VIPer50 VDD DRAIN VIPer50 VDD DRAIN OSC 13V + COMP SOURCE OSC 13V + COMP SOURCE 10 k R1 Q1 R2 FC00370 FC00380 20/29 VIPer50-E 6 Electrical Over Stress 6 6.1 Electrical Over Stress Electrical Over Stress Ruggedness The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be implemented to improve the application immunity to such surges. Figure 23. Input Voltage Surges Protection R1 (Optional) R2 39R D1 Auxilliary winding C2 22nF OSC 13V VIPerXX0 VDD + DRAIN C1 Bulk capacitor COMP SOURCE 21/29 7 Layout VIPer50-E 7 7.1 Layout Layout Considerations Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: - Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. Using different tracks for low level and power signals: Interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. C6 must be as close as possible to T1. Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device. - In case of VIPer, these rules apply as shown on (see Figure 24). - - - Figure 24. Recommended Layout T1 D1 D2 C7 To secondary filtering and load R1 VDD DRAIN C1 OSC 13V + COMP SOURCE C5 From input diodes bridge U1 VIPerXX0 R2 C2 C3 ISO1 C4 C6 FC00500 22/29 VIPer50-E 8 Package Mechanical Data 8 Package Mechanical Data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 23/29 8 Package Mechanical Data VIPer50-E Pentawatt HV Mechanical Data mm. Dim Min. Typ. Maw. Min. Typ. Max. inch A C D E F G1 G2 H1 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 R V4 Diam 4.30 1.17 2.40 0.35 0.60 4.91 7.49 9.30 4.80 1.37 2.80 0.55 0.80 5.21 7.80 9.70 10.40 0.169 0.046 0.094 0.014 0.024 0.193 0.295 0.366 0.189 0.054 0.11 0.022 0.031 0.205 0.307 0.382 0.409 0.396 0.409 0.681 0.599 0.860 0.898 0.118 0.622 0.260 0.122 0.220 10.05 15.60 14.60 21.20 22.20 2.60 15.10 6 2.50 4.50 0.50 10.40 17.30 15.22 21.85 22.82 3 15.80 6.60 3.10 5.60 6.14 0.575 0.835 0.874 0.102 0.594 0.236 0.098 0.177 0.02 90 3.65 3.85 0.144 0.152 P023H3 24/29 VIPer50-E 8 Package Mechanical Data Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data mm. Dim Min. Typ. Maw. Min. Typ. Max. inch A C D E F G1 G2 H1 H2 H3 L L1 L3 L5 L6 L7 M M1 R V4 Diam 4.30 1.17 2.40 0.35 0.60 4.91 7.49 9.30 4.80 1.37 2.80 0.55 0.80 5.21 7.80 9.70 10.40 0.169 0.046 0.094 0.014 0.024 0.193 0.295 0.366 0.189 0.054 0.110 0.022 0.031 0.205 0.307 0.382 0.409 10.05 16.42 14.60 20.52 2.60 15.10 6.00 2.50 5.00 0.50 90 3.65 10.40 17.42 15.22 21.52 3.00 15.80 6.60 3.10 5.70 0.396 0.646 0.575 0.808 0.102 0.594 0.236 0.098 0.197 0.02 0.020 90 0.409 0.686 0.599 0.847 0.118 0.622 0.260 0.122 0.224 3.85 0.144 0.154 L L1 E M1 G2 G1 A M D C R Resin between leads L6 L7 V4 H1 H3 H2 F DIA L3 L5 25/29 8 Package Mechanical Data VIPer50-E Figure 25. Pentawatt HV Tube Shipment ( no suffix ) Base Q.ty Bulk Q.ty Tube length ( 0.5 ) A B C ( 0.1) 50 1000 532 18 33.1 1 All dimensions are in mm. 26/29 VIPer50-E 9 Order Codes 9 Order Codes PENTAWATT HV PENTAWATT HV (022Y) VIPer50-E VIPER50-22-E 27/29 10 Revision history VIPer50-E 10 Revision history Date Revision Changes 26-Sep-2005 1 Initial release. 28/29 VIPer50-E 10 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 29/29 |
Price & Availability of VIPER50-22-E
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