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This X25057 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
4K
X25057
5MHz Low Power SPI Serial E2PROM with IDLockTM Memory
DESCRIPTION
512 x 8 Bit
FEATURES
*5MHz Clock Rate *IDLockTM Memory
--IDLock First or Last Page, Any 1/4 or Lower 1/2 of 2 E PROM Array
The X25057 is a CMOS 4K-bit serial E PROM, internally organized as 512 x 8. The X25057 features a Serial
2
Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. IDLock is a programmable locking mechanism which allows the user to lock system ID and parametric data in
*Low Power CMOS --<1A Standby Current --<3mA Active Current during Write -- <400A Active Current during Read *1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation *Built-in Inadvertent Write Protection --Power-Up/Power-Down Protection Circuitry -- Write Enable Latch --Write Protect Pin *SPI Modes (0,0 & 1,1) *512 x 8 Bits
different portions of the E2PROM memory space, ranging from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that can be used for hardwire protection of the part, disabling
--16 Byte Page Mode *Self-Timed Write Cycle --5ms Write Cycle Time (Typical) *High Reliability --Endurance: 100,000 Cycles/Byte --Data Retention: 100 Years --ESD: 2000V on all pins *8-Lead MSOP Package *8Lead TSSOP Package *8-Lead SOIC Package *8-Lead PDIP Package FUNCTIONAL DIAGRAM
SI SO
COMMAND DECODE AND CONTROL
all write attempts, as well as a Write Enable Latch that must be set before a write operation can be initiated.
The X25057 utilizes Xicor's proprietary Direct Write providing a minimum endurance of 100,000 cycles
TM
cell,
per byte and a minimum data retention of 100 years.
DATA REGISTER Y DECODE LOGIC 16 8
SCK
X DECODE LOGIC
32
LOGIC
4K E PROM ARRAY
2
(512 x 8) CS
WP
WRITE CONTROL LOGIC
HIGH VOLTAGE CONTROL
7033 FRM F01 Characteristics subject to change without notice
(c)Xicor, Inc. 1994 - 1997 Patents Pending 7033-1.1 5/8/97 T1/C0/D0 SH
1
X25057
PIN DESCRIPTIONS
Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25057 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25057 will be in the standby power mode. CS LOW enables the X25057, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25057 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25057. If the internal write cycle has already been initiated, WP going low will have no affect on this write.
SO CS
PIN CONFIGURATION
Not to scale 8 Lead SOIC/PDIP
CS SO
1 2 3 4 *0.244" 8 Lead MSOP 1 2 3 4 0.193" X25057 X25057
8 7 6 5
*0.197"
V CC NC
WP
V SS
SCK SI
7033 FRM F02
8 7 6 5
V CC NC
0.120"
V SS WP
SI SCK
7033 FRM F02.1
8 Lead TSSOP NC 0.122"
V CC CS
1 2 3 4 0.252" X25057
8 7 6 5
SCK SI
V SS WP
7033 FRM F02.2
SO
*SOIC Measurement
PRINCIPLES OF OPERATION
The X25057 is a 512 x 8 E PROM designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25057 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the WP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume opera- tions where left off.
2
PIN NAMES Symbol
CS SO SI SCK WP
VSS VCC
Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage No Connect
7033 FRM T01
NC
2
X25057
Write Enable Latch
The X25057 contains a "Write Enable" latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruc- tion will reset the latch (Figure 4). This latch is Automatically reset upon a power-up condition and after the completion of a byte or page write cycle. IDLock Memory Xicor's IDLock Memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct IDLock Memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are IDLocked by writing the appropriate two byte IDLock instruction to the device as described in Table 1 and Figure 7. Once an IDLock instruction has been completed, that IDLock setup is held in a nonvolatile Status Register (Figure 1) until the next IDLock instruction is issued. The sections of the memory array that are IDLocked can be read but not written until IDLock is removed or changed.
Read Status Operation If there is not a nonvolatile write in progress, the Read Status instruction returns the ID Lock byte from the Status Register which contains the ID Lock bits IDL2-IDL0 (Figure 1). The ID Lock bits define the ID Lock condition (Figure 1/Table1). The other bits are reserved and will return '0' when read. See Figure 3. If a nonvolatile write is in progress, the Read Status Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, the status register data is read out. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (See Figure 3). Write Sequence Prior to any attempt to write data into the X25057, the "Write Enable" latch must first be set by issuing the WREN instruction (See Table 1 and Figure 4). CS is first taken LOW. Then the WREN instruction is clocked into the X25057. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E PROM memory array, the user then issues the WRITE instruction, followed by the 16 bit address and the data to be written. Only the last 9 bits of the address are used and bits [15:9] are specified to be zeroes. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to wrote up to 16 bytes of data to the X25057. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been previously written. For a byte or page write operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figures 5 and 6 for detailed illustration of the write sequences and time frames in which CS going HIGH are valid.
2
Figure 1. Status Register/IDLock Protection Byte
7 0
6 0
5 0
4 0
3 0
2
1
0
IDL2 IDL1 IDL0
7038 FRM T02.1
Note: Bits [7:3] specified to be "0's"
Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence 2 When reading from the E PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25057, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be zeroes). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the Read Operation Sequence illustrated in Figure 2.
3
X25057
Operational Notes The X25057 powers up in the following state: *The device is in the low power, standby state. *A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. *SO pin is at high impedance. *The "Write Enable" latch is reset. Data Protection The following circuitry has been included to prevent inadvertant writes: *The "Write Enable" latch is reset upon power-up. *A WREN instruction must be issued to set the "Write Enable" latch. *CS must come HIGH at the proper clock count in order to start a write cycle.
IDLock Operation
Prior to any attempt to perform an IDLock Operation, the WREN instruction must first be issued. This instruction sets the "Write Enable" latch and allows the part to respond to an IDLock sequence (Figure 7). The IDLock instruction follows and consists of one command byte followed by one IDLock byte (See Figure 1). This byte contains the IDLock bits IDL2-IDL0. The rest of the bits [7:3] are unused and must be written as zeroes. Bringing CS HIGH after the two byte IDLock instruction initiates a nonvolatile write to the Status Register. Writing more than one byte to the Status Register will overwrite the previously written IDLock byte. See Table 1.
Table 1. Instruction Set and Block Lock Protection Byte Definition Instruction Format*
0000 0110 0000 0100 0000 0001
Instruction Name and Operation
WREN: Set the Write Enable Latch (Write Enable Operation) WRDI: Reset the Write Enable Latch (Write Disable Operation)
IDLock Instruction--followed by: IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h ---------->None of the Array 0000 0001 --->IDLock Q1: 00h-7Fh ---------->Lower Quadrant (Q1) 0000 0010 --->IDLock Q2: 80h-FFh----------->Q2 0000 0011 --->IDLock Q3: 100h-17Fh-------->Q3 0000 0100 --->IDLock Q4: 180h-1FFh-------->Upper Quadrant (Q4) 0000 0101 --->IDLock H1: 00h-FFh----------->Lower Half of the Array (H1) 0000 0110 --->IDLock P0: 0h-Fh-------------->Lower Page (P0) 0000 0111 --->IDLock Pn: 1F0h-1FFh-------->Upper Page (Pn) 0000 0101 0000 0010 0000 0011 READ STATUS: Reads IDLock & write in progress status on SO Pin WRITE: Write operation followed by address and data READ: Read operation followed by address
7033 FRM T03
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
4
X25057
Figure 2. Read Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30
READ INSTRUCTION (1 BYTE)
BYTE ADDRESS (2 BYTE) 15 14 3 2 1 0
DATA OUT
SI
HIGH IMPEDANCE SO
7
6
5
4
3
2
1
0
7033 FRM F03.1
Figure 3. Read Status Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
... ...
I
D L
READ STATUS INSTRUCTION
SI NONVOLATILE WRITE IN PROGRESS
I D L I D L
SO
...
2
1
0
SO HIGH DURING NONVOLATILE WRITE CYCLE
SO = STATUS REG BIT WHEN NO NONVOLATILE
WRITE CYCLE
7033 FRM F04.2
5
X25057
Figure 4. WREN/WRDI Sequence
CS
0 SCK
1
2
3
4
5
6
7
INSTRUCTION (1 BYTE)
SI
SO
HIGH IMPEDANCE
7033 FRM F05.1
Figure 5. Byte Write Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
WRITE INSTRUCTION (1 BYTE)
BYTE ADDRESS (2 BYTE) 15 14 3 2 1 0 7 6
DATA BYTE 5 4 3 2 1 0
SI
HIGH IMPEDANCE SO
7033 FRM F06
6
X25057
Figure 6. Page Write Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
PROGRAM INSTRUCTION
BYTEADDRESS (2 BYTE) 15 14 13 3 2 1 0 7 6
DATA BYTE 1 5 4 3 2 1 0
SI
CS 151 DATA BYTE 16 1 0 6 5 4 3 2 1 0
7033 FRM F07.3
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK
DATA BYTE 2 SI 7 6 5 4 3 2 1 0 7 6
DATA BYTE 3 5 4 3 2
Figure 7. IDLock Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IDLock INSTRUCTION SI 0 0 0
IDLock BYTE
0
0
I D L
I D L
I D L
2
1
0
HIGH IMPEDANCE SO
7033 FRM F08.2
7
X25057
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ................... -65C to +135C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature ....................... -65C to +150C
Voltage on any Pin with Respect to VSS ................................... -1V to +7V
D.C. Output Current .............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Supply Voltage
X25057 X25057-2.7 X25057-1.8
Limits
4.5V to 5.5V 2.7V to 5.5V 1.8V to 3.6V
7033 FRM T05
Min.
0C -40C
Max.
+70C +85C
7033 FRM T04
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits Symbol
ICC1 ICC2 ISB ILI ILO
Parameter
VCC Supply Current (Write) VCC Supply Current (Read )
VCC Supply Current (Standby)
Min.
Max.
3 400 1 10 10
Units
mA A A A A V V V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open, CS = VSS SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open, CS = VSS
CS = VCC, VIN = VSS or VCC VIN = VSS to VCC VOUT = VSS to VCC
Input Leakage Current Output Leakage Current
(1)
VIL
Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage
-0.5
VCC x 0.7
VCC x 0.3 VCC + 0.5
VIH(1)
VOL1 VOL2 VOL3 VOH1 VOH2 VOH3
0.4 0.4 0.4
VCC - 0.8 VCC - 0.4 VCC - 0.2
VCC > 3.3V, IOL = 2.1mA 2V < VCC = 3.3V, I OL = 1mA VCC = 2V, I OL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC = 3.3V, I OH = -0.4mA VCC = 2V, I OH = -0.25mA
7033 FRM T06
POWER-UP TIMING Symbol
tPUR
(2) (2)
Parameter
Power-up to Read Operation Power-up to Write Operation
Min.
Max.
1 5
Units
ms ms
7033 FRM T07
tPUW
Notes: (1)VIL Min. and VIH Max. are for reference only and are not 100% tested. (2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
8
X25057
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5.0V.
Symbol
COUT CIN(3)
(3)
Parameter
Output Capacitance (SO) Input Capacitance (SCK, SI, CS, WP)
Max.
8 6
Units
pF pF
Conditions
VOUT = 0V VIN = 0V
7033 FRM T08
EQUIVALENT A.C. LOAD CIRCUIT
5V 2061 OUTPUT 3025 2696 OUTPUT 5288 3.3V 2800 OUTPUT 5600 2V
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
30pF
VCC x 0.1 to VCC x 0.9
10ns
VCC X 0.5
7033 FRM T09
30pF
30pF
Input and Output Timing Level
7033 FRM F09.1
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Data Input Timing
Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH
Parameter
Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Data In Rise Time Data In Fall Time CS Deselect Time
2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V
Voltage
Min.
0 200 300 100 150 100 150 80 130 80 130 20 20
Max.
5 3.3
Units
MHz ns ns ns ns ns ns
tRI tFI
(3)
2 2 100 10
ns s s ns ms
7033 FRM T10
(3)
tCS
tWC
(4)
Write Cycle Time
Notes: (3)This parameter is periodically sampled and not 100% tested. (4)tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
9
X25057
Data Output Timing Symbol
fSCK tDIS tV tHO
Parameter
Clock Frequency Output Disable Time Output Valid from Clock LOW Output Hold Time
Voltage
2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V
Min.
0
Max.
5 3.3 100 150 80 130
Units
MHz ns ns ns
0 50 50
tRO tFO
(5)
Output Rise Time Output Fall Time
ns ns
7033FRM T11
(5)
Notes: (5)This parameter is periodically sampled and not 100% tested.
Figure 8. Serial Output Timing
CS tCYC SCK tV SO MSB OUT MSB-1 OUT tHO tWL LSB OUT tDIS tWH tLAG
SI
ADDR LSB IN
7033 FRM F10
SYMBOL TABLE
WAVEFORM INPUTS
Must be steady May change from LOW
OUTPUTS
Will be steady Will change from LOW
to HIGH
May change from HIGH
to HIGH
Will change from HIGH
to LOW
Don't Care: Changes
to LOW
Changing: State Not
Allowed N/A
Known
Center Line is High
Impedance
10
X25057
Figure 9. Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
HIGH IMPEDANCE SO
7033 FRM F11
11
X25057
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 TYP
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) REF. 0.193 (4.90) REF.
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 FRM 01
12
X25057
PACKAGING INFORMATION 8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .177 (4.5)
.252 (6.4) BSC
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8
.019 (.50) .029 (.75)
Seating Plane
Detail A (20X)
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25057
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00)
0.228 (5.80) 0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8
0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937)
0.050" TYPICAL
0.250"
0.030" TYPICAL
FOOTPRINT
8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F22.1
14
X25057
PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10)
PIN 1 INDEX PIN 1
0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE
0.145 (3.68) 0.128 (3.25)
0.150 (3.81) 0.125 (3.18)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14)
0.110 (2.79) 0.090 (2.29)
0.020 (0.51) 0.016 (0.41)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP
.
0.010 (0.25)
0 15
NOTE: 1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
15
X25057
ORDERING INFORMATION X25057 Device P T G -V
VCC Limits Blank = 4.5V to 5.5V 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C
Package M = 8-Lead MSOP
V = 8-Lead TSSOP S = 8-Lead SOIC
Part Mark Convention 8-Lead MSOP
EYWW XXX
P = 8-Lead PDIP 8-Lead TSSOP
EYWW 5057XX
8-Lead SOIC/PDIP Blank = 8-Lead SOIC P = 8-Lead PDIP G = RoHS compliant leadfree AG = 1.8 to 3.6V, 0 to +70C AH = 1.8 to 3.6V, -40 to +85C F = 2.7 to 5.5V, 0 to +70C G = 2.7 to 5.5V, -40 to +85C
X25057 G XXX Blank = 4.5 to 5.5V, 0 to +70C I = 4.5 to 5.5V, -40 to +85C
AAA = 1.8 to 3.6V, 0 to +70C
AAC = 1.8 to 3.6V, -40 to +85C AAO = 2.7 to 5.5V, 0 to +70C AAP = 2.7 to 5.5V, -40 to +85C AAF = 4.5 to 5.5V, 0 to +70C
AG = 1.8 to 3.6V, 0 to +70C
AH = 1.8 to 3.6V, -40 to +85C F = 2.7 to 5.5V, 0 to +70C
G = 2.7 to 5.5V, -40 to +85C Blank = 4.5 to 5.5V, 0 to +70C
AAG = 4.5 to 5.5V, -40 to +85C
I = 4.5 to 5.5V, -40 to +85C
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
16

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