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| NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor D P2003EVG SOP-8 Lead-Free PRODUCT SUMMARY V(BR)DSS -30 RDS(ON) 20m ID -9A G S 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -30 20 -9 -8 -50 2.5 1.3 -55 to 150 UNITS V V TC = 25 C TC = 70 C ID IDM A TC = 25 C TC = 70 C PD Tj, Tstg W Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 C UNITS C / W C / W SYMBOL RJc RJA TYPICAL MAXIMUM 25 50 Pulse width limited by maximum junction temperature. Duty cycle 1% ELECTRICAL CHARACTERISTICS (TC = 25 C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = -250A VDS = VGS, ID = -250A VDS = 0V, VGS = 20V VDS = -24V, VGS = 0V VDS = -20V, VGS = 0V, TJ = 125 C VDS = -5V, VGS = -10V VGS = -4.5V, ID = -7A VGS = -10V, ID = -9A VDS = -10V, ID = -9A -50 25 15 24 35 20 -30 -1 -1.5 -3 100 nA -1 -10 A A m S V LIMITS UNIT MIN TYP MAX OCT-20-2004 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG SOP-8 Lead-Free DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 Ciss Coss Crss Qg Qgs Qgd td(on) tr 2 1610 VGS = 0V, VDS = -15V, f = 1MHz 410 200 17 VDS = 0.5V(BR)DSS, VGS = -10V, ID = -9A 5 6 5.7 VDS = -15V, RL = 1 ID -1A, VGS = -10V, RGS = 6 10 18 5 nS 24 nC pF Gate-Source Charge2 Gate-Drain Charge 2 2 Turn-On Delay Time2 Rise Time Turn-Off Delay Time Fall Time2 td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 C) Continuous Current Pulsed Current 1 2 3 IS ISM VSD IF = -1A, VGS = 0V -2.1 -4 -1.2 A V Forward Voltage1 Pulse test : Pulse Width 300 sec, Duty Cycle 2 . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH "P2003EVG", DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. OCT-20-2004 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG SOP-8 Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature 100 10 -Is - Reverse Drain Current(A) V GS = 0V 1 T A = 125 C 0.1 25 C 0.01 -55 C 0.001 0.0001 0 0.2 0.4 0.6 0.8 -VSD - Body Diode Forward Voltage(V) 1.0 1.2 OCT-20-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG SOP-8 Lead-Free OCT-20-2004 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG SOP-8 Lead-Free SOIC-8(D) MECHANICAL DATA mm Dimension Min. A B C D E F G mm Dimension Max. 5.0 4.0 6.2 0.51 H I J K L 1.75 0.25 Typ. 4.9 3.9 6.0 0.445 1.27 Min. 0.5 0.18 Typ. 0.715 0.254 0.22 Max. 0.83 0.25 4.8 3.8 5.8 0.38 0 4 8 1.35 0.1 1.55 0.175 M N OCT-20-2004 5 |
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