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| Low Distortion, High Speed Rail-to-Rail Input/Output Amplifiers AD8027/AD8028 FEATURES High speed 190 MHz, -3 dB bandwidth (G = +1) 100 V/s slew rate Low distortion 120 dBc @ 1 MHz SFDR 80 dBc @ 5 MHz SFDR Selectable input crossover threshold Low noise 4.3 nV/Hz 1.6 pA/Hz Low offset voltage: 900 V max Low power: 6.5 mA/amplifier supply current Power-down mode No phase reversal: VIN > |VS| + 200 mV Wide supply range: 2.7 V to 12 V Small packaging: SOIC-8, SOT-23-6, MSOP-10 AD8027 SOIC-8 (R) NC 1 -IN 2 +IN 3 -VS 4 8 7 6 5 CONNECTION DIAGRAMS AD8027 SOT-23-6 (RT) DISABLE/SELECT +VS VOUT NC +IN 3 4 VOUT 1 -VS 2 6 +VS DISABLE/SELECT + - 5 NC = NO CONNECT -IN AD8028 SOIC-8 (R) VOUTA 1 -IN A 2 +IN A 3 -VS 4 - + - + 8 7 6 5 AD8028 MSOP-10 (RM) +VS VOUTB -IN B +IN B VOUTA 1 -IN A 2 +IN A 3 -VS 4 DISABLE/SELECT A 5 03327-B-001 10 +VS - + - + 9 8 7 6 VOUTB -IN B +IN B DISABLE/SELECT B Figure 1. Connection Diagrams (Top View) APPLICATIONS Filters ADC drivers Level shifting Buffering Professional video Low voltage instrumentation With their wide supply voltage range (2.7 V to 12 V) and wide bandwidth (190 MHz), the AD8027/AD8028 amplifiers are designed to work in a variety of applications where speed and performance are needed on low supply voltages. The high performance of the AD8027/AD8028 is achieved with a quiescent current of only 6.5 mA/amplifier typical. The AD8027/AD8028 have a shutdown mode that is controlled via the SELECT pin. The AD8027/AD8028 are available in SOIC-8, MSOP-10, and SOT-23-6 packages. They are rated to work over the industrial temperature range of -40C to +125C. -20 G = +1 FREQUENCY = 100kHz RL = 1k GENERAL DESCRIPTION The AD8027/AD80281 are high speed amplifiers with rail-torail input and output that operate on low supply voltages and are optimized for high performance and wide dynamic signal range. The AD8027/AD8028 have low noise (4.3 nV/Hz, 1.6 pA/Hz) and low distortion (120 dBc at 1 MHz). In applications that use a fraction of, or the entire input dynamic range and require low distortion, the AD8027/AD8028 are ideal choices. Many rail-to-rail input amplifiers have an input stage that switches from one differential pair to another as the input signal crosses a threshold voltage, which causes distortion. The AD8027/AD8028 have a unique feature that allows the user to select the input crossover threshold voltage through the SELECT pin. This feature controls the voltage at which the complementary transistor input pairs switch. The AD8027/ AD8028 also have intrinsically low crossover distortion. -40 -60 VS = +3V SFDR (dB) VS = +5V VS = 5V -80 -100 -120 -140 0 1 2 3 4 5 6 7 OUTPUT VOLTAGE (V p-p) 8 9 10 03327-A-063 Figure 2. SFDR vs. Output Amplitude 1 Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD8027/AD8028 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 17 Input Stage................................................................................... 17 Crossover Selection .................................................................... 17 Output Stage................................................................................ 18 DC Errors .................................................................................... 18 Wideband Operation ..................................................................... 19 Circuit Considerations .............................................................. 19 Applications..................................................................................... 21 Using the SELECT Pin............................................................... 21 Driving a 16-Bit ADC................................................................ 21 Band-Pass Filter.......................................................................... 22 Design Tools and Technical Support ....................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 24 REVISION HISTORY 3/05--Rev. B to Rev. C Updated Format..................................................................Universal Change to Figure 1 ........................................................................... 1 10/03--Rev. A to Rev. B Changes to Figure 1...........................................................................1 8/03--Rev. 0 to Rev. A Addition of AD8028........................................................... Universal Changes to GENERAL DESCRIPTION.........................................1 Changes to Figures 1, 3, 4, 8, 13, 15, 17 ......................... 1, 6, 7, 8, 9 Changes to Figures 58, 60........................................................ 18, 20 Changes to SPECIFICATIONS........................................................3 Updated OUTLINE DIMENSIONS .............................................22 Updated ORDERING GUIDE.......................................................23 3/03--Revision 0: Initial Version Rev. C | Page 2 of 24 AD8027/AD8028 SPECIFICATIONS VS = 5 V at TA = 25C, RL = 1 k to midsupply, G = 1, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Crosstalk, Output to Output DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current 1 Conditions G = 1, VO = 0.2 V p-p G = 1, VO = 2 V p-p G = 2, VO = 0.2 V p-p G = +1, VO = 2 V step/G = -1, VO = 2 V step G = 2, VO = 2 V step fC = 1 MHz, VO = 2 V p-p, RF = 24.9 fC = 5 MHz, VO = 2 V p-p, RF = 24.9 f = 100 kHz f = 100 kHz NTSC, G = 2, RL = 150 NTSC, G = 2, RL = 150 G = 1, RL = 100 , VOUT = 2 V p-p, VS = 5 V @ 1 MHz SELECT = three-state or open, PNP active SELECT = high NPN active TMIN to TMAX VCM = 0 V, NPN active TMIN to TMAX VCM = 0 V, PNP active TMIN to TMAX VO = 2.5 V 100 Min 138 20 Typ 190 32 16 90/100 35 120 80 4.3 1.6 0.1 0.2 -93 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz % Degrees dB Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Impedance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio SELECT PIN Crossover Low, Selection Input Voltage Crossover High, Selection Input Voltage Disable Input Voltage Disable Switching Speed Enable Switching Speed OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Output Off Isolation Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio 200 240 1.50 4 4 -8 -8 0.1 110 6 2 -5.2 to +5.2 110 -3.3 to +5 -3.9 to -3.3 -5 to -3.9 980 45 40/45 800 900 6 -11 0.9 V V V/C A A A A A dB M pF V dB V V V ns ns ns VCM = 2.5 V Three-state < 20 A 90 50% of input to <10% of final VO VI = +6 V to -6 V, G = -1 -VS + 0.10 Sinking and Sourcing VIN = 0.2 V p-p, f = 1 MHz, SELECT = low 30% overshoot 2.7 SELECT = low VS 1 V +VS - 0.06, -VS + 0.06 120 -49 20 +VS - 0.10 V mA dB pF 90 6.5 370 110 12 8.5 500 V mA A dB 1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C | Page 3 of 24 AD8027/AD8028 VS = 5 V at TA = 25C, RL = 1 k to midsupply, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Crosstalk, Output to Output DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current 1 Conditions G = 1, VO = 0.2 V p-p G = 1, VO = 2 V p-p G = 2, VO = 0.2 V p-p G = +1, VO = 2 V step/G = -1, VO = 2 V step G = 2, VO = 2 V step fC = 1 MHz, VO = 2 V p-p, RF = 24.9 fC = 5 MHz, VO = 2 V p-p, RF = 24.9 f = 100 kHz f = 100 kHz NTSC, G = 2, RL = 150 NTSC, G = 2, RL = 150 G = 1, RL = 100 , VOUT = 2 V p-p, VS = 5 V @ 1 MHz SELECT = three-state or open, PNP active SELECT = high NPN active TMIN to TMAX VCM = 2.5 V, NPN active TMIN to TMAX VCM = 2.5 V, PNP active TMIN to TMAX VO = 1 V to 4 V 96 Min 131 18 Typ 185 28 12 85/100 40 90 64 4.3 1.6 0.1 0.2 -92 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz % Degrees dB Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Impedance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio SELECT PIN Crossover Low, Selection Input Voltage Crossover High, Selection Input Voltage Disable Input Voltage Disable Switching Speed Enable Switching Speed OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Off Isolation Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio 200 240 2 4 4 -8 -8 0.1 105 6 2 -0.2 to +5.2 105 1.7 to 5 1.1 to 1.7 0 to 1.1 1100 50 50/50 800 900 6 -11 0.9 V V V/C A A A A A dB M pF V dB V V V ns ns ns VCM = 0 V to 2.5 V Three-state < 20 A 90 50% of input to <10% of final VO VI = -1 V to +6 V, G = -1 RL = 1 k VIN = 0.2 V p-p, f = 1 MHz, SELECT = low Sinking and sourcing 30% overshoot 2.7 SELECT = low VS 1 V -VS + 0.08 +VS - 0.04, -VS + 0.04 -49 105 20 +VS - 0.08 V dB mA pF 90 6 320 105 12 8.5 450 V mA A dB 1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C | Page 4 of 24 AD8027/AD8028 VS = 3 V at TA = 25C, RL = 1 k to midsupply, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Crosstalk, Output to Output DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current 1 Conditions G = 1, VO = 0.2 V p-p G = 1, VO = 2 V p-p G = 2, VO = 0.2 V p-p G = +1, VO = 2 V step/G = -1, VO = 2 V step G = 2, VO = 2 V step fC = 1 MHz, VO = 2 V p-p, RF = 24.9 fC = 5 MHz, VO = 2 V p-p, RF = 24.9 f = 100 kHz f = 100 kHz NTSC, G = 2, RL = 150 NTSC, G = 2, RL = 150 G = 1, RL = 100 , VOUT = 2 V p-p, VS = 3 V @ 1 MHz SELECT = three-state or open, PNP active SELECT = high NPN active TMIN to TMAX VCM = 1.5 V, NPN active TMIN to TMAX VCM = 1.5 V, PNP active TMIN to TMAX VO = 1 V to 2 V 90 Min 125 19 Typ 180 29 10 73/100 48 85 64 4.3 1.6 0.15 0.20 -89 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz % Degrees dB Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Impedance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio SELECT PIN Crossover Low, Selection Input Voltage Crossover High, Selection Input Voltage Disable Input Voltage Disable Switching Speed Enable Switching Speed OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Off Isolation Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Quiescent Current (Disabled) Power Supply Rejection Ratio 200 240 2 4 4 -8 -8 0.1 100 6 2 -0.2 to +3.2 100 1.7 to 3 1.1 to 1.7 0 to 1.1 1150 50 55/55 800 900 6 -11 0.9 V V V/C A A A A A dB M pF V dB V V V ns ns ns RL = 1 k VCM = 0 V to 1.5 V Three-state < 20 A 88 50% of input to <10% of final VO VI = -1 V to +4 V, G = -1 RL = 1 k Sinking and sourcing VIN = 0.2 V p-p, f = 1 MHz, SELECT = low 30% Overshoot 2.7 SELECT = low VS 1 V -VS + 0.07 +VS - 0.03, -VS + 0.03 72 -49 20 +VS - 0.07 V mA dB pF 88 6.0 300 100 12 8.0 420 V mA A dB 1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C | Page 5 of 24 AD8027/AD8028 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12.6 V See Figure 3 VS 0.5 V 1.8 V -65C to +125C -40C to +125C 300C 150C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power - Load Power) V V PD = (VS x I S )+ S x OUT 2 RL VOUT 2 - RL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, then the total drive power is VS x IOUT. If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8027/AD8028 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8027/AD8028. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as PD = (VS x I S ) + (VS /4 )2 RL In single-supply operation with RL referenced to VS-, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in the PCB Layout section. TJ = TA + PD x JA ( ) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 24 AD8027/AD8028 Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC-8 (125C/W), SOT-23-6 (170C/W), and MSOP-10 (130C/W) packages on a JEDEC standard 4-layer board. 2.0 MAXIMUM POWER DISSIPATION (W) 1.5 SOIC-8 Output Short Circuit Shorting the output to ground or drawing excessive current from the AD8027/AD8028 can likely cause catastrophic failure. 1.0 MSOP-10 SOT-23-6 0.5 0 -55 -35 -15 5 25 45 65 85 AMBIENT TEMPERATURE (C) 105 125 03327-A-002 Figure 3. Maximum Power Dissipation vs. Ambient Temperature Rev. C | Page 7 of 24 AD8027/AD8028 TYPICAL PERFORMANCE CHARACTERISTICS Default conditions: VS = 5 V at TA = 25C, RL = 1 k, unless otherwise noted. 2 1 VOUT = 200mV p-p AD8027 G = +1 8 G = +2 7 VOUT = 200mV p-p 6 VS = +3V NORMALIZED CLOSED-LOOP GAIN (dB) 0 CLOSED-LOOP GAIN (dB) -1 -2 -3 G = +2 -4 -5 -6 -7 -8 -9 -10 0.1 1 10 FREQUENCY (MHz) 100 1000 03327-A-003 5 4 3 2 1 0 -1 -2 -3 -4 0.1 1 VS = +5V AD8028 G = +1 G = +10 VS = 5V G = -1 10 FREQUENCY (MHz) 100 1000 03327-A-006 Figure 4. Small Signal Frequency Response for Various Gains Figure 7. Small Signal Frequency Response for Various Supplies 2 G = +1 VS = +3V RF = 24.9 1 VOUT = 200mV p-p 0 VS = +3V 2 G = +1 1 VOUT = 200mV p-p 0 VS = +3V CLOSED- LOOP GAIN (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1 1 10 FREQUENCY (MHz) VS = +5V CLOSED-LOOP GAIN (dB) -1 VS = 5V -1 -2 -3 -4 -5 -6 -7 -8 -9 VS = 5V 1 10 FREQUENCY (MHz) 100 1000 03327-A-007 VS = +5V 100 1000 03327-A-004 -10 0.1 Figure 5. AD8027 Small Signal Frequency Response for Various Supplies Figure 8. AD8028 Small Signal Frequency Response for Various Supplies 2 G = +1 1 VOUT = 2V p-p 0 VS = 5V 8 G = +2 7 VOUT = 2V p-p 6 CLOSED-LOOP GAIN (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1 1 VS = +5V VS = +3V CLOSED-LOOP GAIN (dB) -1 5 4 3 2 1 0 -1 -2 -3 VS = +3V VS = +5V VS = 5V 10 FREQUENCY (MHz) 100 1000 03327-A-005 -4 0.1 1 10 FREQUENCY (MHz) 100 1000 03327-A-008 Figure 6. Large Signal Frequency Response for Various Supplies Figure 9. Large Signal Frequency Response for Various Supplies Rev. C | Page 8 of 24 AD8027/AD8028 4 G = +1 3 VOUT = 200mV p-p 2 3 CL = 20pF G = +1 2 VOUT = 200mV p-p 1 0 CL = 5pF CL = 20pF CL = 5pF CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0.1 1 10 FREQUENCY (MHz) 100 CL = 0pF -1 -2 -3 -4 -5 -6 -7 -8 -9 CL = 0pF 1000 03327-A-009 -10 0.1 1 10 FREQUENCY (MHz) 100 1000 03327-A-012 Figure 10. AD8027 Small Signal Frequency Response for Various CLOAD Figure 13. AD8028 Small Signal Frequency Response for Various CLOAD 8 7 6 8 G = +2 VOUT = 200mV p-p 7 6 G = +2 VOUT = 0.2V p-p RL = 150 VOUT = 0.2V p-p RL = 1k CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 5 4 3 2 1 0 -1 -2 -3 -4 0.1 1 VOUT = 4V p-p VOUT = 2V p-p 5 4 3 2 1 0 -1 -2 -3 VOUT = 2.0V p-p RL = 1k 1 10 FREQUENCY (MHz) VOUT = 2.0V p-p RL = 150 10 FREQUENCY (MHz) 100 1000 03327-A-010 -4 0.1 100 1000 03327-A-013 Figure 11. Frequency Response for Various Output Amplitudes Figure 14. Small Signal Frequency Response for Various RLOAD Values 2 1 0 2 1 0 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) -1 -2 -40C -3 +125C -4 -5 -6 -7 G = +1 VOUT = 200mV p-p 1 10 FREQUENCY (MHz) 100 1000 03327-A-011 -1 -2 -3 -4 -5 -40C -6 -7 G = +1 VOUT = 200mV p-p -8 0.1 1 +125C +25C +25C 10 FREQUENCY (MHz) 100 1000 03327-A-014 -8 0.1 Figure 12. AD8027 Small Signal Frequency Response vs. Temperature Figure 15. AD8028 Small Signal Frequency Response vs. Temperature Rev. C | Page 9 of 24 AD8027/AD8028 4 G = +1 3 VOUT = 200mV p-p 2 1 100 100 VICM = VS- + 0.3V SELECT = TRI VICM = VS+ - 0.3V SELECT = HIGH CLOSED-LOOP GAI (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 0.1 1 10 FREQUENCY (MHz) 100 1000 03327-A-015 VICM = VS- + 0.2V SELECT = TRI 10 10 VOLTAGE VICM = 0V SELECT = HIGH OR TRI CURRENT 1 10 100 1k 10k 100k 1M 10M 100M 1 1G FREQUENCY (Hz) 03327-A-018 Figure 16. Small Signal Frequency Response vs. Input Common-Mode Voltages R1 50 V1 VI R2 50 + U1 + U2 VOUT 6.9 Figure 19. Voltage and Current Noise vs. Frequency 1/2 AD8028 - R3 1k 1/2 AD8028 - G = +2 6.8 RL = 150 6.7 -10 -20 -30 -40 -50 CROSSTALK = 20log (VOUT/VIN) CLOSED-LOOP GAIN (dB) VOUT = 200mV p-p 6.6 6.5 6.4 6.3 6.2 VOUT = 2V p-p 6.1 6.0 5.9 0.1 1 10 FREQUENCY (MHz) 100 1000 03327-A-019 CROSSTALK (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.001 0.01 0.1 1 10 FREQUENCY (MHz) G = +1 VS = 5V RL = 1k 100 1000 03327-A-016 B TO A A TO B Figure 20. 0.1 dB Flatness Frequency Response Figure 17. AD8028 Crosstalk Output to Output 110 100 90 80 95 GAIN 135 115 -20 G = +1 VOUT = 2V p-p RL = 1k -40 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE OPEN-LOOP GAIN (dB) 60 50 40 35 30 20 10 -5 0 -10 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M -25 1G 15 55 DISTORTION (dB) 75 PHASE (Degrees) 70 PHASE -60 VS = +3V -80 VS = +5V -100 -120 VS = 5V -140 0.1 03327-A-017 1 FREQUENCY (MHz) 10 20 03327-A-020 Figure 18. Open-Loop Gain and Phase vs. Frequency Rev. C | Page 10 of 24 Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) VICM = VS+ - 0.2V SELECT = HIGH AD8027/AD8028 -20 G = +1 (RF = 24.9) FREQUENCY = 100kHz RL = 1k -45 -55 -65 G = +1 (RF = 24.9) VOUT = 1.0V p-p @ 2MHz SELECT = TRI SELECT = HIGH -40 DISTORTION (dB) -60 VS = +3V -80 DISTORTION (dB) VS = +5V VS = 5V -75 -85 -95 -105 -100 -120 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE -140 0 1 2 3 4 5 6 7 OUTPUT VOLTAGE (V p-p) 8 9 10 03327-A-021 -115 -125 0.5 SELECT = TRI SELECT = HIGH SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 1.0 1.5 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) 4.0 4.5 03327-A-024 Figure 22. Harmonic Distortion vs. Output Amplitude Figure 25. Harmonic Distortion vs. Input Common-Mode Voltage, VS = 5 V -50 -60 -70 VS = +3V G = +1 (RF = 24.9) VOUT = 1.0V p-p @ 100kHz RL = 1k -50 -60 VS = +5V G = +1 (RF = 24.9) VOUT = 1.0V p-p @ 100kHz VS = +3V VS = +5V -70 -80 -90 -100 -110 -120 -130 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 1.0 1.5 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) 4.0 4.5 DISTORTION (dB) -90 -100 -110 -120 -130 -140 0.5 DISTORTION (dB) -80 -140 0.5 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 1.0 1.5 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) 4.0 4.5 03327-A-022 03327-A-025 Figure 23. Harmonic Distortion vs. Input Common-Mode Voltage, SELECT = High -20 G = +1 (RF = 24.9) VOUT = 2.0V p-p SECOND HARMONIC: SOLID LINE -40 THIRD HARMONIC: DASHED LINE RL = 1k Figure 26. Harmonic Distortion vs. Input Common-Mode Voltage, SELECT = Three-State or Open -20 VS = +5 VOUT = 2.0V p-p SECOND HARMONIC: SOLID LINE -40 THIRD HARMONIC: DASHED LINE G = +2 DISTORTION (dB) DISTORTION (dB) -60 -60 G = +10 -80 G = +1 -80 RL = 150 -100 -100 -120 -120 -140 0.1 1 FREQUENCY (MHz) 10 20 -140 0.1 03327-A-023 1 FREQUENCY (MHz) 10 20 03327-A-026 Figure 24. Harmonic Distortion vs. Frequency and Load Figure 27. Harmonic Distortion vs. Frequency and Gain Rev. C | Page 11 of 24 AD8027/AD8028 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 50mV/DIV 20ns/DIV 0.20 G = +1 VS = 2.5V 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 50mV/DIV 20ns/DIV 03327-A-030 G = +1 VS = 2.5V CL = 20pF CL = 5pF -0.20 03327-A-027 -0.20 Figure 28. Small Signal Transient Response Figure 31. Small Signal Transient Response with Capacitive Load 2.0 G = +1 VS = 2.5V VOUT = 4V p-p VOUT = 2V p-p 1.0 0 -1.0 -2.0 500mV/DIV 100ns/DIV 03327-A-028 4.0 G = -1 3.5 RL = 1k 3.0 V = 2.5V S 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 500mV/DIV -4.0 50ns/DIV 03327-A-031 Figure 29. Large Signal Transient Response, G = +1 Figure 32. Output Overdrive Recovery 2.5 G = +2 2.0 VS = 2.5V 1.5 VOUT = 2V p-p 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 50mV/DIV 20ns/DIV 03327-A-029 VOUT = 4V p-p -2.5 4.0 G = +1 3.5 RL = 1k 3.0 V = 2.5V S 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 500mV/DIV -4.0 50ns/DIV 03327-A-032 Figure 30. Large Signal Transient Response, G = +2 Figure 33. Input Overdrive Recovery Rev. C | Page 12 of 24 AD8027/AD8028 -10 -8 G = +2 -6 INPUT BIAS CURRENT (A) SELECT = TRI VIN (200mV/DIV) -4 -2 VS = +5V 0 2 4 VS = +3V 6 8 SELECT = HIGH VS = 5V +0.1% VOUT - 2VIN (2mV/DIV) -0.1% 5s/DIV 03327-A-033 10 0 1 2 3 4 5 6 7 8 INPUT COMMON-MODE VOLTAGE (V) 9 10 03327-A-036 Figure 34. Long-Term Settling Time Figure 37. Input Bias Current vs. Input Common-Mode Voltage 250 COUNT = 1780 SELECT HIGH MEAN 49V STD. DEV 193V TRI 55V 150V SELECT = TRI VIN (200mV/DIV) 200 FREQUENCY VOUT (400mV/DIV) +0.1% 150 SELECT = HIGH 100 VOUT - 2VIN (0.1%/DIV) -0.1% 50 20ns/DIV 03327-A-034 0 -800 -600 -400 -200 0 200 400 600 800 INPUT OFFSET VOLTAGE (V) 03327-A-037 Figure 35. 0.1% Short-Term Settling Time Figure 38. Input Offset Voltage Distribution 4.5 INPUT BIAS CURRENT (SELECT = HIGH) (A) -6.5 INPUT BIAS CURRENT (SELECT = TRI) (A) 360 340 320 300 INPUT OFFSET VOLTAGE (V) 4.0 SELECT = HIGH -7.0 280 260 240 220 200 180 160 140 120 100 80 60 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 VS = +5V SELECT = TRI VS = 5V VS = +3V SELECT = HIGH 3.5 VS = 5V VS = +3V VS = +5V -7.5 3.0 SELECT = TRI -8.0 2.5 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 -8.5 125 03327-A-035 03327-A-038 Figure 36. Input Bias Current vs. Temperature Figure 39. Input Offset Voltage vs. Temperature Rev. C | Page 13 of 24 AD8027/AD8028 290 VS = 5V 270 120 100 SELECT = HIGH INPUT OFFSET VOLTAGE (V) 250 80 230 CMRR (dB) 60 210 SELECT = TRI 190 40 170 20 150 -5 -4 -3 -2 -1 0 1 2 3 INPUT COMMON-MODE VOLTAGE (V) 4 5 0 1k 10k 03327-A-039 100k 1M FREQUENCY (Hz) 10M 100M 03327-A-042 Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5 Figure 43. CMRR vs. Frequency 290 VS = +5V 270 0 -10 -20 INPUT OFFSET VOLTAGE (V) 250 -30 SELECT = HIGH -40 -PSRR -50 -60 -70 -80 -90 +PSRR 210 SELECT = TRI 190 170 -100 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 INPUT COMMON-MODE VOLTAGE (V) 4.5 5.0 03327-A-040 PSSR (dB) 230 -110 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 03327-A-043 Figure 41. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5 Figure 44. PSRR vs. Frequency 270 VS = +3V 250 INPUT OFFSET VOLTAGE (V) -20 VIN = 0.2V p-p G = +1 -30 SELECT = LOW -40 OFF ISOLATION (dB) SELECT = HIGH 230 -50 -60 -70 -80 210 SELECT = TRI 190 170 -90 -100 10k 150 0 0.50 1.00 1.50 2.00 2.50 3.00 INPUT COMMON-MODE VOLTAGE (V) 03327-A-041 100k 1M 10M FREQUENCY (Hz) 100M 1G 03327-A-044 Figure 42. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 3 Figure 45. Off Isolation vs. Frequency Rev. C | Page 14 of 24 AD8027/AD8028 200 150 100 OPEN-LOOP GAIN (dB) 130 LOAD RESISTANCE TIED TO MIDSUPPLY 120 5V +5V 100 +3V 90 OUTPUT SATURATION VOLTAGE (mV) 110 50 0 -50 -100 -150 -200 100 VS = +3V VS = +5V VS = 5V VOL - VS- VOH - VS+ 80 70 60 1000 LOAD RESISTANCE () 10000 03327-A-045 0 10 20 30 ILOAD (mA) 40 50 60 03327-A-048 Figure 46. Output Saturation Voltage vs. Output Load Figure 49. Open-Loop Gain vs. Load Current 100 1M SELECT = LOW 10 100k OUTPUT IMPEDANCE () 1 OUTPUT IMPEDANCE () G = +5 10k 0.1 G = +2 G = +1 0.01 1k 100 0.001 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 10 100k 1M 03327-A-046 10M FREQUENCY (Hz) 100M 1G 03327-A-049 Figure 47. Output Enabled-- Impedance vs. Frequency Figure 50. Output Disabled--Impedance vs. Frequency 45 VS = +5V RL = 1k TIED TO MIDSUPPLY 80 VS = +5V 60 40 VS = +10V @ +25C +25C 20 -40C 0 -20 -40 -60 +125C OUTPUT SATURATION VOLTAGE (mV) 40 SELECT CURRENT (A) VOL - VS- 35 VS+ - VOH 30 25 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 -80 0 0.5 1.0 1.5 2.0 SELECT VOLTAGE (V) 2.5 3.0 03327-A-050 03327-A-047 Figure 48. Output Saturation Voltage vs. Temperature Figure 51. SELECT Pin Current vs. SELECT Pin Voltage and Temperature Rev. C | Page 15 of 24 AD8027/AD8028 1.5 SELECT PIN (-2.0V TO -0.5V) 1.0 OUTPUT SUPPLY CURRENT (mA) 9.0 8.5 8.0 7.5 7.0 VS = +5V 6.5 6.0 5.5 5.0 G = -1 VS = 2.5V VIN = -1.0V 0 50 100 150 TIME (ns) 200 250 03327-A-051 OUTPUT VOLTAGE (V) 0.5 RL = 100 RL = 1k -0.5 RL = 10k -1.0 VS = 5V 0 VS = +3V 4.5 4.0 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 -1.5 03327-A-053 Figure 52. Enable Turn-On Timing Figure 54. Quiescent Supply Current vs. Supply Voltage and Temperature 1.5 SELECT PIN (-2.0V TO -0.5V) 1.0 OUTPUT OUTPUT VOLTAGE (V) 0.5 RL = 100 RL = 1k -0.5 RL = 10k -1.0 G = -1 VS = 2.5V VIN = -1.0V 2 3 4 5 6 TIME (s) 7 8 9 10 0 -1.5 0.5 1 03327-A-052 Figure 53. Disable Turn-Off Timing Rev. C | Page 16 of 24 AD8027/AD8028 THEORY OF OPERATION The AD8027/AD8028 are rail-to-rail input/output amplifiers designed in the Analog Devices XFCB process. The XFCB process enables the AD8027/AD8028 to run on 2.7 V to 12 V supplies with 190 MHz of bandwidth and over 100 V/s of slew rate. The AD8027/AD8028 have 4.3 nV/Hz of wideband noise with 17 nV/Hz noise at 10 Hz. This noise performance, with an offset and drift performance of less than 900 V maximum and 1.5 V/C typical, respectively, makes the AD8027/AD8028 ideal for high speed, precision applications. Additionally, the input stage operates 200 mV beyond the supply rails and shows no phase reversal. The amplifiers feature overvoltage protection on the input stage. Once the inputs exceed the supply rails by 0.7 V, ESD protection diodes are turned on, drawing excessive current through the differential input pins. A series input resistor should be included to limit the input current to less than 10 mA. The NPN input pair can now operate at 200 mV above the positive rail. Both input pairs are protected from differential input signals above 1.4 V by four diodes across the input (see Figure 55). In the event of differential input signals that exceed 1.4 V, the diodes conduct and excessive current flows through them. A series input resistor should be included to limit the input current to 10 mA. CROSSOVER SELECTION The AD8027/AD8028 have a feature called crossover selection, which allows the user to choose the crossover point between the PNP/NPN differential pairs. Although the crossover region is small, operating in this region should be avoided, because it can introduce offset and distortion to the output signal. To help avoid operating in the crossover region, the AD8027/AD8028 allow the user to select from two preset crossover locations (voltage levels) using the SELECT pin. As shown in Figure 55, the crossover region is about 200 mV and is defined by the voltage level at the base of Q5. Internally, two separate voltage sources are created approximately 1.2 V from either rail. One or the other is connected to Q5, based on the voltage applied to the SELECT pin. This allows either dominant PNP pair operation, when the SELECT pin is left open, or dominant NPN pair operation, when the SELECT pin is pulled high. The SELECT pin also provides the traditional power-down function when it is pulled low. This allows the designer to achieve the best precision and ac performance for high-side and low-side signal applications. See Figure 50 through Figure 53 for SELECT pin characteristics. INPUT STAGE The rail-to-rail input performance is achieved by operating complementary input pairs. Which pair is on is determined by the common-mode level of the differential input signal. As shown in Figure 55, a tail current (ITAIL) is generated that sources the PNP differential input structure consisting of Q1 and Q2. A reference voltage is generated internally that is connected to the base of Q5. This voltage is continually compared against the common-mode input voltage. When the common-mode level exceeds the internal reference voltage, Q5 diverts the tail current (ITAIL) from the PNP input pair to a current mirror that sources the NPN input pair consisting of Q3 and Q4. VCC + 1.2V - ITAIL VOUTP ICMFB Q5 VSEL LOGIC VP Q3 Q1 Q2 Q4 VN VEE VOUTN VCC ICMFB + 1.2V - VEE 03327-A-054 Figure 55. Simplified Input Stage Rev. C | Page 17 of 24 AD8027/AD8028 In the event that the crossover region cannot be avoided, specific attention has been given to the input stage to ensure constant transconductance and minimal offset in all regions of operation. The regions are PNP input pair running, NPN input pair running, and both running at the same time (in the 200 mV crossover region). Maintaining constant transconductance in all regions ensures the best wideband distortion performance when going between these regions. With this technique, the AD8027/AD8028 can achieve greater than 80 dB SFDR for a 2 V p-p, 1 MHz, and G = 1 signal on 1.5 V supplies. Another requirement needed to achieve this level of distortion is that the offset of each pair must be laser trimmed to achieve greater than 80 dB SFDR, even for low frequency signals. The size of the discontinuity is defined as R + RF VDIS = VOS, PNP - VOS, NPN x G R G ( ) Using the crossover select feature of the AD8027/AD8028 helps to avoid this region. In the event that the region cannot be avoided, the quantity (VOS, PNP - VOS, NPN) is trimmed to minimize this effect. Because the input pairs are complementary, the input bias current reverses polarity when going through the crossover region shown in Figure 37. The offset between pairs is described by OUTPUT STAGE The AD8027/AD8028 use a common-emitter output structure to achieve rail-to-rail output capability. The output stage is designed to drive 50 mA of linear output current, 40 mA within 200 mV of the rail, and 2.5 mA within 35 mV of the rail. Loading of the output stage, including any possible feedback network, lowers the open-loop gain of the amplifier. Refer to Figure 49 for the loading behavior. Capacitive load can degrade the phase margin of the amplifier. The AD8027/AD8028 can drive up to 20 pF, G = 1, as shown in Figure 10. A small (25 to 50 ) series resistor, RSNUB, should be included, if the capacitive load is to exceed 20 pF for a gain of 1. Increasing the closed-loop gain increases the amount of capacitive load that can be driven before a series resistor needs to be included. B R + RF - RF VOS,PNP - VOS,NPN = I B, PNP - I B, NPN x RS G RG IB, PNP is the input bias current of either input when the PNP input pair is active, and IB, NPN is the input bias current of either input pair when the NPN pair is active. If RS is sized so that when multiplied by the gain factor it equals RF, this effect is eliminated. It is strongly recommended to balance the impedances in this manner when traveling through the crossover region to minimize the dc error and distortion. As an example, assuming that the PNP input pair has an input bias current of 6 A and the NPN input pair has an input bias current of -2 A, a 200 V shift in offset occurs when traveling through the crossover region with RF equal to 0 and RS equal to 25 . In addition to the input bias current shift between pairs, each input pair has an input bias current offset that contributes to the total offset in the following manner: R + RF VOS = I B + RS G R G RF +V - IB- - VI + RS IB + - VOUT + - ( ) DC ERRORS The AD8027/AD8028 use two complementary input stages to achieve rail-to-rail input performance, as mentioned in the Input Stage section. To use the dc performance over the entire common-mode range, the input bias current and input offset voltage of each pair must be considered. Referring to Figure 56, the output offset voltage of each pair is calculated by R + RF VOS , PNP ,OUT = VOS , PNP G R G , - I B - RF RG + VOS AD8027/ AD8028 + -V SELECT R + RF VOS , NPN ,OUT = VOS , NPN G R G 03327-A-055 Figure 56. Op Amp DC Error Sources where the difference of the two is the discontinuity experienced when going through the crossover region. Rev. C | Page 18 of 24 AD8027/AD8028 WIDEBAND OPERATION Voltage feedback amplifiers can use a wide range of resistor values to set their gain. Proper design of the application's feedback network requires consideration of the following issues: * * * * CF RF +V C1 0.1F C2 10F - Poles formed by the amplifier's input capacitances with the resistances seen at the amplifier's input terminals Effects of mismatched source impedances Resistor value impact on the application's voltage noise Amplifier loading effects C5 R1 VIN RG R1 = RF||RG AD8027/ AD8028 + C3 10F C4 0.1F SELECT VOUT The AD8027/AD8028 have an input capacitance of 2 pF. This input capacitance forms a pole with the amplifier's feedback network, destabilizing the loop. For this reason, it is generally desirable to keep the source resistances below 500 , unless some capacitance is included in the feedback network. Likewise, keeping the source resistances low also takes advantage of the AD8027/AD8028's low input referred voltage noise of 4.3 nV/Hz. With a wide bandwidth of over 190 MHz, the AD8027/AD8028 have numerous applications and configurations. The AD8027/ AD8028 part shown in Figure 57 is configured as a noninverting amplifier. An easy selection table of gain, resistor values, bandwidth, slew rate, and noise performance is presented in Table 5, and the inverting configuration is shown in Figure 58. RF +V C1 0.1F C2 10F - -V 03327-A-057 Figure 58. Wideband Inverting Gain Configuration CIRCUIT CONSIDERATIONS Balanced Input Impedances Balanced input impedances can help to improve distortion performance. When the amplifier transitions from PNP pair to NPN pair operation, a change in both the magnitude and direction of the input bias current occurs. When multiplied times imbalanced input impedances, a change in offset can result. The key to minimizing this distortion is to keep the input impedances balanced on both inputs. Figure 59 shows the effect of the imbalance and degradation in distortion performance for a 50 source impedance, with and without a 50 balanced feedback path. RG -20 VIN R1 AD8027/ AD8028 + SELECT C3 10F C4 0.1F VOUT G = +1 VOUT = 2V p-p -30 RL = 1k VS = +3V -40 DISTORTION (dB) -50 -60 RF = 0 -70 RF = 24.9 -80 R1 = RF||RG -V 03327-A-056 Figure 57. Wideband Noninverting Gain Configuration -90 Table 5. Component Values, Bandwidth, and Noise Performance (VS = 2.5 V) -3 dB SS BW (MHz) 190 95 13 Output Noise with Resistors (nV/Hz) 4.4 10 45 RF = 49.9 -100 0.1 1 FREQUENCY (MHz) 10 20 03327-A-058 Figure 59. SFDR vs. Frequency and Various RF Noise Gain (Noninverting) 1 2 10 RSOURCE () 50 50 50 RF () 0 499 499 RG () N/A 499 54.9 Rev. C | Page 19 of 24 AD8027/AD8028 PCB Layout As with all high speed op amps, achieving optimum performance from the AD8027/AD8028 requires careful attention to PCB layout. Particular care must be exercised to minimize lead lengths of the bypass capacitors. Excess lead inductance can influence the frequency response and even cause high frequency oscillations. The use of a multilayer board with an internal ground plane can reduce ground noise and enable a tighter layout. To achieve the shortest possible lead length at the inverting input, the feedback resistor, RF, should be located beneath the board and span the distance from the output, Pin 6, to the input, Pin 2. The return node of the resistor, RG, should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to Pin 4. On multilayer boards, all layers underneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. This is especially true at the summing junction (the -input). Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin. The length of the high frequency bypass capacitor pads and traces is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Power-Supply Bypassing Power-supply pins are actually inputs, and care must be taken to provide a clean, low noise, dc voltage source to these inputs. The bypass capacitors have two functions: * Provide a low impedance path for unwanted frequencies from the supply inputs to ground, thereby reducing the effect of noise on the supply lines. Provide sufficient localized charge storage, for fast switching conditions and minimizing the voltage drop at the supply pins and the output of the amplifier. This is usually accomplished with larger electrolytic capacitors. * Grounding To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and, therefore, the high frequency impedance of the path. Fast current changes in an inductive ground return can create unwanted noise and ringing. Decoupling methods are designed to minimize the bypassing impedance at all frequencies. This can be accomplished with a combination of capacitors in parallel to ground. Good-quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package . A parallel combination of a 0.01 F ceramic and a 10 F electrolytic covers a wide range of rejection for unwanted noise. The 10 F capacitor is less critical for high frequency bypassing, and, in most cases, one per supply line is sufficient. Rev. C | Page 20 of 24 AD8027/AD8028 APPLICATIONS USING THE SELECT PIN The AD8027/AD8028's unique SELECT pin has two functions: * In this application, the SELECT pins are biased to avoid the crossover region of the AD8028 for low distortion operation. Summary test data for the schematic shown in Figure 60 is listed in Table 8. The power-down function places the AD8027/AD8028 into low power consumption mode. In power-down mode, the amplifiers draw 450 A (typical) of supply current. The second function, as mentioned in the Theory of Operation section, shifts the crossover point (where the NPN/PNP input differential pairs transition from one to the other) closer to either the positive supply rail or the negative supply rail. This selectable crossover point allows the user to minimize distortion based on the input signal and environment. The default state is 1.2 V from the positive power supply, with the SELECT pin left floating or in three-state. * +5V 0.1F - 15 4MHz LPF +5V 2.7nF AD8028 ANALOG INPUT + INPUT RANGE (0.15V TO 2.65V) + SELECT (OPEN) +5V - AD7677 0.1F 15 16 BITS Table 6 lists the SELECT pin's required voltages and modes. Table 6. SELECT Pin Mode Control Mode Disable Crossover Referenced -1.2 V to Positive Supply Crossover Referenced +1.2 V to Negative Supply SELECT Pin Voltage (V) VS = 5 V VS = +5 V VS = +3 V -5 to -4.2 0 to 0.8 0 to 0.8 0.8 to 1.7 0.8 to 1.7 -4.2 to -3.3 -3.3 to +5 1.7 to 5.0 1.7 to 3.0 ANALOG INPUT - AD8028 + 2.7nF 4MHz LPF SELECT (OPEN) 03327-A-059 Figure 60. Unity Gain Differential Drive Table 8. ADC Driver Performance, fC = 100 kHz, VOUT = 4.7 V p-p Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR Measurement -105 dB -102 dB -102 dB +105 dBc When the input stage transitions from one input differential pair to the other, there is virtually no noticeable change in the output waveform. The disable time of the AD8027/AD8028 amplifiers is loaddependent. Typical data is presented in Table 7. See Figure 52 and Figure 53 for the actual switching measurements. Table 7. DISABLE Switching Speeds Time tON tOFF 5 V 45 ns 980 ns Supply Voltages (RL = 1 k) +5 V +3 V 50 ns 50 ns 1100 ns 1150 ns As shown in Figure 61, the AD8028 and AD7677 combination offers excellent integral nonlinearity (INL). 1.0 0.5 INL (LSB) 0 DRIVING A 16-BIT ADC With the adjustable crossover distortion selection point and low noise, the AD8028 is an ideal amplifier for driving or buffering input signals into high resolution ADCs such as the AD7767, a 16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 60 shows the typical schematic for driving the ADC. The AD8028 driving the AD7677 offers performance close to non-rail-to-rail amplifiers and avoids the need for an additional supply other than the single 5 V supply already used by the ADC. -0.5 -1.0 0 16384 32768 CODE 49152 65536 03327-A-060 Figure 61. Integral Nonlinearity Rev. C | Page 21 of 24 AD8027/AD8028 BAND-PASS FILTER In communication systems, active filters are used extensively in signal processing. The AD8027/AD8028 are excellent choices for active filter applications. In realizing this filter, it is important that the amplifier have a large signal bandwidth of at least 10x the center frequency, fO. Otherwise, a phase shift can occur in the amplifier, causing instability and oscillations. In Figure 62, the AD8027/AD8028 part is configured as a 1 MHz band-pass filter. The target specifications are fO = 1 MHz and a -3 dB pass band of 500 kHz. To start the design, select fO, Q, C1, and R4. Then use the following equations to calculate the remaining variables: Q= f O (MHz) Band Pass (MHz) 0.1 1 FREQUENCY - MHz 10 03327-A-062 The test data shown in Figure 63 indicates that this design yields a filter response with a center frequency of fO = 1 MHz, and a bandwidth of 450 kHz. CH1 S21 LOG 5dB/REF 6.342dB 1:6.3348dB 1.00 000MHz 1 k = 2fOC1 C2 = 0.5C1 R1 = 2/k, R2 = 2/(3k), R3 = 4/k H = 1/3(6.5 - 1/Q) R5 = R4/(H - 1) R2 105 R1 316 C1 1000pF + C2 500pF R3 634 +5 C3 0.1F Figure 63. Band-Pass Filter Response DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices, Inc. (ADI) is committed to simplifying the design process by providing technical support and online design tools. ADI offers technical support via free evaluation boards, sample ICs, interactive evaluation tools, data sheets, spice models, application notes, and phone and email support available at www. analog.com. VOUT SELECT C4 -5 0.1F VIN AD8027/ AD8028 - R5 523 R4 523 03327-A-061 Figure 62. Band-Pass Filter Schematic Rev. C | Page 22 of 24 AD8027/AD8028 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) x 45 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 64. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.90 BSC 6 5 4 1.60 BSC 1 2 3 2.80 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.22 0.08 10 4 0 0.60 0.45 0.30 0.15 MAX 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178AB Figure 65. 6-Lead Small Outline Transistor Package [SOT-23] (RT-6) Dimensions shown in millimeters 3.00 BSC 10 6 3.00 BSC 1 5 4.90 BSC PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40 SEATING PLANE 0.23 0.08 Figure 66. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. C | Page 23 of 24 AD8027/AD8028 ORDERING GUIDE Model AD8027AR AD8027AR-REEL AD8027AR-REEL7 AD8027ARZ 1 AD8027ARZ-REEL1 AD8027ARZ-REEL71 AD8027ART-R2 AD8027ART-REEL AD8027ART-REEL7 AD8027ARTZ-R21 AD8027ARTZ-REEL1 AD8027ARTZ-REEL71 AD8028AR AD8028AR-REEL AD8028AR-REEL7 AD8028ARZ1 AD8028ARZ-REEL1 AD8028ARZ-REEL71 AD8028ARM AD8028ARM-REEL AD8028ARM-REEL7 AD8028ARMZ1 AD8028ARMZ-REEL1 AD8028ARMZ-REEL71 Minimum Ordering Quantity 1 2,500 1,000 1 2,500 1,000 250 10,000 3,000 250 10,000 3,000 1 2,500 1,000 1 2,500 1,000 1 3,000 1,000 1 3,000 1,000 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Package Option R-8 R-8 R-8 R-8 R-8 R-8 RT-6 RT-6 RT-6 RT-6 RT-6 RT-6 R-8 R-8 R-8 R-8 R-8 R-8 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding H4B H4B H4B H4B# H4B# H4B# H5B H5B H5B H5B# H5B# H5B# 1 Z = Pb-free part, # denotes lead-free, may be top or bottom marked. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03327-0-3/05(C) Rev. C | Page 24 of 24 |
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