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EL5000A
Data Sheet February 20, 2008 FN6167.2
High Voltage TFT-LCD Logic Driver
The EL5000A is high voltage TFT-LCD logic driver with +40V and -30V output swing capability. Manufactured using the Intersil proprietary monolithic high voltage bipolar process, it is capable of delivering 100mA output peak current into 5nF of capacitive load. To simplify external circuitry, the EL5000A integrates additional logic circuits. The EL5000A can operate on 3.3V logic supply and high voltage -30V to +40V output supplies. The EL5000A is available in a 16 Ld TSSOP. It is specified for operation over the -20C to +85C extended temperature range.
Features
* 3.3V logic supply * 40V VON output high level * -30V VOFF output low level * 166kHz input logic frequency * 100mA output peak current * 10mA output continuous current * TTL-compatible logic input * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) EL5000AERZ EL5000AERZ-T7* PART MARKING 5000AER Z 5000AER Z PACKAGE (Pb-free) PKG. DWG. #
Applications
* TFT-LCD panels
Pinout
EL5000A (16 LD TSSOP) TOP VIEW
VON 1 CKV 2 CKVCS 3 NC 4 CKVBCS 5 CKVB 6 STVP 7 VOFF 8 16 VDD 15 DISH 14 OECON 13 GND 12 STV 11 OE 10 CPV 9 GND
16 Ld TSSOP MDP0044 16 Ld TSSOP MDP0044 16 Ld TSSOP MDP0044
EL5000AERZ-T13* 5000AER Z
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5000A
Absolute Maximum Ratings (TA = +25C)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V VON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V VOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -33V VCKV, VCKVB, VSTVP, VCKVCS, VCKVBCS . . . . . . . . . . . . . . . . . .VON + 0.3V /VOFF - 0.3V VCPV, VOE, VSTV, VOECON . . . . . . . . . . . VDD + 0.3V /GND - 0.3V VDISH . . . . . . . . . . . . . . . . . . . . . . . . . . . GND + 0.3V /VOFF - 0.3V IOUT (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA IOUT (continuous), CKV, CKVB, or STVP . . . . . . . . . . . . . . . . 30mA IOUT (continuous, total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Information
TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20C to +85C TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20C to +150C TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C PDISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER IVDD
VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF load on STV, CKV, CKVB, unless otherwise specified. CONDITION All inputs low CPV = 3.1V, other inputs low 0.7 MIN (Note 1) TYP 1.1 1.5 0.25 0.2 0.45 0.25 -1.25 25 -1 20 -1 -1 200 -1 -40 -1 19.1 -13.1 19.1 -13.1 19.0 -13.1 -0.7 130 0 60 0 0 450 0 -25 0 19.3 -13.3 19.3 -13.3 19.2 -13.3 3 1.5 0.3 0.5 0.3 0.5 1.2 0.5 0.75 0.5 0.75 1.6 0.7 1 0.7 1 2.4 -0.30 180 1 90 1 1 700 1 -5 1 19.5 -13.5 19.5 -13.5 19.4 -13.5 0.9 2.5 MAX (Note 1) UNIT mA mA mA mA mA mA A A A A A A A A A V V V V V V k pF s s s s s
DESCRIPTION VDD Supply Current
IVON
VON Supply Current
All inputs low CPV = 3.1V, other inputs low
IVOFF
VOFF Supply Current
All inputs low CPV = 3.1V, other inputs low
ISTV
STV Input Current
STV = 3.1V STV = 0.2V
ICPV
CPV Input Current
CPV = 3.1V CPV = 0.2V
IOE
OE Input Current
OE = 0.2V OE = 3.1V, OECON = 0.2V OE = 3.1V, OECON = 3.1V
IOECON
OECON Input Current
OECON - 0.2V, OE = 3.1V OECON - 0.2V, OE = 0.2V
VCKV+ VCKV VCKVB+ VCKVB VSTVP+ VSTVP RIN CIN tR-CKV tF-CKV tR-CKVB tF-CKVB tR-STVP
CKV Positive Output Swing CKV Negative Output Swing CKVB Positive Output Swing CKVB Negative Output Swing STVP Positive Output Swing STVP Negative Output Swing CPV, OE, STV Input Resistance CPV, OE, STV Input Capacitance CKV Rise Time CKV Fall Time CKVB Rise Time CKVB Fall Time STVP Rise Time
VON = +20V, 1mA output current VOFF = -14V, 1mA output current VON = +20V, 1mA output current VOFF = -14V, 1mA output current VON = +20V, 1mA output current VOFF = -14V, 1mA output current
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FN6167.2 February 20, 2008
EL5000A
Electrical Specifications
PARAMETER tF-STVP tD-CKV+ tD-CKVtD-CKVB+ tD-CKVBtD-STVP+ tD-STVPtD-CKV_CS+ tD-CKV_CStD-CKVB_CS+ tD-CKVB_CSNOTE: 1. Parts are 100% tested at +25C. Temperature limits established by characterization and are not production tested. VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF load on STV, CKV, CKVB, unless otherwise specified. (Continued) CONDITION MIN (Note 1) 1.2 0.5 0.7 0.5 0.7 1.3 1.2 1.6 3.4 1.6 3.4 TYP 1.6 0.9 1.1 0.9 1.1 1.75 1.7 2.3 4.1 2.3 4.1 MAX (Note 1) 2.4 1.3 1.5 1.3 1.5 2.2 2 2.9 4.8 2.9 4.8 UNIT s s s s s s s s s s s
DESCRIPTION STVP Fall Time CKV Rising Edge Delay Time CKV Falling Edge Delay Time CKVB Rising Edge Delay Time CKVB Falling Edge Delay Time STVP Rising Edge Delay Time STVP Falling Edge Delay Time CKV_CS Rising Edge Delay Time CKV_CS Falling Edge Delay Time CKVB_CS Rising Edge Delay Time CKVB_CS Falling Edge Delay Time
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FN6167.2 February 20, 2008
EL5000A Timing Diagram
TD-CKV+ TD-CKV_CSTD-CKV-
+20V
+17V TD-CKV_CS+ +10V
CKV -14V -11V
-4V -14V
CPV
50% OF VDD
+20V
+20V
+17V +10V CKVB TD-CKVB_CS-4V -14V -11V TD-CKVB+
TD-CKVB-
TD-CKVB_CS+
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FN6167.2 February 20, 2008
EL5000A Typical Performance Curves
1.50 1.25 1.00 IVCC (mA) IVON (A) 300 0.75 0.50 0.25 0 0 1 2 VCC (V) 3 4 5 100 VON = 20V VOFF = -14V 400 CPV INPUT HIGH 500 VCC = 3.3V VOFF = -14V
200
ALL INPUTS LOW
0 0 10 20 30 40 50 VON (V)
FIGURE 1. VSS SUPPLY CURRENT vs VCC
FIGURE 2. VON DC SUPPLY CURRENT vs VON
800
1.50 CPV INPUT HIGH 1.25 1.00 0.75 0.50 0.25 0 0 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 1k 2k 3k 4k 5k RISE VON = 20V VOFF = -14V FALL DELAY (s) ALL INPUTS LOW VCC = 3.3V VON = 20V -30 -25 -20 -15 -10 -5 0 VOFF (V)
600 IVOFF (A)
400
200
0 -35
LOAD CAPACITANCE (pF)
FIGURE 3. VOFF DC SUPPLY CURRENT vs VOFF
FIGURE 4. CLOCK DELAY vs LOAD CAPACITOR
1.50 1.25 1.00 0.75 0.50 0.25 0 0 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 1k 2k 3k 4k 5k VON = 40V VOFF = -20V FALL DELAY (s) DELAY (s)
1.50 1.25 1.00 RISE 0.75 0.50 0.25 4.7nF LOAD CAPACITORS 0 -25 25 VON = 20V VOFF = -14V FALL
RISE
75
125
LOAD CAPACITANCE (pF)
AMBIENT TEMPERATURE (C)
FIGURE 5. CLOCK DELAY vs LOAD CAPACITOR
FIGURE 6. CLOCK DELAY vs TEMPERATURE
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FN6167.2 February 20, 2008
EL5000A Typical Performance Curves (Continued)
1.4 VCC = 3.3V VON = 20V VOFF = -14V 1.2 IVCC (mA) 1k VCC = 3.3V VON = 20V VOFF = -14V
SUPPLY CURRENT (A)
800
IVO
FF , CPV HIGH
600
IVO
1.0
N, CPV
HIGH
400
IVOFF, INPUTS LOW
0.8
200
IVON, INPUTS LOW
0.6 -25
25
75
125
0 -25
25
75
125
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 7. VCC SUPPLY CURRENT vs TEMPERATURE
FIGURE 8. DC SUPPLY CURRENTS vs TEMPERATURE
500 400 INPUT CURRENT (A) 300 200 100 0 -100 -25
CPV INPUT, 3.3V
750
OE INPUT, 3.3V
HEADROOM (mV)
500
STV INP
UT, 3.3V
250
OECON INPUT, 0.2V
CKV, CKVB, AND STVP OUTPUTS 5mA LOAD 75 125 0 -25 25 75 125
25
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 9. INPUT BIAS CURRENTS vs TEMPERATURE
FIGURE 10. OUTPUT SWING HEADROOM vs TEMPERATURE
1400 POWER DISSIPATION (mW) POWER DISSIPATION (mW) VON = 40V 1200 VOFF = -20V RCS = 500 1000 800 600 400 200 0 0 50 100 150 200 INPUT FREQUENCY (kHz) 220pF 4700pF 1000pF
800 VON = 20V VOFF = -14V RCS = 500 600
400 4700pF 200 1000pF 220pF 0 0 50 100 150 200 INPUT FREQUENCY (kHz)
FIGURE 11. POWER CONSUMPTION vs FREQUENCY AND LOAD
FIGURE 12. POWER CONSUMPTION vs FREQUENCY AND LOAD
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FN6167.2 February 20, 2008
EL5000A Typical Performance Curves (Continued)
1.2 POWER DISSIPATION (W) 1.0 845mW 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
TS =+
JA
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.8 1.6 POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.4 1.289W 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
JA =
SO
14
P1
6 W
8
C/
TS SO P +9 16 7 C/ W
FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Pin Descriptions
PIN NUMBER (16 LD TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME VON CKV CKVCS NC CKVBCS CKVB STVP VOFF GND CPV OE STV GND OECON DISH VDD Positive supply High voltage output, scan clock out Discharge switch input, CKV charge share No connect Discharge switch input, CKVB charge share High voltage output, scan clock even High voltage output, scan start pulse Negative supply Ground H sync timing, H sync clock 1 Writing timing, H sync clock 2 V sync timing, V sync Ground, logic return OE disable input, OE blank Discharge function input, VOFF discharge Logic power supply PIN FUNCTION
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FN6167.2 February 20, 2008
EL5000A
COLUMN DRIVER
STV VIDEO SOURCE CPV OE EL5000A
CKV STVP
HIGH VOLTAGE REGISTER
C
CKVB
FIGURE 15. EL5000A SYSTEM BLOCK DIAGRAM
Application Information
General Description
The EL5000A is a high performance 70V TFT-LCD row driver. It level shifts TTL level timing signals from the video source into 70VP-P output voltage. Its output is capable of delivering 100mA peak current into 1nF of capacitive load. It also incorporates logic to control the output timings. The logic timing control circuit is powered from 3.3V supply. Figure 15 shows the system block diagram. CL capacitors model the capacitive loading appeared at the inputs of the TFT-LCD panel for the CKV and the CKVB signals. The CL is typically between 1nF and 5nF. In addition to switches SW1, SW2, SW3, and SW4, a fifth switch is added to reduce the power dissipation and shape the output waveform. Figure 17 shows the location of the additional SW5 switch.
Input Signals
The device performs beside of level transformation also logic operation between the input signals: * STV - Vertical Sync Timing signal, frequency range around 60Hz * CPV - Horizontal Sync Timing signal, frequency range up to 166kHz * OE - Output Enable Write Signal, frequency range up to 166kHz
r SW1 CKV SW5 Rd SW2 CKVB r CL SW3 SW4
CL
Output Signals
The output signals, CKV and CKVB are generated by EL5000A internal switches. Figure 16 depicts the simplified schematic of the output stage and interface.
FIGURE 17. BI-DIRECTIONAL SWITCHES
In reality, each switch consists of two such switches, one for the positive discharge and one for the negative discharge, see Figure 18.
CKV SW1 r SW2
SW5
D1
Rd1
CKVB
Rd2 CKV CKVB CL SW3 SW4
D2
SW5
CL
FIGURE 18. BI-DIRECTIONAL SWITCHES
FIGURE 16. SIMPLIFIED SCHEMATIC OF OUTPUT STAGE
Due to the actual solid-state construction of the switches, the capacitors CL does not get discharged entirely. The amount of left over charges depends on the value of the voltages of VON and VOFF on the capacitors.
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FN6167.2 February 20, 2008
EL5000A
Internal Logic Block Diagram
Figures 19 and 20 show the internal block diagram. In order to reduce power dissipation, most of the logic circuitry is powered from 3.3V logic supply. The output of the 3.3V logic is level-shifted to drive the output switches.
CPV OE OECON
CPVC
CPVX
ECS D STV CLK CL Q OCS Q
FIGURE 19. INTERNAL LOGIC BLOCK DIAGRAM
CPVX OCS
D1 CKV SCAN CLK ODD D2
ECS
D3
D4 STV CPVC D5 SW D6 STVP HIGH VOLTAGE STV CKVB SCAN CLK EVEN
CSS SW SW CKVBCS CKVCS
FIGURE 20. INTERNAL LOGIC BLOCK DIAGRAM AND OUTPUT SWITCHES
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FN6167.2 February 20, 2008
EL5000A
Output Waveforms
Figure 21 shows a typical CKV and CKVB output waveforms. The output droop rate depends on the external discharge resistor value and the output capacitor load. Figure 22 shows the delay time between the incoming horizontal sync timing pulse CPV and the generated output pulses. t is dependent mainly on the value of CL. Figure 23 shows the effect of STV.
CKV CKV CKVB
CKVB
STV
FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS
CPV
FIGURE 23. EFFECT OF STV
CKV
Auxiliary Functions
CKVB
DISH: It discharges VOFF when the logic power voltage level drops out, when 'DISH' is < -0.6V (VCC system power turns off), VOFF is connected to ground level by 1k. OECON: It provides continuos polarity changes to the TFT-LCD panel during the vertical blanking.
CPV
FIGURE 22. CPV TO CKV/CKVB DELAY
VCC
+18V TO +40V
C4 1F
C1 0.1F 16 1
C2 0.1F
C3 22F
15 VSYNC TIMING HSYNC TIMING WRITING TIMING
DISCH
GND
GND
VOFF
14 OECON 12 STV 10 CPV 11 OE 9
2 CKV 3 CKVCS 6 CKVB 5 CKVBCS STVP 7
VON
VDD
R2 5k R R3 5k C
R
C
EL5000 13 8
R C
R6 ca 20k*
C8 0.1F
C9 22F
TFT-LCD
C10
2nF* -9V TO -20V
FIGURE 24. TYPICAL APPLICATION CIRCUIT
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FN6167.2 February 20, 2008
EL5000A
Power Dissipation
The dissipated power in R3 and R6 could be calculated as follows: We assume that:
+17 V +40V
23V
* VON = 40V * VOFF = -20V * H sync timing frequency = 60kHz * CL = 5nF The value of VL (the left over voltage) in the capacitors in that case is 23V for the positive discharge and 3.3V for the negative discharge. The voltage change across the capacitor is therefore 23V; see Figure 25. The stored energy in the capacitor is shown in Equation 1:
1/2 x V C = 1/2 x 23 x 5 x 10 = 132J
2 2 -9
-20V 0V 23V
+3.3 V
FIGURE 25.
(EQ. 1)
The energy, which is stored in the capacitor, will be dissipated on the resistor; see Figure 26. The switch will close 2 x 60,000 in every second. The process will be repeated 2 times for the CKV and the CKVB. In 120,000 cycles per second, the power dissipation in R3 and R6 becomes Equation 2:
2 x 1.32 x 10
-6
FIGURE 26.
For different values of VON, VOFF, CL and H sync timing frequency, the worst case dissipation can be calculated in a similar matter. The value of the R3 and R6 must be selected such that the capacitor CL is discharged via R3 or R6 resistor in one half period of the H sync timing. Figures 13 and 14 show the total power dissipation over a range of possible voltages, operating frequencies and loads. Care should be taken to prevent the power from exceeding the maximum rating of the package, as shown in Figure 13.
x 60 x 10 = 160mW
3
(EQ. 2)
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FN6167.2 February 20, 2008
EL5000A Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A A1 A2 b c D E E1 e
H
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
E
E1
1 B TOP VIEW
(N/2)
0.20 C B A 2X N/2 LEAD TIPS
C SEATING PLANE
e
0.05
L L1 NOTES:
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6167.2 February 20, 2008

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