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| SL23EP09 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock skew: 45ps-typ Low output clock jitter: 25 ps-typ cycle-to-cycle jitter 15 ps-typ period jitter Low part-to-part output skew: 90 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation: 26 mA-max at 66 MHz and VDD=3.3 V 24 mA-max at 66 MHz and VDD=2.5V One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThruTM PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Description The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP09 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. Applications Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embeded Systems Benefits Up to nine (9) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Low Pow er and Low Jitter P LL C LKIN MUX CLK OU T CLK A1 CLK A2 C LKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 C LKB2 C LKB3 2 2 C LKB4 VD D GN D Rev 1.1, February 2, 2007 Page 1 of 13 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP09 Pin Configuration 16-Pin SOIC and TSSOP Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 CLKOUT Pin Type Input Output Output Power Power Output Output Input Input Output Output Power Power Output Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). 3.3V or 2.5V Power Supply. Power Ground. Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Select Input, select pin S2. Weak pull-up (250k ). Select Input, select pin S1. Weak pull-up (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Power Ground. 3.3V or 2.5V Power Supply. Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250k ). Rev 1.1, February 2, 2007 Page 2 of 13 SL23EP09 General Description The SL23EP09 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and output Frequency Range The input and output frequency range is the same. But, it depends on VDD and drive levels as given in the below Table 1. Select Input Control The SL23EP09 provides two (2) input select control pins called S1 and S2. This feature enables users to selects various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k pull-up resistors to VDD. PLL Bypass Mode If the S2 and S1 pins are logic High(1) and Low(0) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven directly from the reference input clock. In this operation mode SL23EP09 works like a non-ZDB fanout buffer. High and Low-Drive Product Options The SL23EP09 is offered with High-Drive "-1H" and Standard-Drive "-1" options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve output-tooutput skew and input-to-output specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL23EP09 is designed to operate in a wide power supply range from 2.3V (Min) to 3.6V (Max). An internal onchip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL09. weak VDD(V) 3.3 3.3 2.5 2.5 Drive HIGH STD HIGH STD Min(MHz) 10 10 10 10 Max(MHz) 220 167 200 133 Table 1. Input/Output Frequency Range If the input clock frequency is DC (GND to VDD), this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A supply current. SpreadThruTM Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP09 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Rev 1.1, February 2, 2007 Page 3 of 13 SL23EP09 S2 0 0 1 1 S1 0 1 0 1 Clock A1-A4 Tri-state Driven Driven Driven Clock B1-4 Tri-state Tri-state Driven Driven CLKOUT Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Status On On Off On Table 2. Select Input Decoding Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 1.1, February 2, 2007 Page 4 of 13 SL23EP09 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min. - 0.5 - 0.5 0 - 40 - 65 - - 2000 Max. 4.6 VDD+0.5 70 85 150 125 260 - Unit V V C C C C C V Operating Conditions: Unless Otherwise Stated VDD=2.3V to 3.6V and for Both C and I Grades Symbol VDD3.3 VDD2.5 TA Description 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature(Ambient) 3.3V+/-10% 2.5V+/-10% Commercial Industrial Condition Min. 3.0 2.3 0 -40 - - - - - - - - 175 1.2 0.8 29 41 37 41 Max. 3.6 2.7 70 85 30 30 22 22 15 15 15 5 325 Unit V V C C pF pF pF pF pF pF pF pF k MHz MHz CLOAD Load Capacitance <100 MHz, 3.3V <100 MHz, 2.5V with High drive <133.3 MHz, 3.3V <133.3 MHz, 2.5V with High drive <133.3 MHz, 2.5V with Standard drive >133.3 MHz, 3.3V >133.3 MHz, 2.5V with High drive CIN RPU/D CLBW Input Capacitance Pull-up and Pull-down Resistors Closed-loop bandwidth S1, S2 and CLKIN pins Pins-12/3/6/7/8/9/10/11/14/15/16 250k -typ 3.3V, (typical) 2.5V, (typical) ZOUT Output Impedance 3.3V, (typical), High drive 3.3V, (typical), Standard drive 2.5V, (typical), High drive 2.5V, (typical), Standard drive Rev 1.1, February 2, 2007 Page 5 of 13 SL23EP09 DC Electrical Specifications (VDD=3.3V): Unless Otherwise Stated for Both C and I Grades Symbol VDD VIL VIH IIL IIH VOL Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage Condition Min 3.0 - 2.0 Max 3.6 0.8 VDD+0.3 10 100 0.4 0.4 - - 12 25 26 42 Unit V V V A A V V V V A A mA mA 0 < VIN < 0.8V VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (high drive) - - - - 2.4 2.4 - - - - VOH Output HIGH Voltage IOH = -8 mA (standard drive) IOH = -12 mA (high drive) IDDPD IDD1 IDD2 Power Down Supply Current CLKIN<2.0MHz Power Supply Current Power Supply Current Measured at CLKIN = 0 MHz (C-Grade) Measured at CLKIN = 0 MHz (I-Grade) All Outputs CL=0, 66 MHz CLKIN All Outputs CL=0, 133 MHz CLKIN DC Electrical Specifications (VDD=2.5V): Unless Otherwise Stated for Both C and I Grades Symbol VDD VIL VIH IIL IIH VOL Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage 0 Min 2.3 - 1.7 - - - - VDD - 0.6 VDD - 0.6 - - - - Max 2.7 0.7 VDD+ 0.3 10 100 0.5 0.5 - - 12 25 24 40 Unit V V V A A V V V V A A mA mA IOL = 8 mA (standard drive) IOL = 12 mA (high drive) VOH Output HIGH Voltage IOH = -8 mA (standard drive) IOH = -12 mA (high drive) IDDPD Power Down Supply Current CLKIN<2MHz Power Supply Current Power Supply Current Measured at CLKIN = 0 MHz (C-Grade) Measured at CLKIN = 0 MHz (I-Grade) All Outputs CL=0, 66 MHz CLKIN All Outputs CL=0, 133 MHz CLKIN IDD1 IDD2 Rev 1.1, February 2, 2007 Page 6 of 13 SL23EP09 AC Electrical Specifications (VDD=3.3V and 2.5V) Symbol FMAX Description Maximum Frequency (Input=Output ) [1] Condition 3.3V High Drive 3.3V Standard Drive 2.5V High Drive 2.5V Standard Drive Min 10 10 10 10 25 40 47 45 - - - - - - - - - - - - 1.5 -100 -200 - - Typ - - - - - - - Max 220 167 200 133 75 60 53 55 Unit MHz MHz MHz MHz % % % % ns ns ns ns ns ns ns ns ns ns ps ps ns ps ps ps ps INDC Input Duty Cycle <135 MHz, VDD=3.3V <135 MHz, VDD=2.5V OUTDC Output Duty Cycle [2] <135 MHz, VDD=3.3V <135 MHz, VDD=2.5V tr/f3.3 Rise, Fall Time (3.3V) (Measured at: 0.8 to 2.0V) [2] Std drive, CL = 30 pF, <100 MHz Std drive, CL = 22 pF, <135 MHz Std drive, CL = 15 pF, <170 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <135 MHz High drive, CL = 15 pF, >135 MHz - - - - - - - - - - 45 - - - - - - 1.6 1.6 0.6 1.2 1.2 0.5 1.5 2.1 1.3 1.2 100 110 4.4 100 200 150 300 tr/f2.5 Rise, Fall Time (2.5) (Measured at: 0.6 to 1.8V) [2] Std drive, CL = 15 pF, <135 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <135 MHz High drive, CL = 15 pF, >135 MHz t1 Output-to-Output Skew [9] (Measured at VDD/2) All outputs CL=0, 3.3V supply, 2.5 power supply, standard drive All outputs CL=0, 2.5V power supply, high drive t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising [2] Edge (Measured at VDD/2) Part-to-Part Skew (Measured at VDD/2) [2] PLL Bypass mode PLL enabled @ 3.3V PLL enabled @2.5V Measured at VDD/2. Any output to any output, 3.3V supply Measured at VDD/2. Any output to any output, 2.5V supply t3 Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev 1.1, February 2, 2007 Page 7 of 13 SL23EP09 AC Electrical Specifications (VDD=3.3V and 2.5V) (cont.) Symbol tPLLOCK CCJ [2,3] Description PLL Lock Time[9] Cycle-to-cycle Jitter Condition Time from 90% of VDD to valid clocks on all the output clocks 3.3V supply, >66 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, >66 MHz, <15 pF, high drive 2.5V supply, >66 MHz, <30 pF, high drive S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive S2:S1 = 1:0 mode, 3.3V, <15pF, high drive S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive S2:S1 = 1:0 mode, 2.5V, <15pF, high drive Min - - - - - - - - - - - - - - - - - - - - - - Typ - 25 65 50 35 30 75 15 15 20 20 20 15 40 30 25 25 15 25 25 40 40 Max 1.0 50 125 100 70 60 150 40 40 50 50 50 40 80 70 60 60 45 60 60 80 80 Unit ms ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps PPJ [2,3] Peak Period Jitter 3.3V supply, 66-100 MHz, <15 pF 3.3V supply, >100 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, 66-100 MHz, <15 pF, high drive 2.5V supply, >100 MHz, <15 pF, high drive S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive S2:S1 = 1:0 mode, 3.3V, <15pF, high drive S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive S2:S1 = 1:0 mode, 2.5V, <15pF, high drive Notes: 3. Typical jitter is measured at 3.3V or 2.5V, 30 C with all outputs driven into the maximum specified load. Rev 1.1, February 2, 2007 Page 8 of 13 SL23EP09 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS pins. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 1/2 inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve "Zero Delay" between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same. Rev 1.1, February 2, 2007 Page 9 of 13 SL23EP09 Switching Waveforms Figure 2. Output to Output Skew Figure 3. Input to Output Skew Figure 4. Part-to-Part Skew Rev 1.1, February 2, 2007 Page 10 of 13 SL23EP09 Package Drawing and Dimensions 16-Lead TSSOP (4.4mm) 16 9 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID 1 8 2.900(0.114) 3.100(0.122) 1.100(0.043) MAX 0.650(0.025) BSC Gauge Plane 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 0.090(0.003) 0.200(0.008) 0.190(0.007) 0.300(0.012) 0.076(0.003) 0.650(0.025) BSC Seating Plane 0 to 8 0.500(0.020) 0.700(0.027) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Condition Still air 1m/s air flow 3m/s air flow Independent of air flow Min - Typ 80 70 68 36 Max - Unit C/W C/W C/W C/W Rev 1.1, February 2, 2007 Page 11 of 13 SL23EP09 Package Drawing and Dimensions (Cont.) 16-Lead SOIC (150 Mil) 16 9 0.150(3.810) 0.157(3.987 Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID 0.230(5.842) 0.244(6.197) 1 8 0.189(4.800) 0.196(4.978) 0.010(0.2540) X 45 0.016(0.406) 0.0075(0.190) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0.004(0.102) 0.050(1.270) BSC 0.0138(0.350) 0.0192(0.487) 0.004(0.102) 0.0098(0.249) Seating plane 0 to 8 0.016(0.406) 0.035(0.889) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Condition Still air 1m/s air flow 3m/s air flow Independent of air flow Min - Typ 120 115 105 60 Max - Unit C/W C/W C/W C/W Rev 1.1, February 2, 2007 Page 12 of 13 SL23EP09 Ordering Information [4] Ordering Number SL23EP09ZC-1 SL23EP09ZC-1T SL23EP09ZC-1H SL23EP09ZC-1HT SL23EP09ZI-1 SL23EP09ZI-1T SL23EP09ZI-1H SL23EP09ZI-1HT SL23EP09SC-1 SL23EP09SC-1T SL23EP09SC-1H SL23EP09SC-1HT SL23EP09SI-1 SL23EP09SI-1T SL23EP09SI-1H SL23EP09SI-1HT Notes: 4. The SL23EP09 products are RoHS compliant. Marking SL23EP09ZC-1 SL23EP09ZC-1 SL23EP09ZC-1H SL23EP09ZC-1H SL23EP09ZI-1 SL23EP09ZI-1 SL23EP09ZI-1H SL23EP09ZI-1H SL23EP09SC-1 SL23EP09SC-1 SL23EP09SC-1H SL23EP09SC-1H SL23EP09SI-1 SL23EP09SI-1 SL23EP09SI-1H SL23EP09SI-1H Shipping Package Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC Temperature 0 to 70C 0 to 70C 0 to 70C 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.1, February 2, 2007 Page 13 of 13 |
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