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AOZ1024D
EZBuckTM 4A Synchronous Buck Regulator
General Description
The AOZ1024D is a synchronous high efficiency, simple to use, 4A buck regulator. The AOZ1024D works from a 4.5V to 16V input voltage range, and provides up to 4A of continuous output current with an output voltage adjustable down to 0.8V. The AOZ1024D comes in a DFN 5 x 4 package and is rated over a -40C to +85C ambient temperature range.
Features

4.5V to 16V operating input voltage range Synchronous rectification: 100m internal high-side switch and 20m internal low-side switch High efficiency: up to 95% Internal soft start 1.5% initial output accuracy Output voltage adjustable to 0.8V 4A continuous output current Fixed 500kHz PWM operation Cycle-by-cycle current limit Pre-bias start-up Short-circuit protection Thermal shutdown Small size DFN 5 x 4 package
Applications

Point of load DC/DC conversion PCIe graphics cards Set top boxes DVD drives and HDD LCD panels Cable modems Telecom/networking/datacom equipment
Typical Application
VIN
C1 22F Ceramic
VIN
L1 4.7H
EN
AOZ1024D
COMP
RC CC
VOUT LX
R1 C2, C3 22F Ceramic
FB AGND PGND
R2
Figure 1. 3.3V/4A Synchronous Buck Regulator
Rev. 1.1 November 2007
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Page 1 of 16
AOZ1024D
Ordering Information
Part Number
AOZ1024DI
Ambient Temperature Range
-40C to +85C
Package
DFN-8
Environmental
RoHS
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
PGND VIN AGND FB
1 8
LX LX EN COMP
LX
2 3 7 6
GND
4 5
5 x 4 DFN
(Top Thru View)
Pin Description
Pin Number
1 2 3 4 5 6 7, 8
Pin Name
PGND VIN AGND FB COMP EN LX
Pin Function
Power ground. Electrically needs to be connected to AGND. Supply voltage input. When VIN rises above the UVLO threshold the device starts up. Reference connection for controller section. Also used as thermal connection for controller section. Electrically needs to be connected to PGND. The FB pin is used to determine the output voltage via a resistor divider between the output and GND. External loop compensation pin. The enable pin is active high. Connect in to VIN if not used and do not leave it open. PWM output connection to inductor.
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AOZ1024D
Block Diagram
VIN
EN
UVLO & POR
5V LDO Regulator
Internal +5V
OTP
+
ISen Reference & Bias
-
Softstart ILimit
Q1
+
0.8V
+
EAmp
- +
FB
-
PWM Comp
PWM Control Logic
Level Shifter + FET Driver
LX
Q2
COMP
+
Frequency Foldback Comparator
500kHz/68kHz Oscillator
0.2V
-
AGND
PGND
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum Operating Ratings.
Parameter
Supply Voltage (VIN) LX to AGND EN to AGND FB to AGND COMP to AGND PGND to AGND PGOOD to AGND Junction Temperature (TJ) Storage Temperature (TS) ESD Rating
(1)
Rating
18V -0.7V to VIN+0.3V -0.3V to VIN+0.3V -0.3V to 6V -0.3V to 6V -0.3V to +0.3V -0.3V to 6V +150C -65C to +150C 2.0kV
Parameter
Supply Voltage (VIN) Output Voltage Range Ambient Temperature (TA) Package Thermal Resistance DFN-8 (JA)(2)
Rating
4.5V to 16V 0.8V to VIN -40C to +85C 50C/W
Note: 2. The value of JA is measured with the device mounted on 1-in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25C. The value in any given application depends on the user's specific board design.
Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5k in series with 100pF.
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u
AOZ1024D
Electrical Characteristics
Symbol
VIN VUVLO IIN IOFF VFB
TA = 25C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3)
Parameter
Supply Voltage Input Under-Voltage Lockout Threshold Supply Current (Quiescent) Shutdown Supply Current Feedback Voltage Load Regulation Line Regulation
Conditions
VIN Rising VIN Falling IOUT = 0, VFB = 1.2V, VEN > 1.2V VEN = 0V
Min.
4.5
Typ.
4.1 3.7 1.6 3
Max.
16
Units
V V
2.5 20 0.812
mA uA V % %
0.788
0.8 0.5 1
IFB VEN VHYS fO DMAX DMIN
Feedback Voltage Input Current EN Input Threshold EN Input Hysteresis Frequency Maximum Duty Cycle Minimum Duty Cycle Error Amplifier Voltage Gain Error Amplifier Transconductance 500 200 5.0 TJ Rising TJ Falling 3 VIN = 12V VIN = 5V VIN = 12V VIN = 5V 150 100 5 97 166 18 30 350 100 Off Threshold On Threshold 2 100 500
200 0.6
nA V mV
MODULATOR 600 6 kHz % % V/ V A / V 6.0 A C 7 130 200 23 36 ms
PROTECTION ILIM Current Limit Over-Temperature Shutdown Limit tSS Soft Start Interval High-Side Switch On-Resistance Low-Side Switch On-Resistance
OUTPUT STAGE m m
Note: 3. Specification in BOLD indicate an ambient temperature range of -40C to +85C. These specifications are guaranteed by design.
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AOZ1024D
Typical Performance Characteristics
Circuit of Figure 1. TA = 25C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Vin ripple 0.1V/div Vo ripple 20mV/div IL 1A/div
Full Load (CCM) Operation
Vin ripple 0.1V/div Vo ripple 20mV/div IL 1A/div VLX 10V/div
VLX 10V/div
1s/div
1s/div
Startup to Full Load
VIN 10V/div
Short Circuit Protection
LX 10V/div
Vo 2V/div
Vo 2V/div
lin 1A/div
lL 5A/div
1ms/div
100s/div
50% to 100% Load Transient
Short Circuit Recovery
Vo Ripple 200mV/div
Vo 2V/div
lo 2A/div
IL 5A/div
100s/div
2ms/div
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AOZ1024D
Efficiency
AOZ1024D Efficiency
Efficiency (VIN = 12V) vs. Load Current
100 95 90
5V OUTPUT 3.3V OUTPUT 1.8V OUTPUT 1.2V OUTPUT
Efficieny (%)
85 80 75 70 65 0 0.5 1
1.5
2
2.5
3
3.5
4
Load Current (A)
Thermal Derating Curves
For DFN package part under typical line and output voltage condition. Circuit of Figure 1. 25C ambient temperature and natural convection (air speed<50LFM) unless otherwise specified.
Derating Curve at 5V/6V Input
5 4.4
Derating Curve at 12V Input
4 Output Current (IO)
1.2V OUTPUT
4.2 Output Current (IO)
1.8V
3
3.3V OUTPUT
4.0
1.2V, 1.8V OUTPUT 3.3V
2
3.8
5V OUTPUT
1
3.6
0 25 35 45 55 65 75 85 Ambient Temperature (TA)
3.4 25 35 45 55 65 75 85 Ambient Temperature (TA)
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AOZ1024D
Detailed Description
The AOZ1024D is a current-mode step down regulator with integrated high-side PMOS switch and a low-side NMOS switch. It operates from a 4.5V to 16V input voltage range and supplies up to 4A of load current. The duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. Features include enable control, Power-On Reset, input under voltage lockout, output over voltage protection, active high power good state, fixed internal soft-start, and thermal shut down. The AOZ1024D is available in a DFN 5x4 package. switch to output. The internal adaptive FET driver guarantees no turn on overlap of both high-side and low-side switch. Compared with regulators using freewheeling Schottky diodes, the AOZ1024D uses freewheeling NMOSFET to realize synchronous rectification. It greatly improves the converter efficiency and reduces power loss in the low-side switch. The AOZ1024D uses a P-Channel MOSFET as the high-side switch. It saves the bootstrap capacitor normally seen in a circuit which is using an NMOS switch. It allows 100% turn-on of the high-side switch to achieve linear regulation mode of operation. The minimum voltage drop from VIN to VO is the load current x DC resistance of MOSFET + DC resistance of buck inductor. It can be calculated by equation below:
Enable and Soft Start
The AOZ1024D has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 4.1V and voltage on the EN pin is HIGH. In the soft start process, the output voltage is typically ramped to regulation voltage in 5ms. The 4ms soft start time is set internally. The EN pin of the AOZ1024D is active HIGH. Connect the EN pin to VIN if enable function is not used. Pulling EN to ground will disable the AOZ1024D. Do not leave it open. The voltage on EN pin must be above 2V to enable the AOZ1024D. When voltage on the EN pin falls below 0.6V, the AOZ1024D is disabled. If an application circuit requires the AOZ1024D to be disabled, an open drain or open collector circuit should be used to interface to the EN pin.
V O _MAX = V IN - I O x R DSON
where; VO_MAX is the maximum output voltage, VIN is the input voltage from 4.5V to 16V, IO is the output current from 0A to 4A, and RDS(ON) is the on resistance of internal MOSFET, the value is between 97m and 200m depending on input voltage and junction temperature.
Switching Frequency
The AOZ1024D switching frequency is fixed and set by an internal oscillator. The practical switching frequency could range from 350kHz to 600kHz due to device variation.
Steady-State Operation
Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1024D integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the internal low-side N-MOSFET
Output Voltage Programming
Output voltage can be set by feeding back the output to the FB pin by using a resistor divider network (see Figure 1). The resistor divider network includes R1 and R2. Usually, a design is started by picking a fixed R2 value and calculating the required R1 with equation below:
R 1 V O = 0.8 x 1 + ------ R 2
Some standard values of R1 and R2 for the most commonly used output voltage values are listed in Table 1.
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AOZ1024D
Table 1. VO (V)
0.8 1.2 1.5 1.8 2.5 3.3 5.0
R1 (k)
1.0 4.99 10 12.7 21.5 31.6 52.3
R2 (k)
Open 10 11.5 10.2 10 10 10
Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side PMOS if the junction temperature exceeds 150C. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100C.
Application Information
The basic AOZ1024 application circuit is show in Figure 1. Component selection is explained below. Input capacitor The input capacitor must be connected to the VIN pin and PGND pin of AOZ1024D to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below:
The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper PMOS and inductor.
Protection Features
The AOZ1024D has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1024D employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. When the output is shorted to ground under fault conditions, the inductor current decays very slowly during a switching cycle because of VO = 0V. To prevent catastrophic failure, a secondary current limit is designed inside the AOZ1024D. The measured inductor current is compared against a preset voltage which represents the current limit, between 5.0A and 6.0A. When the output current is more than current limit, the high side switch will be turned off. The converter will initiate a soft start once the over-current condition is resolved. Power-On Reset (POR) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.1V, the converter starts operation. When input voltage falls below 3.7V, the converter will be shut down.
IO VO VO V IN = ------------------ x 1 - --------- x --------f x C IN V IN V IN
Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by:
VO VO I CIN _RMS = I O x --------- 1 - --------- V IN V IN
if we let m equal the conversion ratio:
VO --------- = m V IN
The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 2 on the next page. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO.
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AOZ1024D
The inductor takes the highest current in a buck circuit. The conduction loss on inductor need to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise, but they cost more than unshielded inductors. The choice depends on EMI requirement, price, and size. Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below:
0.5 0.4 ICIN_RMS(m) 0.3 IO 0.2 0.1 0
0
0.5 m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input capacitors must have current rating higher than ICIN_RMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high current rating. Depending on the application circuits, other low ESR tantalum capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures are based on certain amount of life time. Further de-rating may be necessary in practical design. Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is:
1 V O = I L x ES R CO + -------------------------- 8 x f x C O
where, CO is output capacitor value, and ESRCO is the equivalent series resistance of the output capacitor.
VO VO I L = ----------- x 1 - --------- f xL V IN
The peak inductor current is:
I L I Lpeak = I O + -------2
High inductance gives low inductor ripple current but requires a larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 20-30% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature.
When a low ESR ceramic capacitor is used as the output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to:
1 V O = I L x -------------------------8xf xC
O
If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to:
V O = I L x ES R CO
For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitors are recommended to be used as output capacitors.
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AOZ1024D
In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by:
where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and Cc is compensation capacitor in Figure 1.
I L I CO _RMS = ---------12
Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed.
The zero given by the external compensation network, capacitor Cc and resistor Rc, is located at:
1 f Z 2 = -----------------------------------2 x C C x R C
To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. The AOZ1024D operates at a frequency range from 350kHz to 600kHz. It is recommended to choose a crossover frequency equal or less than 40kHz.
Loop Compensation
The AOZ1024D employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by:
1 f P 1 = ----------------------------------2 x C O x R L
The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by:
f C = 40kHz
The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC , to calculate Rc:
1 f Z 1 = ------------------------------------------------2 x C O x ESR CO
where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor.
VO 2 x C c R C = f C x ----------- x ----------------------------G xG V
FB EA CS where; fC is the desired crossover frequency. For best performance, fC is set to be about 1/10 of the switching frequency; VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and GCS is the current sense circuit transconductance, which is 6.68 A/V.
The compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1024D. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1024D, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is:
The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. C2 can is selected by:
G EA f P 2 = ----------------------------------------2x C c x G VEA
Rev. 1.1 November 2007
1.5 C C = -----------------------------------2 x R C x f P 1
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AOZ1024D
The previous equation can also be simplified to: The maximum junction temperature of AOZ1024D is 150C, which limits the maximum load current capability. Please see the thermal de-rating curves for maximum load current of the AOZ1024D under different ambient temperature. The thermal performance of the AOZ1024D is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. The AOZ1024D is standard DFN5*4 package. Several layout tips are listed below for the best electric and thermal performance. Figure 3 on the next page illustrates a PCB layout example of AOZ1024D. 1. The LX pins are connected to internal PFET and NFET drains. They are low resistance thermal conduction path and most noisy switching node. Connected a large copper plane to LX pin to help thermal dissipation. For full load (4A) application, also connect the LX pads to the bottom layer by thermal vias to enhance the thermal dissipation. 2. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 3. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 4. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 5. Make the current trace from LX pins to L to CO to the PGND as short as possible. 6. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 7. Keep sensitive signal trace far away form the LX pins.
CO x RL C C = ---------------------RC
An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com.
Thermal Management and Layout Consideration
In the AOZ1024D buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the lowside NMOSFET. Current flows in the second loop when the lowside NMOSFET is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ1024D. In the AOZ1024D buck regulator circuit, the major power dissipating components are the AOZ1024D and the output inductor. The total power dissipation of converter circuit can be measured by input power - output power.
P total = V IN x I IN - V O x I O
The power dissipation of the inductor can be approximately calculated by output current and DCR of inductor.
P inductor = IO2 x R inductor x 1.1
The actual junction temperature can be calculated with power dissipation in the AOZ1024D and thermal impedance from junction to ambient.
T junction = ( P total - P inductor _loss ) x JA
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AOZ1024D
Thermal Vias
Bottom Layer Thermal Dissipation
Figure 3. AOZ1024D (DFN 5x4) PCB Layout
Figure 3. AOZ1024D (DFN 5x4) PCB Layout
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AOZ1024D
Package Dimensions, DFN 5x4
D D/2 A B L E/2 R aaa C E Index Area (D/2 x E/2) aaa C D2 D3 L1 E2 E3 Pin #1 IDA
1
e
ccc C
A3
Seating C Plane
A ddd C A1 b CAB
bbb
Dimensions in millimeters
Symbols A A1 A3 b D D2 D3 E E2 E3 e L L1 R aaa bbb ccc ddd Min. 0.80 0.00 0.35 1.975 1.625 2.500 2.050 0.600 0.400 - - - - Nom. 0.90 0.02 0.20 REF 0.40 5.00 BSC 2.125 1.775 4.00 BSC 2.650 2.200 0.95 BSC 0.700 0.500 0.30 REF 0.15 0.10 0.10 0.08 Max. 1.00 0.05 0.45 2.225 1.875 2.750 2.300 0.800 0.600 - - - -
Dimensions in inches
Symbols A A1 A3 b D D2 D3 E E2 E3 e L L1 R aaa bbb ccc ddd Nom. Max. 0.035 0.039 0.001 0.002 0.008 REF 0.014 0.016 0.018 0.197 BSC 0.078 0.084 0.088 0.064 0.070 0.074 0.157 BSC 0.098 0.104 0.108 0.081 0.087 0.091 0.037 BSC 0.024 0.028 0.031 0.016 0.020 0.024 0.012 REF - 0.006 - - 0.004 - - 0.004 - - 0.003 - Min. 0.031 0.000
Recommended Land Pattern
2.125 1.775 0.6 2.7
2.2
0.8
Unit: mm
0.5
0.95
Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002. 4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. Coplanarity applies to the terminals and all other bottom surface metallization. 6. Drawing shown are for illustration only.
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AOZ1024D
Tape Dimensions, DFN 5x4
Tape
T
R0
.40
20 0.
D1 E1
E2 E B0
D0 Feeding Direction
K0
Unit: mm
P0
A0
Package DFN 5x4 (12 mm)
A0 5.30 0.10
B0 4.30 0.10
K0 1.20 0.10
D0 1.50 Min. Typ.
D1 1.50
+0.10 / -0
E 12.00 0.30
E1 1.75 0.10
E2 5.50 0.10
P0 8.00 0.10
P1 4.00 0.20
P2 2.00 0.10
T 0.30 0.05
Leader/Trailer and Orientation
Trailer Tape
(300mm Min.)
Components Tape Orientation in Pocket
Leader Tape
(500mm Min.)
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AOZ1024D
Reel Dimensions, DFN 5x4
II I
R1 59
R1
M
21
6.01
R1
27
R1
I
Zoom In
R6
P
5 R5
B
W1
III
Zoom In
0.05 3-1.8
II
Zoom In
/8" 3-o1
o1
/4
3-
A
o2 . 9 0. 05
"
3-
N=o1002
6 0.2
AA
6.0
1.8 6.450.05 6.2
1.8
o9
8.00 2.20
0.00 -0.05
R1
8.90.1 14 REF
o2
1.
20
o13.0 0
o9
5.0
0.00
2.00
o17.0
R1.10 R3.10
11.90
C
1.8 12 REF
o86 .00 .1
10
41.5 REF 43.00 44.50.1
6.50
R0.5
46.00.1 44.50.1
3.3
.95
R3
4.0 6.10
38
EF
10.0
40
8R
16
A
3-
VIEW: C
3-
2.00 6.50 10.71
o3 /
o3
/1
8.00.1
6"
0.80 3.00
+0.05
2.5 1.80
R4
"
8.000.00
6
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AOZ1024D
AOZ1024D Package Marking
Z1024DI FAYWLT
Part Number Code
Fab & Assembly Location Year & Week Code
Assembly Lot Code
This data sheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Rev. 1.1 November 2007
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