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Features
* Utilizes the AVR(R) RISC Architecture * High-performance and Low-power 8-bit RISC Architecture
- 90 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz Nonvolatile Program and Data Memory - 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) - 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - Interrupt and Wake-up on Pin Change - One 8-bit Timer/Counter with Separate Prescaler - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator Special Microcontroller Features - Low-power Idle and Power-down Modes - External and Internal Interrupt Sources - In-System Programmable via SPI Port (ATtiny12) - Enhanced Power-on Reset Circuit (ATtiny12) - Internal Calibrated RC Oscillator (ATtiny12) Specification - Low-power, High-speed CMOS Process Technology - Fully Static Operation Power Consumption at 4 MHz, 3V, 25C - Active: 2.2 mA - Idle Mode: 0.5 mA - Power-down Mode: <1 A Packages - 8-pin PDIP and SOIC Operating Voltages - 1.8 - 5.5V for ATtiny12V-1 - 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4 - 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8 Speed Grades - 0 - 1.2 MHz (ATtiny12V-1) - 0 - 2 MHz (ATtiny11L-2) - 0 - 4 MHz (ATtiny12L-4) - 0 - 6 MHz (ATtiny11-6) - 0 - 8 MHz (ATtiny12-8)
*
*
8-bit Microcontroller with 1K Byte Flash ATtiny11 ATtiny12 Summary
*
* *
* *
*
Pin Configuration
ATtiny11 PDIP/SOIC
(RESET) PB5 (XTAL1) PB3 (XTAL2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (T0) PB1 (INT0/AIN1) PB0 (AIN0) (RESET) PB5 (XTAL1) PB3 (XTAL2) PB4 GND
ATtiny12 PDIP/SOIC
1 2 3 4 8 7 6 5 VCC PB2 (SCK/T0) PB1 (MISO/INT0/AIN1) PB0 (MOSI/AIN0)
Not recommended for new design
Rev. 1006FS-AVR-06/07
Note: This is a summary document. A complete document 1 is available on our Web site at www.atmel.com.
Overview
The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Table 1. Parts Description
Device ATtiny11L ATtiny11 ATtiny12V ATtiny12L ATtiny12 Flash 1K 1K 1K 1K 1K EEPROM 64 B 64 B 64 B Register 32 32 32 32 32 Voltage Range 2.7 - 5.5V 4.0 - 5.5V 1.8 - 5.5V 2.7 - 5.5V 4.0 - 5.5V Frequency 0-2 MHz 0-6 MHz 0-1.2 MHz 0-4 MHz 0-8 MHz
The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
ATtiny11 Block Diagram
See Figure 1 on page 3. The ATtiny11 provides the following features: 1K bytes of Flash, up to five general-purpose I/O lines, one input line, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny11 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel's high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. Figure 1. The ATtiny11 Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL
PROGRAM FLASH
HARDWARE STACK
MCU CONTROL REGISTER
INSTRUCTION REGISTER
GENERALPURPOSE REGISTERS
MCU STATUS REGISTER
INSTRUCTION DECODER
Z
TIMER/ COUNTER
CONTROL LINES
ALU
INTERRUPT UNIT
STATUS REGISTER
PROGRAMMING LOGIC
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
+ -
PORTB DRIVERS
PB0-PB5
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1006FS-AVR-06/07
ATtiny12 Block Diagram
Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel's high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. Figure 2. The ATtiny12 Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER INTERNAL CALIBRATED OSCILLATOR
TIMING AND CONTROL
PROGRAM FLASH
HARDWARE STACK
MCU CONTROL REGISTER
INSTRUCTION REGISTER
GENERALPURPOSE REGISTERS
MCU STATUS REGISTER
INSTRUCTION DECODER
Z
TIMER/ COUNTER
CONTROL LINES
ALU
INTERRUPT UNIT
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
+ -
PORTB DRIVERS
PB0-PB5
4
ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
Pin Descriptions
VCC GND Port B (PB5..PB0) Supply voltage pin. Ground pin. Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below. Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option External Reset Enabled External Reset Disabled External Crystal External Low-frequency Crystal External Ceramic Resonator External RC Oscillator External Clock Internal RC Oscillator Notes: 1. 2. 3. 4. 5. PB5 Used
(3) (1) (4)
PB4 (2)
PB3 Used Used Used Used Used I/O
Input /I/O -
Used Used Used I/O
(5)
I/O I/O
"Used" means the pin is used for reset or clock purposes. "-" means the pin function is unaffected by the option. Input means the pin is a port input pin. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. I/O means the pin is a port input/output pin.
XTAL1 XTAL2 RESET
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
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1006FS-AVR-06/07
Register Summary ATtiny11
Address
$3F $3E $3D $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 ... $22 $21 $20 $1F $1E $1D $1C $1B $1A $19 $18 $17 $16 $15 ... $0A $09 $08 ... $00
Name
SREG Reserved Reserved Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved Reserved Reserved WDTCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved Reserved ACSR Reserved Reserved
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 9
-
INT0 INTF0 -
PCIE PCIF -
-
-
-
TOIE0 TOV0
-
page 33 page 34 page 34 page 35
-
-
SE -
SM -
-
CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
page 32 page 28 page 41 page 41
Timer/Counter0 (8 Bit)
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 43
-
-
PINB5
PORTB4 DDB4 PINB4
PORTB3 DDB3 PINB3
PORTB2 DDB2 PINB2
PORTB1 DDB1 PINB1
PORTB0 DDB0 PINB0
page 37 page 37 page 37
ACD
-
ACO
ACI
ACIE
-
ACIS1
ACIS0
page 45
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
Register Summary ATtiny12
Address
$3F $3E $3D $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 ... $22 $21 $20 $1F $1E $1D $1C $1B $1A $19 $18 $17 $16 $15 ... $0A $09 $08 ... $00
Name
SREG Reserved Reserved Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 OSCCAL Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved Reserved ACSR Reserved Reserved
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 9
-
INT0 INTF0 -
PCIE PCIF -
-
-
-
TOIE0 TOV0
-
page 33 page 34 page 34 page 35
-
PUD -
SE -
SM -
WDRF -
BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
page 32 page 29 page 41 page 41 page 12
Timer/Counter0 (8 Bit) Oscillator Calibration Register
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 43
-
-
EEPROM Address Register EERIE EEMWE EEWE EERE
page 18 page 18 page 18
EEPROM Data Register
-
-
DDB5 PINB5
PORTB4 DDB4 PINB4
PORTB3 DDB3 PINB3
PORTB2 DDB2 PINB2
PORTB1 DDB1 PINB1
PORTB0 DDB0 PINB0
page 37 page 37 page 37
ACD
AINBG
ACO
ACI
ACIE
-
ACIS1
ACIS0
page 45
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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1006FS-AVR-06/07
Instruction Set Summary
Mnemonics
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k k
Description
Add two Registers Add with Carry two Registers Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Relative Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled
Operation
Rd Rd + Rr Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd RdRr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * (FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd RdRd Rd $FF PC PC + k + 1 PC PC + k + 1 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC + k + 1 if (SREG(s) = 0) then PCPC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
8
ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
Instruction Set Summary (Continued)
Mnemonics
LD ST MOV LDI IN OUT LPM BIT AND BIT-TEST INSTRUCTIONS SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watch Dog Reset (see specific descr. for Sleep function) (see specific descr. for WDR/timer) I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Operands
Rd,Z Z,Rr Rd, Rr Rd, K Rd, P P, Rr
Description
Load Register Indirect Store Register Indirect Move Between Registers Load Immediate In Port Out Port Load Program Memory
Operation
Rd (Z) (Z) Rr Rd Rr Rd K Rd P P Rr R0 (Z)
Flags
None None None None None None None
#Clocks
2 2 1 1 1 1 3
DATA TRANSFER INSTRUCTIONS
9
1006FS-AVR-06/07
Ordering Information
ATtiny11
Power Supply Speed (MHz) Ordering Code ATtiny11L-2PC ATtiny11L-2SC 2.7 - 5.5V 2 ATtiny11L-2PI ATtiny11L-2SI ATtiny11L-2SU(2) ATtiny11-6PC ATtiny11-6SC 4.0 - 5.5V 6 ATtiny11-6PI ATtiny11-6PU(2) ATtiny11-6SI ATtiny11-6SU(2) Package 8P3 8S2 8P3 8S2 8S2 8P3 8S2 8P3 8P3 8S2 8S2 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C)
Industrial (-40C to 85C)
Notes:
1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscillator has the same nominal clock frequency for all speed grades. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 8P3 8S2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
10
ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
ATtiny12
Power Supply Speed (MHz) Ordering Code ATtiny12V-1PC ATtiny12V-1SC 1.8 - 5.5V 1.2 ATtiny12V-1PI ATtiny12V-1PU(2) ATtiny12V-1SI ATtiny12V-1SU(2) ATtiny12L-4PC ATtiny12L-4SC 2.7 - 5.5V 4 ATtiny12L-4PI ATtiny12L-4PU(2) ATtiny12L-4SI ATtiny12L-4SU(2) ATtiny12-8PC ATtiny12-8SC 4.0 - 5.5V 8 ATtiny12-8PI ATtiny12-8PU(2) ATtiny12-8SI ATtiny12-8SU(2) Package 8P3 8S2 8P3 8P3 8S2 8S2 8P3 8S2 8P3 8P3 8S2 8S2 8P3 8S2 8P3 8P3 8S2 8S2 Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
Notes:
1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscillator has the same nominal clock frequency for all speed grades. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 8P3 8S2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
11
1006FS-AVR-06/07
Packaging Information
8P3
1
E E1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
12
ATtiny11/12
1006FS-AVR-06/07
ATtiny11/12
8S2
C
1
E
E1
L
N
TOP VIEW
END VIEW
e A
SYMBOL
b
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A1
A A1 b C
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5
D
D E1 E
SIDE VIEW
Notes: 1. 2. 3. 4. 5.
L e
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. D
R
2325 Orchard Parkway San Jose, CA 95131
13
1006FS-AVR-06/07
Datasheet Revision History
Rev. 1006F-06/07 Rev. 1006E-07/06
Please note that the page numbers listed in this section are refering to this document. The revision numbers are referring to the document revision. 1. "Not recommended for new design" 1. Updated chapter layout. 2. Updated Power-down in "Sleep Modes for the ATtiny11" on page 20. 3. Updated Power-down in "Sleep Modes for the ATtiny12" on page 20. 4. Updated Table 16 on page 36. 5. Updated "Calibration Byte in ATtiny12" on page 49. 6. Updated "Ordering Information" on page 10. 7. Updated "Packaging Information" on page 12.
Rev. 1006D-07/03 Rev. 1006C-09/01
1. Updated VBOT values in Table 9 on page 24. 1. N/A
14
ATtiny11/12
1006FS-AVR-06/07
Headquarters
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Product Contact
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1006FS-AVR-06/07

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