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| M.tec 1M x 16Bit x 4 Banks synchronous DRAM TBS6416B4E GENERAL DESCRIPTION The TBS6416B4E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with M'tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURES * JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Four-banks operation * MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation * DQM for masking * Auto & self refresh * 64ms refresh period (4K cycle) ORDERING INFORMATION Part No. TBS6416B4E-7G Max Freq. 143MHz Interface LVTTL Package 54 TSOP(II) Revision_1.1 1 TwinMOS Technologies Inc. Sep. 2000 M.tec PIN CONFIGURATION (Top View) TBS6416B4E 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) Revision_1.1 2 TwinMOS Technologies Inc. Sep. 2000 M.tec PIN FUNCTION DESCRIPTION Pin Name A0~ A11 BS0, BS1 DQ0 ~DQ15 /CS /RAS /CAS /WE UDQM/LDQM CLK CKE Vcc Vss Vcc Vss NC Address Bank Data Input / Output Chip Select Row Address Strobe Column Address Strobe Write Enable Input /output mask Clock Input Clock Enable Power (+3.3 V) Ground TBS6416B4E Function Description Multiplexed pins for row and column address Row address: A0~ A11. Column address: A0 ~ A7. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, /RAS, /CAS and /WE define the operation to be executed. Referred to /RAS Referred to /RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Q Power (+ 3.3 V) for I/O Separated power from VCC , used for output buffers to improve noise. buffer Q Ground for I/O buffer No Connection Separated ground from VSS , used for output buffers to improve noise. No connection Revision_1.1 3 TwinMOS Technologies Inc. Sep. 2000 M.tec FUNCTIONAL BLOCK DIAGRAM TBS6416B4E Bank Select Data Input Sense AMP Address ADD Buffer Row Decoder & Refresh Counter 1Mx16 1Mx16 1Mx16 1Mx16 Column Decoder Output Buffer DQ Column Buffer /CS / RAS / CAS / WE CLK CKE Commend Decoder & Clock Buffer Latency & Burst Length Programming Register Revision_1.1 4 TwinMOS Technologies Inc. Sep. 2000 M.tec ABSOLUTE MAXIMUM RATING Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage temperature Power dissipation Short circuit current TBS6416B4E Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the recommended operating conditions. Exposure to higher voltage than recommended for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Input) Input leakage current (I/O pins) Symbol VCC, VCCQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -1 -1.5 Typ 3.3 3.0 0 - Max 3.6 VCCQ+0.3 0.8 0.4 1 1.5 Unit V V V V V uA uA Note 1 2 IOH=-2mA IOL=2mA 3 3,4 Notes: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V Vout VCCQ Revision_1.1 5 TwinMOS Technologies Inc. Sep. 2000 M.tec DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70C) TBS6416B4E Parameter Operating current (One bank active) Symbol Test Condition Burst length = 1 tRCtRC(min) IOL = 0mA CKEVIL(max), tCC = 15 ns TBS6416B4E-7G Unit Note ICC1 100 mA 1 ICC2P Pre-charge standby current in power- down mode ICC2PS 2 mA CKE&CLKVIL(max), tCC = CKEVIH(min), /CSVIH(min) , tCC = 15ns Input signals are stable CKEVIH(min), CLKVIL(Max) , tCC = Input signals are stable CKEVIL(max), tCC = 15 ns 2 ICC2N Pre-charge standby current in non power-down mode ICC2NS 30 mA 10 ICC3P Active standby current in power-down mode ICC3PS 5 mA CKE&CLKVIL(max), tCC = CKEVIH(min), /CSVIH(min) , tCC = 15ns Input signals are stable CKEVIH(min), CLKVIL(Max) , tCC = Input signals are stable IOL=0 mA Page burst 2Banks activated tCCD = 2CLKS tRCtRC(min) CL = 3 CL = 2 5 Active standby current in non power-down mode (One bank active) ICC3N 40 mA 20 150 mA 140 mA 2 1 ICC3NS Operating current (Burst mode) ICC4 Refresh current ICC5 160 Self refresh current ICC6 CKE0.2V 1 mA Note: 1.Measured with outputs open. 2.Refresh period is 64 ms. Revision_1.1 6 TwinMOS Technologies Inc. Sep. 2000 M.tec AC CHARACTERISTICS AND OPERATING CONDITION FOR PC-143 (Vcc=3.3V0.3V, Ta=0 to 70C) Parameter Row active to row active delay /RAS to /RAS delay Row pre-charge time Row active time Row cycle time Col. Address to col. Address delay Write Recovery Time CLK Cycle Time CLK High Level width CLK Low Level width Access Time from CLK Output Data Hold Time Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time tRRD tRCD tRP tRAS tRC tCCD tWR tCK tCH tCL tAC tOH tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC 15 CL=2 CL=3 2.5 1.5 1 1.5 1 1.5 1 1.5 1 64 CL=2 CL=3 TBS6416B4E Symbol TBS6416B4E-7G Min 14 20 20 45 63 1 14 10 7 2.5 2.5 6 5.4 1000 100K Max ns ns ns ns ns CLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Unit Revision_1.1 7 TwinMOS Technologies Inc. Sep. 2000 M.tec 54PIN PLASTIC TSOP(II) (400mil) 54 28 TBS6416B4E detail of lead end F P E 1 2 A H G I 7 J C D NOTE N M L K B ITEM A B C D E F G H I J K L M N P MILLIMETERS 22.62 MAX. 0.91 MAX. 0.80 (T.P.) 0.32 +0.08 -0.07 0.100.05 1.20 MAX. 1.00 11.760.20 10.160.10 0.800.20 0.145 +0.025 -0.015 0.500.10 0.13 0.10 3 +7 -3 INCHES 0.891 MAX. 0.036 MAX. 0.031 (T.P.) 0.0130.003 0.0040.002 0.048 MAX. 0.039 0.4630.008 0.4000.004 0.031 +0.009 -0.008 0.0060.001 0.020 +0.004 -0.005 0.005 0.004 3 +7 -3 M Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Revision_1.1 8 TwinMOS Technologies Inc. Sep. 2000 |
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