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A New Age of Unified High-Frequency Analog and Digital Circuits Digital Satellite Broadcast Tuner IC
CXA3108Q CXA3038N
Satellite broadcasting using digital modulation first entered service in 1994 in the US, and similar service will begin this year, first in Europe and then in Japan. Thus digital satellite broadcasting is expanding rapidly on a worldwide scale. Sony has now developed a chip set for the tuners of digital satellite broadcast receivers. This chip set, which is introduced here, consists of the CXA3108Q, which takes full advantage of Sony's high-speed bipolar process technology and integrates an oscillator/mixer circuit and a PLL circuit for channel selection on a single chip, and the CXA3038N quadrature detector IC. On-Chip PLL Frequency Synthesizer Circuit The CXA3108Q integrates on a single chip two functions that were previously implemented on separate ICs: the L-band down converter functions (oscillator and mixer), and channel selection. The PLL control function supports both the I2C bus and the 3-wire bus and allows an even wider range of reference frequencies to be selected.
CXA3108Q
s s s Supports an oscillator frequency of 2.7 GHz High gain and low noise figure On-chip channel selection PLL (Supports both I 2C bus* and 3-wire bus systems)
CXA3038N
s s Adjustment-free carrier recovery provided by an on-chip PLL circuit Minimal IQ quadrature error and minimal amplitude error
* ForI2Cbus Purchase of Sony's I2C components conveys a license under Philips I2C PatentRightstousethesecomponentsinanI2Csystem,providedthatthe systemconformstotheI2CStandardSpecificationsasdefinedbyPhilips.
Support for a 2.7-GHz Oscillator Frequency The adoption of the newly-developed P42 high-frequency linear process (fT = 30 GHz), and the use of a Sony's unique differential Colpitts oscillator circuit allows this device to provide a stable oscillator signal with no parasitic oscillation over the wide band of 1.3 to 2.7 GHz. As shown in figure 3, the frequency conversion characteristics of this device are extremely flat and feature high gain and low noise figure. Adjustment-Free Carrier Recovery <CXA3038N> The CXA3038N provides adjustmentfree operation of the carrier recovery function, which is required for 480MHz band quadrature detection by including an on-chip PLL circuit. External control is not required, since the PLL circuit includes the divide data and it can replace the high-cost SAW resonator. Furthermore, to provide for cases where the carrier frequency needs to be adjusted, the device includes an A/D converter to allow the frequency to be adjusted over a range consisting of 4 50-kHz steps from the center frequency of 479.5 MHz.
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These products combine both high-frequency/low-noise analog circuits and high-speed digital circuits in a single chip, and incorporate a wide range of techniques for suppressing mutual interference between these circuits. We are convinced that these ICs will contribute to reduced costs and significant miniaturization in digital satellite broadcast tuners.
Support for a Wide Range of Applications The CXA3108Q provides two IF output circuit systems and an external input pin for the PLL circuit, and can support applications such as single unit tuners for both analog and digital satellite broadcasts and tuners for both UHF and VHF broadcasts. Since the CXA3038N also includes an on-chip 32 frequency divider circuit for the local oscillator signal, it can also support the earlier carrier recovery technique, in which a PLL circuit was included in the QPSK demodulation IC used in a later stage. The CXA3108Q and CXA3038N have power consumption levels of 350 mW and 250 mW, respectively, and achieve a significant power reduction over most previous chip sets. This makes these devices optimal for bit stream output type tuner pack products that implement, in a single unit, the whole tuner up to the QPSK demodulation and error correction circuit, which requires consideration of the heat generation problem.
Set Top Box Tuner pack BS Converter Channel Selection CXA3108Q SAW Filter Quadrature Demodulation CXA3038N
Video output Audio output
MPEG Decoder
Descrambler
QPSK Demodulation Error Correction CXD1961Q
s Figure 1
Digital Satellite Broadcast Reception Set Top Box Block Diagram
CXA3108Q
1st IF from LNB Mix. AGC amp. Output buffer SAW
Gain controller I mix. AGC amp. +90 LPF
CXA3038N
I out
480MHz
LPF Q mix. /32 PLL Ref clock PLL 1.4~2.7 GHz Osc. 30V 1T379 1T379 Loop Filter I2C bus (SDA, SCL) or 3-wire bus (DAT, CL, ENA) Loop Filter Ref osc.
Osc.
Q out
A/D
Freq. adjust
s Figure 2
CXA3108Q and CXA3038N Block Diagram
+1
(dB)
fIF=480MHz 20 CG (conversion gain)
IQ amplitude error 0
-1
(dB)
15 NF (noise figure)
(deg)
750mVp-p 1000mVp-p IQ phase error 95
90 85 -40 -30 Input Level (dBm) -20 -10
10 1.0
1.5 Reception Frequency (GHz)
2.0
s Figure 3
CXA3108Q Frequency Conversion Characteristics
s Figure 4
CXA3038N Quadrature Error

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