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| CMOS Low Power Dual 2:1 Mux/Demux USB 2.0 (480 Mbps)/USB 1.1 (12 Mbps) ADG772 FEATURES USB 2.0 (480 Mbps) and USB 1.1 (12 Mbps) signal switching compliant Tiny 10-lead 1.6 mm x 1.3 mm mini LFCSP package and 12-lead 3 mm x 3 mm LFCSP package 2.7 V to 3.6 V single-supply operation Typical power consumption: <0.1 W RoHS compliant S1A D1 S1B IN1 IN2 S2A D2 S2B 06692-001 ADG772 APPLICATIONS USB 2.0 signal switching circuits Cellular phones PDAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems SWITCHES SHOWN FOR A LOGIC 0 INPUT Figure 1. GENERAL DESCRIPTION The ADG772 is a low voltage, CMOS device that contains two independently selectable single-pole, double throw (SPDT) switches. It is designed as a general-purpose switch and can be used for routing both USB 1.1 and USB 2.0 signals. This device offers a data rate of 1260 Mbps, making the part suitable for high frequency data switching. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG772 exhibits break-before-make switching action. The ADG772 comes in a 12-lead LFCSP, and a 10-lead mini LFCSP. These packages make the ADG772 the ideal solution for space-constrained applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 1.6 mm x 1.3 mm mini LFCSP package. USB 1.1 (12 Mbps) and USB 2.0 (480 Mbps) compliant. Single 2.7 V to 3.6 V operation. RoHS compliant. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. ADG772 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions..............................5 Truth Table .....................................................................................5 Typical Performance Characteristics ..............................................6 Test Circuits........................................................................................9 Terminology .................................................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12 REVISION HISTORY 8/07--Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADG772 SPECIFICATIONS VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tON tOFF Propagation Delay Propagation Delay Skew, tSKEW Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk +25C -40C to +85C 0 V to VDD 6.7 8.8 0.04 0.2 3.3 3.6 0.2 0.2 2 0.8 0.005 0.1 2 9 12.5 6 9.5 250 20 5 3.4 0.5 73 -90 -80 -3 dB Bandwidth Data Rate CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 630 1260 2.4 6.9 0.006 1 1 Unit V typ max typ max typ max nA typ nA typ V min V max A typ A max pF typ ns typ ns max ns typ ns max ps typ ps typ ns typ ns min pC typ dB typ dB typ dB typ MHz typ Mbps typ pF typ pF typ A typ A max Test Conditions/Comments VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA; see Figure 21 VDD = 2.7 V, VS = 1.5 V, IS = 10 mA VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 22 VS = VD = 0.6 V or 3.3 V; see Figure 23 VIN = VINL or VINH VIN = VINL or VINH 13.5 10 2.9 RL = 50 , CL = 35 pF VS = 2 V; see Figure 24 RL = 50 , CL = 35 pF VS = 2 V; see Figure 24 RL = 50 , CL = 35 pF RL = 50 , CL = 35 pF RL = 50 , CL = 35 pF VS1 = VS2 = 2 V; see Figure 25 VD = 1.25 V, RS = 0 , CL = 1 nF; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 S1A to S2A/S1B to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 S1A to S1B/S2A to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 30 RL = 50 , CL = 5 pF; see Figure 30 VDD = 3.6 V Digital inputs = 0 V or 3.6 V Guaranteed by design, not subject to production test. Rev. 0 | Page 3 of 12 ADG772 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 2. Parameter VDD to GND Analog Inputs 1 , Digital Inputs Rating -0.3 V to +4.6 V -0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Peak Current, Pin S1A, Pin S2A, Pin D1, or Pin D2 Continuous Current, Pin S1A, Pin S2A, Pin D1, or Pin D2 Operating Temperature Industrial Range (B version) Storage Temperature Range Junction Temperature 10-Lead Mini LFCSP (4-Layer Board) JA Thermal Impedance 12-Lead LFCSP (4-Layer Board) JA Thermal Impedance Pb-Free Temperature, Soldering, IR Reflow Peak Temperature Time at Peak Temperature 1 -40C to +85C -65C to +150C 150C 131.6C/W 61C/W ESD CAUTION 260(+0/-5)C 10 sec to 40 sec Overvoltages at the IN1, IN2, S1A, S2A, D1, or D2 pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. 0 | Page 4 of 12 ADG772 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 S1A 11 GND 10 S2A 10 GND 9 S2A 1 S1A D1 1 S1B 2 PIN 1 INDICATOR ADG772 TOP VIEW (Not to Scale) 9 D2 8 S2B 7 NC D1 2 S1B 3 ADG772 TOP VIEW (Not to Scale) 8 D2 7 S2B 006692-002 NC 3 IN1 4 VDD 6 IN2 5 NC = NO CONNECT Figure 2. 10-Lead Mini LFCSP Pin Configuration Figure 3. 12-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions 10-Lead Mini LFCSP 1 2 3 4 5 6 7 8 9 10 N/A 12-Lead LFCSP 12 1 2 4 5 6 8 9 10 11 3, 7 Mnemonic S1A D1 S1B IN1 IN2 VDD S2B D2 S2A GND NC Description Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Logic Control Input. Controls Switch S1A/S1B--D1. Login Control Input. Controls Switch S2A/S2B--D2. Most Positive Power Supply Potential. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Ground (0 V) Reference. No Connect. TRUTH TABLE Table 4. Logic (IN1/IN2) 0 1 Switch A (S1A or S2A) Off On Switch B (S1B or S2B) On Off Rev. 0 | Page 5 of 12 VDD 6 06692-003 IN1 4 IN2 5 ADG772 TYPICAL PERFORMANCE CHARACTERISTICS 7 TA = 25C 6 5 4 3 2 1 06692-024 7 VDD = 3.0V VDD = 3.3V 6 5 4 3 2 1 06692-027 TA = +85C TA = +25C VDD = 3.3V ON RESISTANCE () ON RESISTANCE () VDD = 3.6V TA = -40C 0 0 0.5 1.0 1.5 2.0 2.5 VD, VS (V) 3.0 3.5 4.0 0 0 0.5 1.0 1.5 2.0 VD, VS (V) 2.5 3.0 3.5 Figure 4. On Resistance vs. VD (VS) VDD = 3.0 V to 3.6 V 10 9 8 ON RESISTANCE () 7 6 5 4 3 2 1 06692-023 Figure 7. On Resistance vs. VD (VS) for Different Temperature, VDD = 3.3 V 8 TA = 25C VDD = 2.3V VDD = 2.5V ON RESISTANCE () VDD = 2.7V VDD = 2.7V 7 6 5 4 3 2 1 TA = +85C TA = +25C TA = -40C 0 0.5 1.0 1.5 2.0 VD, VS (V) 2.5 3.0 3.5 0 0.5 1.0 1.5 VD, VS (V) 2.0 2.5 3.0 Figure 5. On Resistance vs. VD (VS) VDD = 2.5 V 0.2 V 30 TA = 25C 25 ON RESISTANCE () Figure 8. On Resistance vs. VD (VS) for Different Temperature, VDD = 2.7 V 25 VDD = 1.8V TA = -40C TA = +25C TA = +85C 15 VDD = 1.65V ON RESISTANCE () 20 20 VDD = 1.8V VDD = 1.95V 10 15 10 5 5 0 06692-025 06692-022 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VD, VS (V) 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 VD, VS (V) 1.4 1.6 1.8 2.0 Figure 6. On Resistance vs. VD (VS) VDD = 1.8 V 0.15 V Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 1.8 V Rev. 0 | Page 6 of 12 06692-026 0 0 ADG772 2.5 VDD = 3.3V 2.0 1.5 CURRENT (nA) 2.0 TA = 25C 1.5 VCC = 3.3V ID,S (ON)++ QINJ (pC) 1.0 VCC = 2.5V 1.0 0.5 0 -0.5 ID,S (OFF)+ 0.5 VCC = 1.8V 0 -0.5 06692-028 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 90 0 0.5 1.0 1.5 VS (V) 2.0 2.5 3.0 3.5 Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V 0.9 0.8 0.7 0.6 ID,S (ON)++ 8 TIME (ns) Figure 13. Charge Injection vs. Source Voltage 12 VDD = 2.5V 10 tON (1.8V) tOFF (1.8V) tON (3.3V) tON (2.7V) CURRENT (nA) 0.5 0.4 0.3 0.2 0.1 0 -0.1 0 10 20 ID,S (ON) 6 tOFF (2.7V) tOFF (3.3V) ID,S (OFF)+ 4 2 ID,S (OFF) + 06692-029 30 40 50 60 TEMPERATURE (C) 70 80 90 -20 0 20 40 TEMPERATURE (C) 60 80 85 Figure 11. Leakage Current vs. Temperature, VDD = 2.5 V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 ID,S (OFF)+ ID,S (OFF) + 06692-030 Figure 14. tON/tOFF Times vs. Temperature 0 -2 -4 TA = 25C VDD = 3.3V, 2.5V, 1.8V ID,S (ON)++ INSERTION LOSS (dB) -6 -8 -10 -12 -14 -16 1 10 100 FREQUENCY (MHz) 1000 06692-014 CURRENT (nA) ID,S (ON) 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 90 -18 Figure 12. Leakage Current vs. Temperature, VDD = 1.8 V Figure 15. Bandwidth Rev. 0 | Page 7 of 12 06692-019 0 -40 06692-018 -1.0 ID,S (OFF) + ID,S (ON) -1 ADG772 0 -10 -20 ATTENUATION (dB) TA = 25C VDD = 3.3V, 2.5V, 1.8V -30 -40 -50 -60 -70 -80 -90 06692-016 2 -100 Figure 16. Off Isolation vs. Frequency 0 -10 -20 -30 TA = 25C VDD = 3.3V, 2.5V, 1.8V Figure 19. USB 1.1 Eye Diagram +500mV 1 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 1 10 100 FREQUENCY (MHz) 1000 06692-015 +100mV/ DIV S1A-S1B S1A-S2A 2 06692-021 06692-020 1 10 100 FREQUENCY (MHz) 1000 C2 835mV 20.0ns/DIV 2.5GS/s ET 400ps/pt A C1 2.64V -100 -500mV 37.37ns 3 250ps/DIV 39.87ns Figure 17. Crosstalk vs. Frequency 0 -20 -40 PSRR (dB) -60 -80 -100 -120 -140 10 Figure 20. USB 2.0 Eye Diagram TA = 25C VDD = 3.3V 100 1k 10k 100k 1M FREQUENCY (MHz) 10M 100M 1G Figure 18. PSRR vs. Frequency 06692-017 Rev. 0 | Page 8 of 12 ADG772 TEST CIRCUITS IDS IS (OFF) A S D ID (OFF) A 06692-005 V1 VD VS VD S D 06692-004 VS RON = V1/IDS Figure 21. On Resistance Figure 22. Off Leakage Figure 23. On Leakage VDD 0.1F VDD VS S1B S1A D RL 50 GND VOUT CL 35pF VOUT VIN 50% 50% IN 90% 90% tON tOFF Figure 24. Switching Times, tON, tOFF 0.1F VDD VDD VS S1B S1A D RL 50 GND CL 35pF VOUT VIN VOUT 0V 50% 50% 80% 80% IN tBBM tBBM 06692-008 Figure 25. Break-Before-Make Time Delay, tBBM VDD SWITCH ON S1B S1A IN GND 1nF VOUT VOUT 06692-009 SWITCH OFF VIN NC VOUT VS D QINJ = CL x VOUT Figure 26. Charge Injection Rev. 0 | Page 9 of 12 06692-007 06692-006 NC S D ID (ON) A ADG772 VDD 0.1F NETWORK ANALYZER 50 VS VOUT 0.1F VDD VDD VDD NETWORK ANALYZER 50 VS VOUT NC S1B D S1A 50 S1B S1A D GND RL 50 GND RL 50 06692-010 OFF ISOLATION = 20 log VOUT VS INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 27. Off Isolation Figure 29. Channel-to-Channel Crosstalk (S1A-S1B) VDD NETWORK ANALYZER VOUT 50 S2A S2B S1A S1B D1 NC 50 D2 NC 0.1F NETWORK ANALYZER VOUT S1A RL 50 50 VS VOUT VS 06692-013 VDD S1B D 50 VS RL 50 GND 06692-011 CHANNEL-TO-CHANNEL CROSSTALK = 20 log CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT VS Figure 28. Channel-to-Channel Crosstalk (S1A-S2A) Figure 30. Bandwidth Rev. 0 | Page 10 of 12 06692-012 ADG772 TERMINOLOGY IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (On) The difference between the maximum and minimum values of on resistance as measured on the switch. RON On resistance match between any two channels. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. Measured with reference to ground. CD (Off) Off switch drain capacitance. Measured with reference to ground. CD, CS (On) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Off Isolation Measure of unwanted signal coupling through an off switch. Crosstalk Measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. -3 dB Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N Ratio of the harmonics amplitude plus noise of a signal to the fundamental. TSKEW The measure of the variation in propagation delay between each channel. Rev. 0 | Page 11 of 12 ADG772 OUTLINE DIMENSIONS 0.20 DIA TYP 1.30 0.55 0.40 0.30 1.60 0.40 BSC TOP VIEW 0.60 0.55 0.50 0.20 BSC 9 1 PIN 1 IDENTIFIER 6 4 0.35 0.30 0.25 BOTTOM VIEW 0.05 MAX 0.02 NOM 033007-A SEATING PLANE Figure 31. 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) 1.30 mm x 1.60 mm Body, Ultra Thin Quad (CP-10-10) Dimensions shown in millimeters 0.75 0.55 0.35 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.60 MAX PIN 1 INDICATOR *1.45 1.30 SQ 1.15 9 8 7 10 11 12 1 2 EXPOSED PAD (BOTTOM VIEW) 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 0.50 BSC 6 5 4 3 0.25 MIN COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 32. 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADG772BCPZ-1REEL1 ADG772BCPZ-REEL1 ADG772BCPZ-REEL71 EVAL-ADG772EBZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) Evaluation Board Package Option CP-12-1 CP-10-10 CP-10-10 Branding S2P B B Z = RoHS Compliant Part. (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06692-0-8/07(0) Rev. 0 | Page 12 of 12 |
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