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| FPD750 0.5W POWER PHEMT FEATURES: * * * * * 27.5 dBm Linear Output Power at 12 GHz 11.5 dB Power Gain at 12 GHz 14.5 dB Max Stable Gain at 12 GHz 38 dBm Output IP3 50% Power-Added Efficiency Datasheet v3.0 LAYOUT: GENERAL DESCRIPTION: The FPD750 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 m by 750 m Schottky barrier gate, defined by highresolution stepper-based photolithography. The double recessed gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD750 also features Si3N4 passivation and is available in the low cost plastic SOT89 SOT343 and DFN packages. TYPICAL APPLICATIONS: * * * * Narrowband and broadband highperformance amplifiers SATCOM uplink transmitters PCS/Cellular low-voltage high-efficiency output amplifiers Medium-haul digital radio transmitters ELECTRICAL SPECIFICATIONS1: PARAMETER Power at 1dB Gain Compression Maximum Stable Gain (S21/S12) Power Gain at P1dB Power-Added Efficiency Output Third-Order Intercept Point IP3 (from 15 to 5 dB below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| Matched for optimal power; Tuned for best IP3 VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.75 mA IGS = 0.75 mA IGD = 0.75 mA VDS > 6V 12.0 14.5 185 40 230 370 200 10 1.0 14.0 16.0 65 280 dBm mA mA mS A V V V C/W SYMBOL P1dB MSG G1dB PAE CONDITIONS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS; POUT = P1dB VDS = 8V; IDS = 50% IDSS MIN 26.5 13.5 10.5 TYP 27.5 14.5 11.5 45 38 MAX UNITS dBm dB dB % JC Note: 1TAmbient = 22C; RF specifications measured at f = 12 GHz using CW signal 1 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com FPD750 Datasheet v3.0 ABSOLUTE MAXIMUM RATING : PARAMETER Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power Channel Operating Temperature Storage Temperature Total Power Dissipation 4 Simultaneous Combination of Limits 2 or more Max. Limits 80% 1 SYMBOL VDS VGS IDS IG PIN TCH TSTG PTOT TEST CONDITIONS 6 -3V < VGS < -0.5V 0V < VDS < +8V For VDS < 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below ABSOLUTE MAXIMUM 10V -3V IDss 7.5mA 22dBm 175C -65C to 150C 2.3W Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power 3 Total Power Dissipation to be de-rated as follows above 22C: PTOT= 2.3 - (0.015W/C) x THS where THS= heatsink or ambient temperature above 22C Example: For a 85C carrier temperature: PTOT = 2.3 - (0.015 x (85 - 22)) = 1.4W 4 Users should avoid exceeding 80% of 2 or more Limits simultaneously 5 Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. 6 Operating at absolute maximum VD continuously is not recommended. If operation at 10V is considered then IDS must be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is restricted to < -0.5V. PAD LAYOUT: PAD DESCRIPTION Gate Pad Drain Pad Source Pad PIN COORDINATES (m) 130, 170 380, 170 A A C B B C Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening DIE SIZE (m) 470 x 340 DIE THICKNESS (m) 75 MIN. BOND PAD OPENING (m x m ) 70 x 80 2 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com FPD750 Datasheet v3.0 PREFERRED ASSEMBLY INSTRUCTIONS: GaAs devices are fragile and should be handled with great care. Specially designed collets should be used where possible. The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. PART NUMBER FPD750 DESCRIPTION Die HANDLING PRECAUTIONS: To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (0-250 V) as defined in JEDEC Standard No. 22-A114. Further information on ESD control measures can be found in MIL-STD-1686 and MILHDBK-263. APPLICATION NOTES & DESIGN DATA: Application Notes and design data including Sparameters, noise parameters and device model are available on request. DISCLAIMERS: This product is not designed for use in any space based or life sustaining/supporting equipment. ORDERING INFORMATION: 3 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com |
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