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DATASHEET
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03 Description
The MK2069-03 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation and frequency translation. It can accept an input clock over a wide range of frequencies and produces a de-jittered, low phase noise clock output. The device is optimized for user configuration by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.
Features
* Wide range VCXO PLL feedback divider allows high * * * * * * * * * *
frequency multiplication ratios and the input of very low input reference frequencies Input clock frequency of <1kHz to 13.5MHz Output clock frequency of 500kHz to 160MHz PLL lock status output VCXO-based clock generation offers very low jitter and phase noise generation, even with low frequency or jittery input clock. PLL Clear function (CLR input) allows the VCXO to free-run, offering a short term holdover function. 2nd PLL provides frequency translation of VCXO PLL to higher or alternate output frequencies. Device will free-run in the absence of an input clock (or stopped input clock) based on the VCXO frequency pulled to minimum frequency limit. Low power CMOS technology 56 pin TSSOP package Single 3.3V power supply
Block Diagram
P u lla b le x ta l S V 2 :0 IS E T LF LFR X1 X2
3
R T 1 :0
2
S T 1 :0
2
VDD
4
VCLK
P hase D etector
O EV VCXO
C harge P um p
IC L K
SV D iv id e r 1 ,2 ,4 ,6 ,8 , 1 0 ,1 2 ,1 6 F P V D iv id e r 2 to 6 5
RT D iv id e r
1 to 4
VCO
ST D iv id e r
2 ,4 ,8 ,1 6
TCLK O ET
VCXO PLL
F V D iv id e r 1 to 4 0 9 6
F T D iv id e r T ra n s la to r PLL
1 to 6 4
RCLK
L o c k D e te c to r
O ER LD
CLR O EL
12 6
LDC
LDR
6
4
F V 1 1 :0
F P V 5 :0
F T 5 :0
GND
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Pin Assignment
ST0 ST1 RT0 RT1 FT0 FT1 FT2 FT3 FT4 FT5 FPV0 VDDT GNDT X1 VDDV X2 GNDV LFR LF IS E T FV0 FV1 FV2 FV3 FV4 FV5 FV6 FV7 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 SV2 SV1 SV0 FPV5 FPV4 FPV3 OEL OET OEV OER VDD LD TCLK VDDP VCLK GNDP RCLK LDR GND LDC CLR IC L K FPV2 FPV1 FV11 FV10 FV9 FV8
VCXO PLL Feedback Divider Selection
FV11:0 FV Divider Ratio Notes 0...00 2 For FV addresses 0 to 4094, 0...01 3 FV Divide = Address + 2 : : 1...10 4096 1...11 1
VCXO PLL Scaling Divider Selection Table
SV2 SV1 SV0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SV Divider Ratio 4 6 8 10 12 2 16 1
M K 2 0 6 9 -0 3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Translator PLL Reference Divider Selection Table
RT1 RT0 0 0 0 1 1 0 1 1 RT Divider Ratio 2 3 4 1
Translator PLL Feedback Divider Selection
FT5:0 FT Divider Ratio 000000 2 000001 3 : : 111110 64 111111 1 Notes
For FT addresses 0 to 62, FT Divide = Address + 2
VCXO PLL Feedback Pre-Divider Selection
FPV5:0 FPV Divider Ratio Notes 000000 2 FPV Divide = Address + 2 000001 3 : : 111111 65
Translator PLL Scaling Divider Selection Table
ST1 ST0 0 0 0 1 1 0 1 1 ST Divider Ratio 2 4 8 16
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Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Pin Name
ST0 ST1 RT0 RT1 FT0 FT1 FT2 FT3 FT4 FT5 FPV0 VDDT GNDT X1 VDDV X2 GNDV LFR LF ISET FV0 FV1 FV2 FV3 FV4 FV5 FV6 FV7 FV8 FV9 FV10 FV11 FPV1 FPV2 ICLK CLR LDC GND LDR RCLK GNDP
Pin Type
Input Input Input Input Input Input Input Input Input Input Input Power Ground Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Ground Power Output Ground
Pin Description
Scaling Divider bit 0 input, Translator PLL (internal pull-up). Scaling Divider bit 1 input, Translator PLL (internal pull-up). Reference Divider bit 0 input, Translator PLL (internal pull-up). Reference Divider bit 1 input, Translator PLL (internal pull-up). Feedback Divider bit 0 input, Translator PLL (internal pull-up). Feedback Divider bit 1 input, Translator PLL (internal pull-up). Feedback Divider bit 2 input, Translator PLL (internal pull-up). Feedback Divider bit 3 input, Translator PLL (internal pull-up). Feedback Divider bit 4 input, Translator PLL (internal pull-up). Feedback Divider bit 5 input, Translator PLL (internal pull-up). Feedback Pre-Divider bit 0 input, VCXO PLL (internal pull-up). Power Supply connection for Translator PLL. Ground connection for Translator PLL. Crystal oscillator input. Connect this pin to the external quartz crystal. Power Supply connection for VCXO PLL. Crystal oscillator output. Connect this pin to the external quartz crystal. Ground connection for VCXO PLL. Loop filter connection, reference node. Refer to loop filter circuit on page 6. Loop filter connection, active node. Refer to loop filter circuit on page 6. Charge pump current setting pin. Refer to loop filter circuit on page 6. Feedback Divider bit 0 input, VCXO PLL (internal pull-up). Feedback Divider bit 1input, VCXO PLL (internal pull-up). Feedback Divider bit 2 input, VCXO PLL (internal pull-up). Feedback Divider bit 3 input, VCXO PLL (internal pull-up). Feedback Divider bit 4 input, VCXO PLL (internal pull-up). Feedback Divider bit 5 input, VCXO PLL (internal pull-up). Feedback Divider bit 6 input, VCXO PLL (internal pull-up). Feedback Divider bit 7 input, VCXO PLL (internal pull-up). Feedback Divider bit 8 input, VCXO PLL (internal pull-up). Feedback Divider bit 9 input, VCXO PLL (internal pull-up). Feedback Divider bit 10 input, VCXO PLL (internal pull-up). Feedback Divider bit 11 input, VCXO PLL (internal pull-up). Feedback Pre-Divider bit 1 input, VCXO PLL (internal pull-up). Feedback Pre-Divider bit 2 input, VCXO PLL (internal pull-up). Reference clock input, 5V tolerant input Clear input, allows VCXO to free-run when low (internal pull-up). Lock detector threshold setting circuit connection. Refer to circuit on page 10. Ground connection for internal digital circuitry. Lock detector threshold setting circuit connection. Refer to circuit on page 10. VCXO PLL Reference Clock output. Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
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Pin Number
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Pin Name
VCLK VDDP TCLK LD VDD OER OEV OET OEL FPV3 FPV4 FPV5 SV0 SV1 SV2
Pin Type
Output Power Output Output Power Input Input Input Input Input Input Input Input Input Input
Pin Description
Clock output from VCXO PLL Power Supply for output drivers (VCLK, TCLK, RCLK, LD, LDR). Clock output from Translator PLL Lock detector output. Power Supply connection for internal digital circuitry. Output enable for RCLK. RCLK is tri-stated when low (internal pull-up). Output enable for VCLK. VCLK is tri-stated when low (internal pull-up). Output enable for TCLK. TCLK is tri-stated when low (internal pull-up). Output enable for LD. LD is tri-stated when low (internal pull-up). Feedback Pre-Divider bit 3 input, VCXO PLL (internal pull-up). Feedback Pre-Divider bit 4 input, VCXO PLL (internal pull-up). Feedback Pre-Divider bit 5 input, VCXO PLL (internal pull-up). Scaler Divider bit 0 input, VCXO PLL (internal pull-up). Scaler Divider bit 1 input, VCXO PLL (internal pull-up). Scaler Divider bit 2 input, VCXO PLL (internal pull-up).
Functional Description
The MK2069-03 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL's with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal "VCO" (voltage controlled oscillator) function of the PLL. The use of a VCXO assures a low phase noise clock source even when a low PLL loop bandwidth is implemented. A low loop bandwidth is needed when the input reference frequency at the phase detector is low, or when jitter attenuation of the input reference is desired. The second PLL is used to translate or multiply the frequency of the VCXO PLL which has a maximum output frequency of 27 MHz. This second PLL, or Translator PLL, uses an on-chip VCO circuit that can provide an output clock up to 160 MHz. The Translator PLL uses a high loop bandwidth (typically greater than 1 MHz) to assure stability of the clock output generated by the VCO. It requires a stable, high frequency input reference which is provided by the VCXO. The divide values of the divider blocks within both PLLs are set by device pin configuration. This enables the system designer to define the following:
* * * *
Input clock frequency VCXO crystal frequency VCLK output frequency TCLK output frequency
Any unused clock or logic outputs can be tri-stated to reduce interference (jitter, phase noise) on other clock outputs. Outputs can also be tri-stated for system testing purposes. External components are used to configure the VCXO PLL loop response. This serves to maximize loop stability and to achieve the desired input clock jitter attenuation characteristics.
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Application Information
The MK2069-03 is a mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost. To help avoid unexpected problems, the guidance provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the following relationship:
f(VCLK) = FPV Divider x FV Divider x f(ICLK)
Where: FPV Divider = 2 to 65 FV Divider = 1 to 4096 VCLK output frequency range is set by the allowable frequency range of the external VCXO crystal and by the internal VCXO divider selections:
f(VCLK)
f ( VCXO ) = ---------------------SV Divider
Where: f(VCXO) = F(External Crystal) = 8 to 27 MHz SV Divider = 1,2,4,6,8,10,12 or 16 FPV Divider = 2 to 65
A higher crystal frequency will generally produce lower phase noise and therefore is preferred. A crystal frequency between 13.5 MHz and 27 MHz is recommended. Because VCLK is generated by the external crystal, the tracking range of VCLK in a given configuration is limited by the pullable range of the crystal. This is guaranteed to be +/-115 ppm minimum. This tracking range in ppm also applies to the input clock and all clock outputs if the device is to remain frequency locked to the input, which is required
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for normal operation.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed device characteristics and by variables set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO PLL loop bandwidth is approximated by:
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
f(TCLK) = FT Divider x f(VCLK) RT Divider Where: FT Divider = 1 to 64 The frequency range of TCLK is set by the operational range of the internal VCO circuit and the output divider selections: f(TCLK) f(VC0) = ---------------------ST Divider
R S x I CP x K O NBW = -----------------------------------------------------------------------------------------------------------------2 x SV Divider x FV Divider x FPV Divider
Where: f(VCO) = 40 to 320 MHz ST Divider = 2,4,8 or 16
Where: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps (see table on page 7) KO = VCXO Gain in Hz/V (see table on page 8) SV Divider = 1,2,4,6,8,10,12 or 16 FV Divider = 1 to 4096
A higher VCO frequency will generally produce lower phase noise and therefore is preferred.
MK2069-03 Loop Response and JItter Attenuation Characteristics
The MK2069-03 will reduce the transfer of phase jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The low-pass frequency response of the VCXO PLL loop is the mechanism that provides input jitter attenuation. Clock jitter, more accurately called phase jitter, is the overall instability of the clock period which can be measured in the time domain using an oscilloscope, for instance. Jitter is comprised of phase noise which can be represented in the frequency domain. The phase noise of the input reference clock is attenuated according to the VCXO PLL low-pass frequency response curve. The response curve, and thus the jitter attenuation characteristics, can be established through the selection of external MK2069-03 passive components and other device setting as explained in the following section.
The above equation calculates the "normalized" loop bandwidth (denoted as "NBW") which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on VCLK due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed:
NBW(VCXO PLL)
f(Phase Detector) -------------------------------------20
The PLL loop damping factor is determined by:
S DF = ----- x 2
R
I CP x C S x K O ----------------------------------------------------------------------------------------------------SV Divider x FV Divider x FPV Divider
Where: CS = Value of capacitor CS in loop filter in Farads
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CP
S = -----
C
20
External VCXO PLL Components
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also dampens VCXO input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO input voltage can hit the supply or ground rail resulting in non-linear loop response. The best way to set the value of CP is to use the filter response software available from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak.
DON'T STUFF Refer to "Crystal Tuning Load Capacitors" Section
Optional Crystal Tuning Capacitors
MK2069
CL
XTAL
X1 X2
CL CP CS RS RSET
LFR LF ISET
Loop Filter Response Software
Online tools to calculate loop filter response can be found at www.idt.com.
In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband and will further assure output stability with the presence of system and power supply noise. A damping factor of 4 will ensure a passband peak less then 0.2dB which may be required for network clock wander transfer compliance. A higher damping factor may also increase output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress.
Notes on setting the value of CP
As another general rule, the following relationship should be maintained between components CS and CP in the loop filter:
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Graph of Charge Pump Current vs. Value of RSET (external resistor)
1E-3
ICP, Amps
100E-6
10E-6 100E+3
1E+6
RSET, ohms
Recommended Range of Operation
10E+6
Charge Pump Current, Example Settings from Above Graph
RSET 5 M 3 M 2 M 1 M 480 k 400 k Charge Pump Current (ICP) 25 A 42 A 65 A 125 A 255 A 300 A
VCXO Gain (KO) vs. XTAL Frequency
6000 V C X O G a in (K O ), H z p e r V o lt
5000
4000
3000
Notes on Setting Charge Pump Current
The recommended range for the charge pump current is 25 A to 300 A. Below 25 A, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor.
2000
1000 10 15 20 25 30
C ry s ta l F re q u e n c y , M H z
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Example Loop Filter Component Value
Phase Detector Frequency 8 kHz 8 kHz 8 kHz Xtal Freq (MHz) 19.44 19.44 22.368 SV Div 1 1 1 VCLK (MHz) 19.44 19.44 22.368 FV Div x FPV Div 2430 2430 2796 RSET
RS
CS
CP
Loop Loop BW Damp. (-3dB) 4.0 1.4 4.5
Passband Peaking 0.15dB at 1Hz 1.2dB at 6Hz 0.12dB at 1Hz
Note
1 M 560 k 1 F 1 M 680 k 1 F
4.7 nF 22 Hz
1 2 3
1 M 560 k 0.1 F 4.7 nF 27 Hz 4.7 nF 20 Hz
Notes: 1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant. 2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when GR-1244-CORE compliance is not needed. 3) This configuration is used to generate a DS3 clock of 44.736 MHz at the TCLK output. This configuration is GR-1244-CORE compliant when used following a system synchronizer.
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors. Recommendations for these capacitors can be found at www.idt.com.
When CLR is high, the VCXO PLL operates normally. When CLR is low, the VCXO PLL charge pump output is inactivated which means that no charge pump correction pulses are provided to the loop filter. During this time, the VCXO frequency is held constant by the residual charge or voltage on the PLL loop filter, regardless of the input clock condition. However, the VCXO frequency will drift over time, eventually to the minimum pull range of the crystal, due to leak-off of the loop filter charge. This means that CLR can provide a holdover function, but only for a very short duration, typically in milliseconds. Upon bringing CLR high, the FV divider is reset and begins counting with the first positive edge of the new input clock, and the charge pump is re-activated (FPV is not reset). By resetting the FV Divider, the memory of the previous input clock phase is removed from this feedback divider, eliminating the generation of extra VCLK clock cycles that would occur if the loop was to re-lock under normal means. Lock time is also reduced, as is the generation of clock wander. By using CLR in this fashion VCLK will align to the input clock phase with only one or two VCLK cycle slips resulting.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase compensation circuit. It is used when changing the phase of the input clock, which might occur when selecting a new reference input through the use of an external clock multiplexer. The phase compensation circuit allows the VCXO PLL to quickly lock to the new input clock phase without producing extra clock cycles or clock wander, assuming the new clock is at the same frequency. Input pin CLR controls the phase compensation circuit. CLR must remain high for normal operation. When used in conjunction with an external multiplexer (MUX), CLR should be brought low prior to MUX reselection, then returned high after MUX reselection. This prevents the VCXO PLL from attempting to lock to the new input clock phase associated with the input clock.
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When CLR is not used, the number of VCLK cycle slips can be as high the FV Divider value. TCLK is always locked to VCLK regardless of the state of the CLR input. Under ideal conditions, where the VCXO is phase- locked to a low-jitter reference input, loop phase error is typically maintained to within a few nanoseconds.
Lock Detection
The MK2069-03 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase lock is lost (such as when the input clock stops, drifts beyond the pullable range of the crystal, or suddenly shifts in phase), the LD output goes low. The definition of a "locked" condition is determined by the user. LD is high when the VCXO PLL phase detector error is below the user-defined threshold. This threshold is set by external components RLD and CLD shown in the Lock Detection Circuit Diagram, below. To help guard against false lock indications, the LD pin will go high only when the phase error is below the set threshold for 8 consecutive phase detector cycles. The LD pin will go low when the phase error is above the set threshold for only 1 phase detector cycle.
Lock Detection Circuit Diagram
L o c k D e te ctio n C irc u it
FV D iv id e r O u tp u t Lock Q u a lific a tio n C o u n te r (8 u p , 1 d o w n )
RESET
LD
VCXO Phase D e te c to r E rro r O u tp u t LDR RLD LDC
OEL
In p u t T h res h o ld se t to V D D /2
CLD
The lock detector threshold (phase error) is determined by the following relationship: (LD Threshold) = 0.6 x R x C
Where:
If the lock detection circuit is not used, the LDR output may remain unconnected, however the LDC input should be tied high or low. If the PCB was designed to accommodate the RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm).
1 k < R < 1 M (to avoid excessive noise or leakage) C > 50 pF (to avoid excessive error due to stray capacitance, which can be as much as 10 pF including Cin of LDC) Lock Detector Application example: The desired maximum allowable loop phase error for a generated 19.44MHz clock is 100UI which is 5.1 s. Solution: 5.1 s = (0.001 f) x (8.5 k)
Power Supply Considerations
As with any integrated clock device, the MK2069-03 has a special set of power supply requirements:
* The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply noise sources include the system switching power supply or other system components. The noise can interfere with device PLL components such as the VCO or phase detector.
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* Each VDD pin must be decoupled individually to prevent
power supply noise generated by one device circuit block from interfering with another circuit block. PCB power plane or system EMI problems may result. This above set of requirements is served by the circuit illustrated in the Recommended Power Supply Connection (next page). The main features of this circuit are as follows:
Recommended Power Supply Connection
VDD Pin
Connection Via to 3.3V Power Plane Ferrite Chip 0.1 F BULK 1 nF
0.01 F
* Clock noise from device VDD pins must not get onto the
* Only one connection is made to the PCB power plane. * The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass `pi' filter that remove noise from the power supply as well as clock noise back toward the supply. The bulk capacitor should be a tantalum type, 1 F minimum. The other capacitors should be ceramic type.
0.01 F
VDD Pin
0.01 F
VDD Pin
should fan out at the common supply filter to reduce interaction between the device circuit blocks.
* The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as possible. There should be no via's between the decoupling capacitor and the supply pin.
Series Termination Resistor
Output clock PCB traces over 1 inch should use series termination to maintain clock signal integrity and to reduce EMI. To series terminate a 50 trace, which is a commonly used PCB trace impedance, place a 33 resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20 .
Quartz Crystal
The MK2069-03 operates by phase-locking the VCXO circuit to the input signal at the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2069-03 incorporates variable load capacitors on-chip which "pull" or change the frequency of the crystal. The crystals specified for use with the MK2069-03 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2069-03 and the crystal.
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0.01 F
* The power supply traces to the individual VDD pins
VDD Pin
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Recommended Crystal Parameters:
Crystal parameters can be found in application note MAN05 on www.icst.com. Approved crystals can be found at www.icst.com (search "crystal").
should be no signal traces near the crystal or the traces. Also refer to the Optional Crystal Shielding section that follows. 4) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 5) All components should be on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor may be mounted on the back). Other signal traces should be routed away from the MK2069-03. This includes signal traces on PCB traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 6) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state ("1") can be left unconnected. The pins requiring a logic low state ("0") can be grounded.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small capacitors from X1 and X2 to ground, shown as CL in the External VCXO PLL Components diagram on page 6. These capacitors are used to center the total load capacitor adjustment range imposed on the crystal. The load adjustment range includes stray PCB capacitance that varies with board layout. Because the typical telecom reference frequency is accurate to less than 32 ppm, the MK2069-03 may operate properly without these adjustment capacitors. However, ICS recommends that these capacitors be included to minimize the effects of variation in individual crystals, including those induced by temperature and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout, using the procedure described in the `MAN05' application note.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2 are sensitive to noise pickup. In applications that are especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-03 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. 1) The metal layer underneath the crystal section should be the ground layer. Remove all other layers that are above. This ground layer will help shield the crystal circuit from other system noise sources. As an alternative, all layers underneath the crystal can be removed, however this is not recommended if there are adjacent PCBs that can induce noise into the unshielded crystal circuit. 2) Cut a channel in the PCB ground plane around the crystal area as shown. This will eliminate high frequency ground currents that can couple into the crystal circuit. 3) Add a through-hole for the optional third lead offered by the crystal manufacturer (case ground). The requirement for this third lead can be made at prototype evaluation. The crystal is less sensitive to system noise interference when the case is grounded.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please refer to the Recommended PCB Layout drawing on the following page. 1) Each 0.01F decoupling capacitor (CD) should be mounted on the component side of the board as close to the VDD pin as possible. No via's should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite chip and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the LF and LFR pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted as close to the device as possible, on the component side of the board. This will help keep the crystal PCB traces short to minimize parasitic load capacitance on the crystal leads as well as noise pickup. The crystal traces should be spaced away from each other and should use minimum trace width. There
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4) Add a ground trace around the crystal circuit to shield from other active traces on the component layer.
The external crystal is particularly sensitive to other system clock sources that are at or near the crystal frequency since it will try to lock to the interfering clock source. The crystal should be keep away from these clock sources. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section.
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Recommended PCB Layout Diagram
SUPPLY SOURCE TO DEVICE (SUCH AS VIA TO SUPPLY PLANE) OPTIONAL CRYSTAL SHIELDING THRU HOLE FOR 3RD LEAD (XTAL CASE GROUND) SHIELD TRACE (TOP LAYER) CUT CHANNEL IN GROUND PLANE
V
CE 603 FC A
G
CBD A CBB 603 G
56
G G
G G
1 2 3 4 5 6
G
G
55 54 53 52 51 50 49 48 47 46 45
CL 603
7
G
CD 603
8 9 10 11 12 13 14 15
G CD 603 G RT 603
CD 603
G
CL 603
XTAL
G MK2069 G G G
44 43 42 41 40 39 38 37 36 35 34 33 32 31
CD 603
G
16 17 18 19 20
RT 603 RLD 603 CLD 603 G
G
G
CP 805
21 22 23 24
CS 1206
RS 603 G RSET 603
25 26 27 28
G
G
30 29
Components are identified by function (top line) and by typical package type (bottom line) which may vary. Legend: G = Via to PCB Ground plane V = Via to PCB Power Plane CE = EMI suppression cap, typical value 0.1 F (ceramic) FC = Ferrite chip CBD = Bulk decoupling capacitor for chip power supply, 1 F minimum (tantalum) CBB = Bulk bypass cap for chip power supply, typical value 1000 pF (ceramic) CD = Decoupling capacitor for VDD pin (ceramic) CL = Optional load capacitor for crystal tuning (do not stuff) CS = External loop capacitor CS (film type) CP = External loop capacitor CP (film type) RS = External loop resistor RS RSET = Resistor RSET used to determine charge pump current RT = Series termination resistor for clock output, typical value 33 RLD* = External resistor for lock detector circuit CLD* = External capacitor for lock detector circuit *Note: If output LD is not used, RLD and CLD may be omitted. See text on page 10.
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Circuit Troubleshooting
1) IF TCLK or VCLK does not lock to ICLK
First check VCLK to ICLK. It is best to display and trigger the scope with RCLK, especially if a non-integer VCXO PLL multiplication ratio is used. If VCLK is not locked to ICLK: 1.1) Ensure the proper ICLK input is selected. 1.2) Check Divider settings. 1.3) Ensure ICLK is within lock range (within about 100 ppm of the nominal input frequency, limited by pull range of the external crystal). If in doubt, tweak the ICLK frequency up and down to see if VCLK locks. 1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is excessive device may not lock. Also see item 2.1 below. 1.5) Clean the PCB. The VCXO PLL loop filter is very sensitive to board leakage, especially when the VCXO PLL phase detector frequency is in the low kHz. If organic solder flux is used (most common today) scrub the PCB board with detergent and water and then blow and bake dry. Inorganic solder flux (Rosen core) requires solvent. See also section 3 below.
leakage. Refer to item 1.5 above. 2.3) VCLK and TCLK jitter can also be caused by poor power supply decoupling. Ensure a bulk decoupling capacitor is in place. 2.4) Ensure that the VCXO PLL loop bandwidth is sufficiently low. It should be at least 1/20th of the phase detector frequency. 2.5) Ensure that the VCXO PLL loop damping is sufficient. If should be at least 0.7, preferably 1.0 or higher. 2.6) Ensure that the 2nd pole in the VCXO PLL loop filter is set sufficiently. In general, CP should be equal to CS/20. If CP is too high, passband peaking will occur and loop instability may occur. If CP is set too low, excessive VCXO modulation by the charge correction pulses may occur.
3) If There is Excessive Input to Output Skew
3.1) TCLK should track VCLK. The rising edge of TCLK should be within a few nanoseconds of VCLK. 3.2) VCLK should track RCLK. The rising edge of VCLK should be within 5-10 nsec of RCLK (VCLK leads). 3.3) The biggest cause of input to output skew is VCXO PLL loop filter leakage. Skew is best observed by comparing ICLK to RCLK. When no leakage is present the rising edge of RCLK should lag the rising edge of ICLK by about 10 sec. Loop filter leakage can greatly increase this lag time or cause the loop to not lock. Refer to item 1.5, above. 3.4) Another way to view the loop filter leakage is to observe LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled `Loop Filter Capacitor Type' on page 9.
2) If There is Excessive Jitter on VCLK or TCLK
2.1) The problem may be an unstable input reference clock. An unstable ICLK will not appear to jitter when ICLK is used as the oscilloscope trigger source. In this condition, VCLK and TCLK may appear to be unstable since the jitter from ICLK (the trigger source) has been removed by the trigger circuit of the scope. 2.2) The instability may be caused by VCXO PLL loop filter
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2069-03. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V -40 to +85 C -65 to +150 C 175 C 260 C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-40 +3.15
Typ.
+3.3
Max.
+85 +3.45
Units
C V
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C
Parameter
Operating Voltage Supply Current
Symbol
VDD IDD
Conditions
All clock outputs loaded with 15 pF, VCLK = 19.44 MHz, TCLK = 155.52 MHz
Min.
3.15
Typ.
3.3 20
Max.
3.45 30
Units
V mA
Input High Voltage, FV11:0, FPV5:0, SV2:0, FT5:0, RT1:0, ST1:0, CLR Input Low Voltage, FV11:0, FPV5:0, SV2:0, FT5:0, RT1:0, ST1:0, CLR Input Pull-Up Resistor (Note 1) Input High Voltage, CLR Input High Voltage, ICLK (Note 2) Input Low Voltage, ICLK, CLR Input High Current (Note 1) Input Low Current (Note 1) Input Capacitance, except X1 Output High Voltage (CMOS Level) Output High Voltage Output Low Voltage Output Short Circuit Current, TCLK Output Short Circuit Current, VCLK, RCLK and LD VIN, VCXO Control Voltage
VIH
2
VDD + 0.4 0.8
V
VIL
-0.4
V
RPU VIH VIH VIL IIH IIL CIN VOH VOH VOL IOS IOS VXC 0 IOH = -4 mA IOH = -8 mA IOL = 4 mA VDD-0.4 2.4 VIH = VDD VIL = 0
VDD/2+1 VDD/2+1
200 VDD + 0.4 5.5
VDD/2-1
k V V V A A pF V V 0.4 V mA mA VDD V
-0.4 -10 -10 7
+10 +10
50 20
Note 1: All logic select inputs (FV11:0, FPV5:0, SV2:0, FT5:0, RT1:0, ST1:0, CLR) have an internal pull-up resistor. Note 2: ICLK can safely be brought to VIH max prior to the application of VDD, providing utility in hot-plug line card applications.
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C
Parameter
Crystal Frequency Range (Note 1) VCXO Crystal Pull Range VCXO Crystal Free-Run Frequency (Note 2) Input Clock Frequency (Note 3) Input Clock Pulse Width VCXO PLL Phase Detector Jitter Tolerance Translator PLL VCO Frequency Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) Timing Jitter, Filtered 65kHz-5MHz (OC-3) Timing Jitter, Filtered 1kHz-5MHz (OC-12) Timing Jitter, Filtered 250kHz-5MHz (OC-12) Output Frequency Output Duty Cycle (% high time), VCLK when SV Divider = 1 Output Duty Cycle (% high time), VCLK when SV Divider > 1, TCLK Output High Time, RCLK (Note 4) Output Rise Time, VCLK and RCLK Output Fall Time, VCLK and RCLK
Symbol
fXTAL fXP fXF fI tID tJT fV tOJf
Conditions
Using recommended crystal Using recommended crystal Input reference = 0 Hz
Min.
13.5 115 -300 0.001
Typ.
Max. Units
27 MHz ppm ppm 27 MHz nsec
150 -150
Positive or Negative Pulse 1 UI = phase detector period
10 0.4 40 320 95
UI MHz ps
Derived from phase noise characteristics, peak-to-peak 6 sigma Derived from phase noise characteristics, peak-to-peak 6 sigma Derived from phase noise characteristics, peak-to-peak 6 sigma Derived from phase noise characteristics, peak-to-peak 6 sigma VCO frequency = 40 to 320 MHz 2.5 40 44
tOJf
85
ps
tOJf
105
ps
tOJf
80
ps
160 50 50 60 65
MHz % %
tOD tOD
Measured at VDD/2, CL=15pF Measured at VDD/2, CL=15pF Measured at VDD/2, CL=15pF 0.8 to 2.0V, CL=15pF 2.0 to 0.8V, CL=15pF
tOH
0.5 VCLK Period 1.5 1.5 2 2 ns ns
tOR tOF
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Parameter
Output Rise Time, TCLK Output Fall Time, TCLK Skew, ICLK to VCLK (Note 5) Skew, ICLK to RCLK (Note 5) Skew, ICLK to TCLK (Note 5) Nominal Output Impedance
Symbol
tOR tOF tIV tIV tVT ZOUT
Conditions
0.8 to 2.0V, CL=15pF 2.0 to 0.8V, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF
Min.
Typ.
0.75 0.75
Max. Units
1 1 +10 +20 +10 ns ns ns ns ns
-5 +5 -5
2.5 10 1.5 20
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may result in increased output phase noise. Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the attempt of the PLL to lock to 0 Hz. Note 3: The minimum practical phase detector frequency is is assumed to be 1 kHz. Through proper loop filter design lower input frequencies may be possible. Input frequencies as low as 400Hz have been implemented. Note 4: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period. Note 5: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the external VCXO PLL loop filter.
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Package Outline and Package Dimensions
56 pin TSSOP 6.10 mm (240 mil) body, 0.50 mm. (20 mil) pitch Package dimensions are kept current with JEDEC Publication No. 95
56
Millimeters Symbol Min Max
Inches Min Max
E1 IN D EX AR EA
E
1
2
D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 Basic 0.018 0.030 0 8 -0.004
A 2 A 1
A
c
-Ce
b S E A T IN G P LA N E L
aaa C
Ordering Information
Part / Order Number
MK2069-03GI MK2069-03GITR
Marking
MK2069-03GI MK2069-03GI
Shipping packaging
Tubes Tape and Reel
Package
56 pin TSSOP 56 pin TSSOP
Temperature
-40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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