 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CP27 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts stats. However, the interrupts = ( NMI , INT0, INTRTC), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interupt request is kept on hold internally.) If another interupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CP27 CMOS 16-Bit Microcontrollers TMP91CP27U 1. Outline and Features TMP91CP27 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91CP27U comes in a 64-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (1.0 s/2 bytes at 16 MHz) (2) Minimum instruction execution time: 148 ns (at 27 MHz) (3) Built-in RAM: 4 Kbytes Built-in ROM: 48 Kbytes (4) External memory expansion * * Expandable up to 16 Mbytes (Shared program/data area) Can simultaneously support 8-/16-bit width external data bus (Dynamic data bus sizing) (5) 8-bit timers: 6 channels (6) 16-bit timers: 1 channel (7) General-purpose serial interface: 2 channels * * * UART/Synchronous mode: 2 channels IrDA Ver.1.0 (115.2 Kbps) mode selectable: 1 channel I2C bus mode/clock synchronous mode selectable 030619EBP1 (8) Serial bus interface: 1 channel * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 91CP27-1 2003-11-05 TMP91CP27 (9) 10-bit AD converter (Sample hold circuit is inside): 4 channels (10) Watchdog timer (11) Timer for real time clock (RTC) (12) Chip select/wait controller: 4 blocks (13) Interrupts: 34 interrupts * * * 9 CPU interrupts: Software interrupt instruction and illegal instruction 21 internal interrupts: 7 priority levels are selectable 4 external interrupts: 7 priority levels are selectable (among 3 interrupts are selectable edge mode) (14) Input/output ports: 53 pins (15) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP (16) Clock controller * * * * * Clock gear function: Select a high-frequency clock fc to fc/16 RTC (fs = 32.768 KHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz) VCC = 1.8 V to 3.6 V (fc max = 10 MHz) P-LQFP64-1010-0.50D (17) Operating voltage (18) Package 91CP27-2 2003-11-05 TMP91CP27 ADTRG (P53) CPU (TLCS-900/L1) AN0 to AN3 (P50 to P53) AVCC, AVSS 10-bit 4-ch AD converter TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1/ CTS1 (P95) SCK (P60) SO/SDA (P61) SI/SCL (P62) SIO/UART/IrDA XWA XBC XDE XHL XIX XIY XIZ XSP (Channel 0) SIO/UART (Channel 1) Serial bus interface (SBI) 8-bit timer (TMRA 0) 8-bit timer (TMRA 1) 8-bit timer (TMRA 2) WA BC DE HL IX IY IZ SP 32 bits SR F PC High-speed oscillator Clock gear Low speed oscillator DVCC DVSS X1 X2 XT1 (P96) XT2 (P97) RESET AM0 AM1 ALE Port 0 Port 1 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P25) A0/A16 to A5/A21 RD (P30) Watchdog timer (WDT) Port 2 TA0IN (P70) TA1OUT (P71) RTC WR (P31) Port 3 HWR (P32) Port 6 TA3OUT (P72) 8-bit timer (TMRA 3) 4-Kbyte RAM 8-bit timer (TMRA 4) 8-bit timer (TMRA 5) 48-Kbyte ROM CS/WAIT controller (4 blocks) Interrupt controller (P40 to P42) CS0 to CS2 NMI TA4IN (P73) TA5OUT (P74) INT0 (P63) TB0IN0/INT5 (P80) TB0IN1/INT6 (P81) TB0OUT0 (P82) TB0OUT1 (P83) 16-bit timer (TMRB0) ( ): Initial function after resert Figure 1.1 TMP91CP27 Block Diagram 91CP27-3 2003-11-05 TMP91CP27 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91CP27U, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1 shows the pin assignment of the TMP91CP27U. P61/SO/SDA P62/SI/SCL P63/INT0 P50/AN0 P51/AN1 P52/AN2 AVCC AVSS P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT 57 58 59 60 61 62 64 1 2 3 4 5 6 56 P60/SCK 55 P42/ CS2 54 P41/ CS1 53 P40/ CS0 52 P32/ HWR 51 P31/ WR 50 P30/ RD 49 P25/A5/A21 48 P24/A4/A20 47 P23/A3/A19 46 P22/A2/A18 45 P21/A1/A17 44 P20/A0/A16 43 P17/AD15/A15 42 P16/AD14/A14 P53/AN3/ ADTRG 63 P80/TB0IN0/INT5 7 P81/TB0IN1/INT6 8 P82/TB0OUT0 P83/TB0OUT1 P90/TXD0 P91/RXD0 9 10 11 12 Top view LQFP64 41 P15/AD13/A13 40 P14/AD12/A12 39 P13/AD11/A11 38 P12/AD10/A10 37 P11/AD9/A9 36 P10/AD8/A8 35 P07/AD7 34 P06/AD6 33 P05/AD5 32 P04/AD4 31 P03/AD3 30 P02/AD2 29 P01/AD1 28 P00/AD0 27 ALE 26 NMI P92/SCLK0/ CTS0 13 P93/TXD1 14 P94/RXD1 15 P95/SCLK1/ CTS1 16 AM0 DVCC X2 DVSS X1 AM1 RESET 17 18 19 20 21 22 23 24 P96/XT1 25 P97/XT2 Figure 2.1 Pin Assignment Diagram (64-pin LQFP) 91CP27-4 2003-11-05 TMP91CP27 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.3 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/3) Pin Names P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P25 A0 to A5 A16 to A21 P30 RD Number of Pins 8 8 I/O I/O I/O I/O I/O Output I/O Output Output Output Output Output Output I/O Output I/O Output I/O Output I/O Output Input Input Input I/O I/O I/O Output I/O I/O Input I/O I/O Input Functions Port 0: I/O port that allows I/O to be selected at the bit level Address data (Lower): 0 to 7 of address/data bus Port1: I/O port that allows I/O to be selected at the bit level Address data (Upper): 8 to 15 of address/data bus Address: 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: 0 to 5 of address bus Address: 16 to 21 of address bus Port 30: Output port Read: Strobe signal for reading external memory when read internal area also, output RD by setting to P3 6 1 P31 WR 1 1 1 1 1 4 P32 HWR P40 CS0 P41 CS1 P42 CS2 P50 to P53 AN0 to AN3 ADTRG P60 SCK P61 SO SDA P62 SI SCL P63 INT0 1 1 1 1 91CP27-5 2003-11-05 TMP91CP27 Table 2.2.2 Pin Names and Functions (2/3) Pin Names P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 Number of Pins 1 1 1 1 1 1 I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input I/O Output Functions Port 70: I/O port 8-bit timer 0 input: Input pin of 8-bit timer TMRA0 Port 71: I/O port 8-bit timer 1 output: Output pin of 8-bit timer TMRA0 or TMRA1 Port 72: I/O port 8-bit timer 3 output: Output pin of 8-bit timer TMRA2 or TMRA3 Port 73: I/O port 8-bit timer 4 input: Input pin of 8-bit timer TMRA4 Port 74: I/O port 8-bit timer 5 output: Output pin of 8-bit timer TMRA4 or TMRA5 Port 80: I/O port 16-bit timer 0 Input 0: Input of count/capture trigger in 16-bit timer TMRB0 Interrupt request pin 5: Interrupt request pin with selectable rising/falling edge Port 81: I/O port 16-bit timer 0 input 1: Input of count/capture trigger in 16-bit timer TMRB0 Interrupt request pin 6: Interrupt request pin of rising edge Port 82: I/O port 16-bit timer 0 output 0: Outpit pin of 16-bit timer TMRB0 Port 83: I/O port 16-bit timer 0 output 1: Output pin of 16-bit timer TMRB0 Port 90: I/O port Serial 0 send data: Open-drain output pin by programmable Port 91: I/O port Serial 0 receive data Port 92: I/O port Serial 0 clock I/O Serial 0 data send enable (Clear to send) Port 93: I/O port Serial 1 send data: Open-drain output pin by programmable Port 94: I/O port Serial 1 receive data Port 95: I/O port Serial 1 clock I/O Serial 1 data send enable (Clear to send) Port 96: I/O port. Open-drain output pin Low-frequency oscillator connection pin Port 97: I/O port. Open-drain output pin Low-frequency oscillator connection pin 1 1 1 1 1 1 P93 TXD1 P94 RXD1 P95 SCLK1 CTS1 1 1 1 P96 XT1 P97 XT2 1 1 91CP27-6 2003-11-05 TMP91CP27 Table 2.2.3 Pin Names and Functions (3/3) Pin Names ALE NMI Number of Pins 1 1 I/O Output Input Functions Address latch enable (It can be set as prohibition of an output for noise reduction.) Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable (Schmitt input). Operation mode: Fixed to AM1 = "1" and AM0 = "1". Reset: Initialize LSI. (Schmitt input, with pull-up resistor) Pin used to both power supply pin for AD converter and standard power supply for AD converter (H). Pin used to both GND pin for AD converter (0 V) and standard power supply pin for AD converter (L). AM0, AM1 RESET 2 1 1 1 2 1 1 Input Input AVCC AVSS X1/X2 DVCC DVSS I/O High-frequency oscillator connection pin. Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (All pins shuold be connected with GND (0 V).) 91CP27-7 2003-11-05 TMP91CP27 3. 3.1 Operation This following describes block by block the functions and operation of the TMP91CP27. CPU The TMP91CP27 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91CP27; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91CP27 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (80 s at 4 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fBSYS is set to fc/32 (= fc/16 x 1/2). B B When the reset is accept, the CPU: * Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> PC<23:16> * * * * Value at FFFF00H address Value at FFFF01H address Value at FFFF02H address Sets the stack pointer (XSP) to 100H. Sets bits When reset is released, the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. * Initializes the internal I/O registers. * * Note: Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Sets ALE pin to high impedance. The CPU internal register (except to PC, SR, XSP in CPU) and internal RAM data do not change by resetting. Figure 3.1.1 is a reset timing chart of the TMP91CP27. 91CP27-8 2003-11-05 fFPH Sampling Sampling RESET A16 to A21 (P40 to P42 input mode) (P20 to P25 input mode) CS0 to CS2 ALE Address (P00 to P07, P10 to P17 input mode) (P30 output mode) Address (P31 output mode) (P32 input mode) (Output mode) (Input mode) (Input mode) Data-out Address (After reset released, starting 2 waits read cycle.) Address AD0 to AD15 Read Figure 3.1.1 TMP91CP27 Reset Timing Chart 91CP27-9 (P00 to P07, P10 to P17 input mode) RD AD0 to AD15 Write WR HWR P30 to P31 P32, P40 to P42 P00 to P07, P10 to P17, P20 to P25, P60 to P63, P70 to P74, P80 to P83, P90 to P97 TMP91CP27 2003-11-05 Pull up (Internal) High impedance TMP91CP27 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91CP27. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H Internal RAM (4 Kbytes) 002000H 64-Kbyte area (nn) 010000H External memory 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FF4000H 48-Kbyte Internal ROM FFFF00H FFFFFFH Vecter table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map 91CP27-10 2003-11-05 TMP91CP27 3.3 Diversity of TMP91CW12A and TMP91CP27 TMP91CP27 is article cut function and pin from TMP91CW12A fundamentally. Specification of function shows section 3.3.1 to 3.3.6. Wide difference of AC/DC characteristic is AC characteristics (Shown section 3.3.7). For the details, please refer to Chapter 4, "Electrical characteristics". 3.3.1 Cut Internal I/O TMP91CP27 is micro controller cut 8-bit timer (TMRA6 to TMRA7), 16-bit timer (TMRB1) and clock doublers circuit (DFM) from TMP91CW12A. Please don't access to special function register address of above internal I/O in TMP91CW12A. Please refer to "Table of special function register". 3.3.2 Cut Port Function TMP91CP27 be cut below port function from TMP91CW12A. * Port 2: P27 (A23/A7) and P26 (A22/A6) * Port 3: P37, P36 ( R / W ), P35 ( BUSAK ), P34 ( BUSRQ ) and P33 ( WAIT ) * Port 4: P43 ( CS3 ) * Port 5: P57 to P54 (AN7 to AN4) * Port 6: P66, P65 and P64 (SCOUT) * Port 7: P75 (TA7OUT) * Port 8: P87 (TB1OUT1), P86 (TB1OUT0), P85 (TB1IN1/INT8) and P84 (TB1IN0/INT7) * Port A: PA7 to PA4, PA3 to PA0 (INT4 to INT1) 3.3.3 Cut factor of Interrupt TMP91CP27 be cut factor of interrupt by cut internal I/O and port function (Refer to Table 3.5.1). Please don't access to interrupt priority setting register for cut factor of interrupt. Please refer to "table of special function register". 3.3.4 Bus Release Function TMP91CP27 don't include bus release function by cutting bus request pin (P34) and bus acknowledge pin (P35). 3.3.5 CS/WAIT Controller When set TMP91CP27 to BxCS 91CP27-11 2003-11-05 TMP91CP27 3.3.6 AD Converter Analog input pin AN4 to AN7 be cut. Therefore please don't select cutting channel in ADMOD1 3.3.7 AC Characteristic When accessing to external, AC characteristic don't guarantee at 2 V operation. 91CP27-12 2003-11-05 TMP91CP27 3.4 System Clock Function and Standby Control TMP91CP27 contains (1) a clock gear, (2) stand-by controller and (3) noise-reduction circuit. It is used for low-power and low-noise systems. The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins). Figure 3.4.1 shows a transition figure. Reset (fBOSCH/32) B IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Release NORMAL mode (fBOSCH/gear value/2) B Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fBOSCH/32) B IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) Release NORMAL mode (fBOSCH/gear value/2) B Instruction Interrupt STOP mode (Stops all circuits) Instruction SLOW mode (fs/2) Dual clock mode transition fiigure Instruction Figure 3.4.1 Clock Operating Mode Note: The clock frequency input from the X1 and X2 pins is called fBOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 B B B B B B B B B B 91CP27-13 2003-11-05 TMP91CP27 3.4.1 Block Diagram of System Clock SYSCR0 B Warm-up timer (for high/low frequency oscillator) T T0 SYSCR0 Lowfrequency oscillator /2 /4 fs fs /2 fBFPH B fBSYS B fc SYSCR0 Highfrequency oscillator fBOSCH B fc/2 fc/4 fc/8 fc/16 SYSCR1 /2 /4 /8 /16 Clock gear SYSCR1 fBSYS TMRA01 to TMRA45 T0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt controller WDT I/O port ADC SIO0 to SIO1 Prescaler SBI T Prescaler RTC fs Binary counter Figure 3.4.2 Block Diagram of System Clock 91CP27-14 2003-11-05 TMP91CP27 3.4.2 SFR 7 SYSCR0 Bit symbol (00E0H) Read/Write After reset Function XEN 1 Highfrequency oscillator (fc) 6 XTEN 0 Lowfrequency oscillator (fs) 5 RXEN 1 4 RXTEN 0 Lowfrequency oscillator (fs) after release of STOP mode R/W 3 RSYSCK 0 2 WUEF 0 1 PRCK1 0 00: fBFPH B B 0 PRCK0 0 Highfrequency oscillator (fc) after release of 0: Stop 0: Stop 1: Oscillation 1: Oscillation STOP mode Selects Warm-up clock after timer release of control STOP 0 Write: mode Don't care 0: fc 1: fs 1 Write: Start warm-up 0 Read: End warm-up 1 Read: Do not end warm-up Select prescaler clock 01: Reserved 10: fc/16 11: Reserved (Note 2) 0: Stop 0: Stop 1: Oscillation 1: Oscillation 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 6 5 4 3 SYSCK 0 Select system clock 0: fc 1: fs 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 Bit symbol (00E2H) Read/Write After reset Function 6 - R/W 0 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before HALT Write to "0". Select warm-up time for oscillator 00: Reserved 01: 2P8 11: 2P P/inputted frequency frequency frequency 10: 2P14 16 P/inputted P/inputted Note 1: Note 2: SYSCR1 B B Figure 3.4.3 SFR for System Clock 91CP27-15 2003-11-05 TMP91CP27 7 EMCCR0 Bit symbol (00E3H) Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 - R/W 0 Write "0". 5 - R/W 1 Write "1". 4 - R/W 0 Write "0". 3 ALEEN R/W 0 1: ALE output enable 0: ALE output disable 2 EXTIN R/W 0 1: fc external clock 1 DRVOSCH R/W 1 0 DRVOSCL R/W 1 fc oscillator fs oscillator driver ability driver ability 1: NORMAL 1: NORMAL 0: WEAK 0: WEAK EMCCR1 Bit symbol (00E4H) Read/Write After reset Function Protect OFF by writing "1FH". Protect ON by writing except "1FH". Figure 3.4.4 SFR for Noise Reduction 91CP27-16 2003-11-05 TMP91CP27 3.4.3 System Clock Controller The system clock controller generates the system clock signal (fBSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 B B B B For example, fBSYS is set to 0.5 MHz when the 16 MHz oscillator connected to the X1 and X2 pins. B B (1) Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2 01 (2P 8 P/frequency) Change to NORMAL (fc) 16 [s] Change to SLOW (fs) 7.8 [ms] 500 2000 [ms] [ms] At fBOSCH = 16 MHz, fs = 32.768 kHz B B 10 (2P14 11 (2P16 P/frequency) 1.024 [ms] 4.096 [ms] P/frequency) 91CP27-17 2003-11-05 TMP91CP27 Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET BIT JR SET RES 00E0H 00E1H 00E2H (SYSCR2), X-11- -X-B 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) WUP: ; ; ; ; ; ; ; Sets warm-up time to 2P16 Enables low-frequency oscillation. Clears and starts warm-up timer. P/fs. Detects stopping of warm-up timer. Changes fBSYS from fc to fs. Disables high-frequency oscillation. B B X: Don't care, -: No change Warm-up timer End of warm-up timer B Counts up by fs fc fs Enables low-frequency Clears and starts warm-up timer Chages fBSYS from fc to fs B Disabiles high-frequency End of warm-up timer 91CP27-18 2003-11-05 TMP91CP27 Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET BIT JR RES RES 00E0H 00E1H 00E2H (SYSCR2), X-10- -X-B 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) WUP: ; ; ; ; ; ; ; Sets warm-up time to 2P14 Enables high-frequency oscillation. Clears and starts warm-up timer. P/fc. Detects stopping of warm-up timer. Changes fBSYS from fs to fc. Disables low-frequency oscillation. B B X: Don't care, -: No change B Counts up by fBOSCH B fs fc Enables high-frequency Clears and starts warm-up timer Chages fBSYS from fs to fc B End of warm-up timer Disables low-frequency 91CP27-19 2003-11-05 TMP91CP27 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 B B either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fBFPH reduces power consumption. B B Below show example of changing clock gear. Example 3: Changing to a clock gear SYSCR1 EQU LD X: Don't care 00E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. (Clock gear changing) To change the clock gear, write the register value to the SYSCR1 SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed. 91CP27-20 2003-11-05 TMP91CP27 3.4.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA45, TMRB0, SIO0 to SIO1 and SBI) there is a prescaler which can divide the clock. The T, T0 clock input to the prescaler is either the clock fBFPH divided by 2 or the clock fc/16 divided by 4. The setting of the SYSCR0 B B 91CP27-21 2003-11-05 TMP91CP27 3.4.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) Output ALE pin disable (5) SFR protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 to EMCCR1 registers. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fBOSCH B C1 Resonator X1 pin Enable oscillation (STOP + EMCCR0 C2 X2 pin (Setting method) The drivability of the oscillator is reduced by writing "0" to EMCCR0 91CP27-22 2003-11-05 TMP91CP27 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 XT1 pin Enable oscillation EMCCR0 B Resonator C2 XT2 pin (Setting method) The drivability of the oscillator is reduced by programming 0 to the EMCCR0 fBOSCH B X1 pin Enable oscillation (STOP+EMCCR0 EMCCR0 X2 pin (Setting method) The oscillator is disabled by programming "1" to EMCCR0 91CP27-23 2003-11-05 TMP91CP27 (4) Output ALE pin disable (Purpose) Not need noise of clock property case of don't access external area is reduced. (Block diagram) EMCCR0 ALE pin (Setting method) Output buffer of ALE pin is output disable by programming "0" to EMCCR0 91CP27-24 2003-11-05 TMP91CP27 (5) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller) is changed. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear (write enable only EMCCR1) SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) Protect register EMCCR0 Write except "1FH" to EMCCR1 Write "1FH" to EMCCR1 S R Q Write signal to specified SFR Write signal to other SFR Write signal to SFR (Setting method) If writing except "1FH" code to EMCCR1 register, it become protect ON. By this operation, write operation to specified SFR is disabling. If writing "1FH" to EMCCR1 register, it become protect OFF. State of protect can to confirm by reading EMCCR0 91CP27-25 2003-11-05 TMP91CP27 3.4.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 TMRA01 TMRA23 TMRA45 TMRB0 SIO0 SIO1 SBI AD converter WDT SFR TA01RUN b. c. IDLE1: Only the oscillator and the RTC (Real time clock) continue to operate. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.4.3. Table 3.4.3 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O port TMRA, TMRB Block SIO, SBI AD WDT RTC Interrupt controller Operate enable Operate IDLE2 11 IDLE1 10 STOP 01 See Table 3.4.6, Table 3.4.7. Stop Stop Keep the state when the HALT instruction was executed. Available to select operation block 91CP27-26 2003-11-05 TMP91CP27 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register B B * Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessry enough resetting time (See Table 3.4.5 ) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction is executed.) 91CP27-27 2003-11-05 TMP91CP27 Table 3.4.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of Halt state clearance NMI INTWD INT0 (Note1) INTRTC INT5 to INT6 INTTA0 to INTTA5 INTTB00, INTTB01, OF0 INTRX0 to INTRX1, INTTX0 to INTTX1 INTSBI INTAD RESET Interrupt Enable (Interrupt level) (Interrupt mask) Interrupt Disable (Interrupt level) < (Interrupt mask) IDLE2 (Note 2) IDLE1 STOP x IDLE2 - - IDLE1 STOP - - - - P*1 P x x x x x x x P *1 P x x x x x x x Initialize LSI x x x x x x x x x x x x P *1 P x x x x x x x : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. (Interrupt routine don't execute.) x: It can not be used to release the HALT mode. -: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold high level until starting interrupt process. If low level was set before interrupt process is stared, interrupt process is not started correctly. Note 2: If using external interrupt INT5 to INT6 in IDLE2 mode, set 16-bit timer RUN register TB0RUN Address 8203H 8206H 8209H 820BH 820EH INT0 Interrupt LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets CPU interrupt level to 5. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91CP27-28 2003-11-05 TMP91CP27 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A21 ALE AD0 to AD15 RD WR Address Data Address Address Data Address Address + 2 Interrupt for release halt IDLE2 mode Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (e.g., restart of operation) is synchronous with it. Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A21 ALE AD0 to AD15 RD WR Address Data Address Data Address Address + 2 Interrupt for release halt IDLE1 mode Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91CP27-29 2003-11-05 TMP91CP27 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. Pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A21 ALE AD0 to AD15 RD Address Data Address Data Address Address + 2 WR Interrupt for release halt STOP mode Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.4.5 Sample Warm-up Times after Clearance of STOP Mode @ fBOSCH = 16 MHz, fs = 32.768 kHz B B SYSCR0 0 (fc) 1 (fs) SYSCR2 16 8 P) 10 (2P 500 14 P) 11 (2P 2000 16 P) s 1.024 ms ms 4.096 ms ms 7.8 ms 91CP27-30 2003-11-05 TMP91CP27 Example: * Address SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H NMI pin input The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to NMI. EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), X-1001X1B ; fBSYS = fs/2 ; Sets warm-up time to 2P14 (SYSCR0), -11000 - - B ; Operates high frequency after released. B B P/fc Clears and starts warm-up timer (High frequency) END NMI interrupt routine 9006H LD XX, XX RETI -: No change Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of "HALT" instruction (during 6 state). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode. 91CP27-31 2003-11-05 TMP91CP27 Table 3.4.6 Input Buffer State Table Input Buffer State When the CPU is Operating During Reset When Used as Function Pin ON upon external read ON ON upon port read When Used as Input Port Port Name Input Function Name In HALT mode (IDLE2/IDLE1) When When Used as Used as Function Input Port Pin OFF OFF In HALT modeSTOP When Used as Function Pin OFF OFF When Used as Input Port When Used as Function Pin OFF When Used as Input Port P00-07 P10-17 P20-25 P32(*1) P40-42(*1) P50-52(*2) P53(*2) P60 P61 P62 P63 P70 P71 P72 P73 P74 P80 P81 P82 P83 P90 P91 P92 P93 P94 P95 P96 P97 /NMI /RESET AM0,AM1 X1 AD0-7 AD8-15 OFF /ADTRG SCK SDA SI SCL INT0 TA0IN TA4IN TB0UN0 INT5 TB0IN1 INT6 RXD0 SCLK0 /CTS0 RXD1 SCLK1 /CTS1 For oscillator XT1 For port OFF ON ON OFF - ON OFF OFF ON ON ON ON OFF ON OFF ON ON ON ON ON ON ON ON ON ON OFF OFF ON - - - - OFF ON ON OFF OFF ON ON OFF ON ON ON OFF OFF ON ON ON ON OFF - OFF OFF ON OFF OFF ON ON OFF - - - ON: The buffer is always turned on. A current *1:Port having a pull-up/pull-down resistor. flows the input buffer if the input pin is not driven. *2:AIN input does not cause a current to flow through the OFF :The buffer is always turned off. buffer. -: No applicable 91CP27-32 2003-11-05 TMP91CP27 Table 3.4.7 Output buffer State Table Output Buffer State When the CPU is Operating During When Reset Used as Function Pin P00-07 P10-17 AD0-7 AD8-15 A8-15 P20-25 P30 P31 P32(*1) P40-42(*1) P60 P61 P62 P63 P70 P71 P72 P73 P74 P80 P81 P82 P83 P90 P91 P92 P93 P94 P95 P96 P97 ALE X2 A0-5 A16-21 /RD /WR /HWR /CS0 /CS1 /CS2 SCK SDA SO SCL TA1OUT TA3OUT TA5OUT TB0OUT0 TB0OUT1 TXD0 SCLK0 TSD1 SCLK1 For oscillator XT2 For port OFF ON upon external write When Used as Output Port Port Name Output Function Name In HALT mode (IDLE2/IDLE1) When Used as Function Pin OFF When Used as Output Port In HALT modeSTOP When Used as Function Pin OFF When Used as Output Port When Used as Function Pin When Used as Output Port ON OFF ON ON ON ON OFF ON - ON ON ON - ON ON ON - ON OFF OFF - OFF ON ON ON ON OFF ON ON ON ON ON OFF ON ON ON ON OFF ON OFF ON OFF ON - OFF OFF OFF OFF ON - ON OFF ON OFF ON OFF ON - ON: The buffer is always turned on. OFFThe buffer is always turned off. -:No applicable *1 Port having a pull-up/pull-down resistor. 91CP27-33 2003-11-05 TMP91CP27 3.5 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register 91CP27-34 2003-11-05 TMP91CP27 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? No Yes Clear interrupt requenst flag Interrupt vector value "V" read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA trasfer and interrupt (INTTC0 to INTTC3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.5.1 Overall Interrupt Processing Flow 91CP27-35 2003-11-05 TMP91CP27 3.5.1 General-Purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 91CP27-36 2003-11-05 TMP91CP27 Table 3.5.1 TMP91CP27 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Maskable Non-maskable Type Interrupt Source and Source of Micro DMA Request "RESET" or SWI0 instruction SWI1 instruction INTUNDEF: Illegal Instruction or SWI2 instruction SWI3 instruction SWI4 instruction SWI5 instruction SWI6 instruction SWI7 instruction NMI pin Vector Value (V) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H Micro DMA Start Vector - - - - - - - - - - - 0AH INTWD: Watchdog timer (Micro DMA) INT0 pin Reserved Reserved Reserved Reserved INT5 pin INT6 pin Reserved Reserved INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 Reserved Reserved INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) Reserved Reserved INTTBOF0: 16-bit timer 0 (Over flow) Reserved INTRX0: Serial reception (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial reception (Channel 1) INTTX1: Serial transmission (Channel 1) INTSBI: Serial bus interface interrupt INTRTC: Interrupt for RTC INTAD: AD conversion end INTTC0: End of Micro DMA (Channel 0) INTTC1: End of Micro DMA (Channel 1) INTTC2: End of Micro DMA (Channel 2) INTTC3: End of Micro DMA (Channel 3) (Reserved) : (Reserved) - - - - 003CH 0040H - - - - FFFF3CH FFFF40H - - - - 0FH 10H - - 004CH 0050H 0054H 0058H 005CH 0060H - - FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H - - 13H 14H 15H 16H 17H 18H - - 006CH 0070H - - FFFF6CH FFFF70H - - 1BH 1CH - - 007CH - - FFFF7CH - - 1FH - 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H : 00FCH - FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H : FFFFFCH - 21H 22H 23H 24H 25H 26H 27H - - - - - : - 91CP27-37 2003-11-05 TMP91CP27 3.5.2 Micro DMA In addition to general-purpose interrupt processing, the TMP91CP27 supports a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifying the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority highest level and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on 91CP27-38 2003-11-05 TMP91CP27 Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see 3.5.2 (4) "Detailed description of the transfer mode register: DMAM0 to DMAM3". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 19 interrupts shown in the micro DMA start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 20 interrupts. Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for Counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numbered values). 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Address Source Destination Address + 2 D0 to D5 Input Output Figure 3.5.2 Timing for Micro DMA Cycle (Word transfer) States 1 to 3: Instruction fetch cycle (gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycles State 6: Dummy cycle (The address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91CP27-39 2003-11-05 TMP91CP27 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91CP27 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once. At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to "0". Only one-channel can be set once for micro DMA. (Do not write "1" to plural bits.) When writing again "1" to the DMAR register, check whether the bit is "0" before writing "1". When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. Symbol Name DMA software request register Address 7 6 5 4 3 DMAR3 0 2 DMAR2 0 1 DMAR1 0 0 DMAR0 0 DMA request 89H R/W DMAR (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU. An instruction of the form "LDC cr,r" can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA Source address register 0: Only use LSB 24 bits DMA Destination address register 0: Only use LSB 24 bits DMA Counter register 0: 1 to 65536 DMA Mode register 0 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA Source address register 3 DMA Destination address register 3 DMA Counter register 3 DMA Mode register 3 91CP27-40 2003-11-05 TMP91CP27 (4) Detailed description of the transfer mode register: DMAM0 to DMAM3 (DMAM0 to DMAM3) 0 0 0 Mode Note: The upper three bits of data programmed to these registers must always be 0. Execution time ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved 0 0 0 Z Z Transfer destination address INC mode..................... I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer destination address DEC mode ................... I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address INC mode ........................... Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address DEC mode.......................... Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Address fixed mode........................................................... I/O to I/O (DMADn) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Counter mode for counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTC is generated 8 states (1000 ns) @ byte/word transfer 12 states (1500 ns) @4-byte transfer 8 states (1000 ns) @ byte/word transfer 12 states (1500 ns) @4-byte transfer 8 states (1000 ns) @ byte/word transfer 12 states (1500 ns) @4-byte transfer 8 states (1000 ns) @ byte/word transfer 12 states (1500 ns) @4-byte transfer 8 states (1000 ns) @ byte/word transfer 12 states (1500 ns) @4-byte transfer 5 states (625 ns) 0 0 1 Z Z 0 1 0 Z Z 0 1 1 Z Z 1 0 0 Z Z 1 0 1 0 0 Note 1: "n" is the corresponding micro DMA channels 0 to 3 DMADn+/DMASn+: Post increment (Increment register value after transfer) DMADn-/DMASn-: Post decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width/0 waits. fc = 16MHz/selected high frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91CP27-41 2003-11-05 TMP91CP27 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 25 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: * * * * * When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt (Program DMA start vector to INTCLR register) When the CPU receives a micro DMA request (When micro DMA is set.) When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE56). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts ( NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 91CP27-42 2003-11-05 Interrupt controller Interrupt request F/F 1 Interrupt enable F/F in CPU side Reset IFF2:0 S Q Reset R Interrupt vector read V = 20H V = 24H CPU NMI INTWD Priority setting register Dn A B Dn + 1 Dn + 2 C Decorder 1 7 3 INTRQ2 to 0 6 6 Highest priority interrupt level select A B C Priority encorder 3 3 Interrupt request signal to CPU Interrupt level detect EI1 to 7 DI Interrupt request signal D Q CLR Interuupt request F/F Dn + 3 Interrupt request F/F read 25 V = 3CH V = 40H V = 4CH Y1 Y2 Y3 Y4 Y5 Y6 INT0 Reset SQ R D0 D1 Interrupt vector read micro DMA acknoeledge Interrupt vector generator D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 If INTRQ2 to 0 IFF 2 to 0 then 1. INT5 INT6 INTTA0 During IDLE1 During STOP Figure 3.5.3 Block Diagram of Interrupt Controller 91CP27-43 V = 9CH V = A0H V = A4H V = A8H V = ACH Micro DMA start vector setting register Interrupt vector V read HALT release RESET INT0, INTRTC NMI 4-input OR 4 If IFF = 7 then 0 A 2 Micro DMA request Micro DMA counter zero interrupt INTAD INTTC0 INTTC1 INTTC2 INTTC3 Soft start 19 S Selector D5 D4 D3 D2 D1 D0 DQ CLR 6 INTTC0 RESET 2 DMA0V DMA1V DMA2V DMA3V 0 1 2 3 B Micro DMA channel priority encorder Micro DMA channel specification TMP91CP27 2003-11-05 TMP91CP27 (1) Interrupt level setting registers Symbol Name INT0 & INTAD enable Address 7 IADC R 0 6 INTAD IADM2 0 INT6 I6M2 0 ITA1M2 0 ITA3M2 0 ITA5M2 0 5 IADM1 R/W 0 I6M1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 4 IADM0 0 I6M0 0 ITA1M0 0 ITA3M0 0 ITA5M0 0 3 I0C R 0 I5C R 0 ITA0C R 0 ITA2C R 0 ITA4C R 0 2 INT0 I0M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 0 1 I0M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 0 I0M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 0 INTE0AD 90h INTE56 INT5 & INT6 enable 93h I6C R 0 INTTA1 (TMRA1) INTTA0 & INTETA01 INTTA1 enable 95h ITA1C R 0 INTTA2 & INTETA23 INTTA3 enable INTETA45 INTTA4 & INTTA5 enable 97h ITA5C R 0 ITA3C R 0 INTTA0 (TMRA0) INTTA3 (TMRA3) 96h INTTA2 (TMRA2) INTTA5 (TMRA5) INTTA4 (TMRA4) Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disable interrupt request Setting interrupt priority level to "1". Setting interrupt priority level to "2". Setting interrupt priority level to "3". Setting interrupt priority level to "4". Setting interrupt priority level to "5". Setting interrupt priority level to "6". Disable interrupt request 91CP27-44 2003-11-05 TMP91CP27 Symbol Name Interrupt enable TMRB0 Address 7 ITB01C R 0 6 ITB01M2 5 ITB01M1 4 ITB01M0 3 ITB00C R 0 ITF0C 2 ITB00M2 1 ITB00M1 0 ITB00M0 INTTB01 (TMRB0) INTETB0 99H R/W 0 0 0 INTTB00 (TMRB0) R/W 0 ITF0M2 0 INTRX0 ITX0M0 0 ITX1M0 0 IRTCM0 0 ITC1M0 0 ITC3M0 0 IRX0C R 0 IRX1C R 0 IS2C R 0 ITC0C R 0 ITC2C R 0 0 0 INTTC2 ITC2M2 ITC2M1 R/W 0 0 ITC2M0 0 INTTC0 ITC0M2 ITC0M1 R/W 0 0 ITC0M0 0 INTSBI IS2M2 IS2M1 R/W 0 0 IS2M0 0 INTRX1 IRX1M2 IRX1M1 R/W 0 0 IRX1M0 IRX0M2 IRX0M1 R/W 0 0 IRX0M0 0 ITF0M1 R/W 0 0 0 ITF0M0 INTTBOF0 (TMRB0 over flow) Interrupt enable INTETB01V TMRB0 (over flow) 9BH R 0 ITX0C R 0 0 0 R/W 0 INTTX0 ITX0M1 R/W 0 INTTX1 ITX1M1 R/W 0 INTRTC IRTCM2 0 INTTC1 ITC1M2 0 INTTC3 ITC3M2 0 0 IRTCM1 R/W 0 ITC1M1 R/W 0 ITC3M1 R/W 0 0 R 0 INTES0 Interrupt enable Serial 0 9CH ITX0M2 INTES1 Interrupt enable serial 1 9DH ITX1C R 0 ITX1M2 INTES2RTC Interrupt enable SBI/RTC 9EH IRTCC R 0 INTETC01 INTTC0 & INTTC1 enable INTTC2 & INTTC3 enable A0H ITC1C R 0 ITC3C R 0 INTETC23 A1H Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disable interrupt request Setting interrupt priority level to "1". Setting interrupt priority level to "2". Setting interrupt priority level to "3". Setting interrupt priority level to "4". Setting interrupt priority level to "5". Setting interrupt priority level to "6". Disable interrupt request 91CP27-45 2003-11-05 TMP91CP27 (2) External interrupt control Symbol Name Address 7 - 0 6 - 0 5 - 0 4 - W 3 - 0 2 I0EDGE 0 INT0 edge 1 I0LE 0 INT0 mode 0: Edge 1: Level 0 NMIREE 0 1: Operate even on rising/ falling edge of NMI IIMC Interrupt input mode control 8CH (Prohibit RMW) 0 Write "0". 0: Rising 1: Falling INT0 level enable 0 1 0 1 edge detect interrupt "H" level interrupt Interrupt request generation at falling edge Interrupt request generation at rising/falling edge NMI rising edge enable (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Symbol Name Interrupt clear control Clears interrupt request flag INT0 6 5 CLRV5 Address 88H (Prohibit RMW) 7 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 0 Interrupt vector (4) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining) 91CP27-46 2003-11-05 TMP91CP27 Symbol Name DMA0 start vector Address 7 6 5 DMA0V5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0 start vector DMA0V 80H R/W DMA1 start vector DMA1V DMA1 start vector 81H DMA1V5 0 DMA2 start vector DMA2V5 0 DMA3 start vector DMA3V5 0 R/W DMA2 start vector DMA2V 82H R/W DMA3 start vector DMA3V 83H R/W (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to "1" specifies a burst. Symbol Name DMA software request register DMA burst request register Address 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 DMAR 89H 1: DMA software request R/W 0 1: DMA request on Burst Mode DMAB 8AH 91CP27-47 2003-11-05 TMP91CP27 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (*1) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the above program, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1 instructions (Example: "NOP" * 1 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register INT0 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag NOP ; Wait EI instruction EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by an instruction. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to Level Mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in Level Mode. (H L) INTRX: Instruction which read the receive buffer 91CP27-48 2003-11-05 TMP91CP27 3.6 Port Function The TMP91CP27 features 53 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin. Table 3.6.2 to Table 3.6.3 lists I/O registers and their specifications. Table 3.6.1 Port Function (R: = with pull-up resistor) Number of Port Names Pin Names Pins Port 0 Port 1 Port 2 Port 3 P00 to P07 P10 to P17 P20 to P25 P30 P31 P32 P40 P41 P42 P50 to P53 P60 P61 P62 P63 P70 P71 P72 P73 P74 P80 P81 P82 P83 Port 9 P90 P91 P92 P93 P94 P95 P96 P97 8 8 6 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O I/O Output Output I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - - - - - - - - - - - - - - - - - - - - Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Names for Built-in Functions AD0 to AD7 AD8 to AD15/A8 to A15 A16 to A21/A0 to A5 RD WR HWR Port 4 CS0 CS1 CS2 Port 5 Port 6 AN0 to AN3, ADTRG (P53) SCK SO/SDA SI/SCL INT0 TA0IN TA1OUT TA3OUT TA4IN TA5OUT TB0IN0/INT5 TB0IN1/INT6 TB0OUT0 TB0OUT1 TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1 XT1 XT2 Port 7 Port 8 91CP27-49 2003-11-05 TMP91CP27 Table 3.6.2 I/O Port Setting List (1/2) Ports Port 0 Pin Names P00 to P07 Input port Output port Specifications I/O Register Setting Values Pn x x x x x x x x x x x x 1 0 x x 0 1 x x 0 1 x x x x x None 0 0 1 1 0 0 1 1 1 1 None 0 1 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 0 1 1 PnCR 0 1 x 0 1 0 1 0 1 0 1 PnFC None 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 AD0 to AD7 bus Port 1 P10 to P17 Input port Output port AD8 to AD15 bus A8 to A15 Port 2 P20 to P25 Input port Output port A0 to A5 output A16 to A21 output Port 3 P30 Output port RD output only when accessing an external area Always RD output P31 Output port WR output only when accessing an None external area P32 Input port (without pull up) Input port (with pull up) Output port HWR output Port 4 P40 to P42 Input port (without pull up) Input port (with pull up) Output port P40 P41 P42 Port 5 P50 to P53 P53 Port 6 P60 to P63 P60 P61 CS0 output CS1 output CS2 output Input port AN0 to AN3 input ADTRG input (Note 1) (Note 2) x x x x x x x Input port Output port SCK input SCK output SDA input SDA output SO output (Note 3) x x x x P62 SI input SCL input SCL output (Note 3) x x P63 X: Don't care INT0 input Note 1: If use P50 to P53 as input channels of AD converter, channel selection set by using ADMODE1 91CP27-50 2003-11-05 TMP91CP27 Table 3.6.3 I/O Port Setting List (2/2) Ports Port 7 Pin Names P70 to P74 P70 P71 P72 P73 P74 Input port Output port Specifications I/O Register Setting Values Pn x x x x x x x x x x x x x x x x x x x x x x x x x x PnCR 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 0 PnFC 0 0 None 1 1 None 1 0 0 1 1 1 1 0 0 1 None 0 1 0 1 None 0 1 0 None TA0IN input TA1OUT output TA3OUT output TA4IN input TA5OUT output Input port Output port TB0IN0, INT5 input TB0IN1, INT6 input TB0OUT0 output TB0OUT1 output Input port Output port TXD0 output RXD0 input SCLK0 input SCLK0 output CTS0 input Port 8 P80 to P83 P80 P81 P82 P83 Port 9 P90 to P95 P90 P91 P92 P93 P94 P95 TXD1 output RXD1 input SCLK1 input SCLK1 output CTS1 input P96 to P97 Input port Output port XT1 to XT2 (Note 4) (Note 5) x x X: Don't care Note 4: If use P96 to P97 as output port, it be set open-drain buffer. Note 5: If use P96 to P97 as XT1 to XT2, enabling oscillation and so on are set by using SYSCR0 register. By resetting, these port pin become general-purpose input port. And it become input port except P96/XT1 and P97/XT2 that input pin of input and output is programmable. When use port pin to internal function, need setting by program. 91CP27-51 2003-11-05 TMP91CP27 3.6.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Resetting, reset all bits of the control register P0CR to "0" and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 can also function as address data bus (AD0 to AD7). When access external memory, port 0 function as address data bus (AD0 to AD7) and P0CR be cleared to "0". Reset External access Direction control (on bit basis) P0CR write AS Selector Output buffer External access (Data write) Internal data bus Output latch Port 0 P00 to P07 (AD0 to AD7) P0 write AD0 to AD7 B P0 Read External access (Data read) Figure 3.6.1 Port 0 91CP27-52 2003-11-05 TMP91CP27 3.6.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and function register P1FC. Resetting reset all bits of output latch P1, the control register P1CR and function register P1FC to "0" and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as address data bus (AD8 to AD15) and address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control Internal data bus (on bit basis) P1FC write Output latch Output buffer P1 write Port 1 P10 to P17 (AD8 to AD15/A8 to A15) P1 read Figure 3.6.2 Port 1 91CP27-53 2003-11-05 TMP91CP27 Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register is undefined.) Port 0 Control Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 0 0 0 P07C 6 P06C 5 P05C 4 P04C W 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: Input 1: Output (When access to external, become AD7 to AD0 and this register is cleared to "0".) Port I/O setting 0 1 Input Output Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to "0".) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 < Port 1 Function Register 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 0 0 0 P17F 6 P16F 5 P15F 4 P14F W 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8 Note: Read-modify-write instructions are prohibited for registers P0CR, P1CR and P1FC. Port1 function setting P1FC 1 Address data bus (AD15 to AD8) Address bus (A15 to A8) Note: Figure 3.6.3 Register for Ports 0 and 1 91CP27-54 2003-11-05 TMP91CP27 3.6.3 Port 2 (P20 to P25) Port 2 is an 6-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and function register P2FC. Resetting, set all bits of output latch P2 to "1", and reset the control register P2CR and function register P2FC to "0" and sets port 2 to input mode. In addition to functioning as a general-purpose I/O port, port 2 can also function as address bus (A0 to A5) and address bus (A16 to A21). Selector S Direction control (on bit basis) A16 to A21 A0 to A5 Reset B A Y P2CR write Internal data bus Function control (on bit basis) P2FC write S Output latch A Selector B Y Output buffer Port 2 P20 to P25 (A0 to A5/A16 to A21) P2 write P2 read Figure 3.6.4 Port 2 91CP27-55 2003-11-05 TMP91CP27 Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset 6 5 P25 4 P24 3 P23 R/W 2 P22 1 P21 0 P20 Data from external port (Output latch register is set to "1".) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 0 0 6 5 P25C 4 P24C 3 P23C W 2 P22C 0 1 P21C 0 0 P20C 0 < Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function 0 0 0 6 5 P25F 4 P24F 3 P23F W 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input, 01: Output, 10: A5 to A0, 11: A21 to A16 Note: Read-modify-write instructions are prohibited for registers P2CR and P2FC. Port 2 function setting P2FC 1 Address bus (A5 to A0) Address bus (A21 to A16) Note: Figure 3.6.5 Register for Port 2 91CP27-56 2003-11-05 TMP91CP27 3.6.4 Port 3 (P30 to P32) Port 3 is a 3-bit general-purpose I/O port (however P30 and P31 is only output port). Each bit can be set individually for input or output using the control register P3CR and function register P3FC. Resetting, all bits of output latch P3 is set to "1", and the control register P3CR (Bit0 and bit1 don't using) and function register P3FC are reset to "0". And P30 and P31 of port 3 output "High", and sets P32 to input mode with pull-up resister. In addition to functioning as a general-purpose I/O port, port 3 can also function as the output for the CPU's control/status signal. Case of P30 is defined as RD signal output mode (Case of Reset Direction control (on bit basis) Internal data bus P3FC write S Selector S Output latch A B P3 write RD P30 ( RD ) Output buffer Internal address area P3 read Figure 3.6.6 Port 3 (P30) 91CP27-57 2003-11-05 TMP91CP27 Reset Function control Internal data bus (on bit basis) P3FC write S Selector S Output latch A B P3 write WR P31 ( WR ) Output buffer Internal address area P3 read Reset Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Selector S Output latch A B P3 write HWR P-ch Programmable pull up P32 ( HWR ) Output buffer P3 read Figure 3.6.7 Port 3 (P31 and P32) 91CP27-58 2003-11-05 TMP91CP27 Port 3 Register 7 P3 (0007H) Bit symbol Read/Write After reset Data from external port Note3 Pull-up resistor 0: OFF 1: ON 6 5 4 3 2 P32 1 P31 R/W 1 0 P30 1 Function Port 3 Control Register 7 P3CR (000AH) Bit symbol Read/Write After reset 6 5 4 3 2 P32C W 0 0: Input 1: Output 1 0 Input/ Output setting 0 Input 1 Output Port 3 Function Register 7 P3FC (000BH) Bit symbol Read/Write After reset Function - W 0 Write "0". 0 0: Port 1: HWR 6 5 4 3 2 P32F 1 P31F W 0 0: Port 1: WR 0 P30F 0 0: Port 1: RD P30 ( RD ) function setting 0 "0" output RD output 1 "1" output RD is only output during external accesses. 1 always. (Correspond to pseudo SRAM) P31 ( WR ) function setting 0 "0" output 1 "1" output WR is only output during external accesses. P32 ( HWR ) function setting 0 Input port - 1 Output port HWR output 0 1 Note 1: Note 2: Read-modify-write instrustions are prohibited for registers P3CR and P3FC. When port 3 is used in Input mode, the P3 register controls the internal pull-up resistor. Read-modify-write instruction is prohibited in Input mode or I/O mode. Setting the internal pull-up resistor may be depend on the states of the input pin. Note 3: Output latch register is set to "1", and pull-up resistor is connected. Figure 3.6.8 Register for Port 3 91CP27-59 2003-11-05 TMP91CP27 3.6.5 Port 4 (P40 to P42) Port 4 is a 3-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P4CR and function register P4FC. Resetting, set P40 to P42 of output register to "1", the control register P4CR and function register P4FC reset to "0" and sets port 4 to input mode with pull-up resistor. In addition to functioning as a general-purpose I/O port, port 4 can also function as chip select output signal ( CS0 to CS2 ). Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write S Selector S Output latch A B P4 write P40 ( CS0 ), P41 ( CS1 ), P42 ( CS2 ) P-ch Programmable pull up Internal data bus Output buffer CS0 , CS1 , CS2 P4 read Figure 3.6.9 Port4 91CP27-60 2003-11-05 TMP91CP27 Port 4 Register 7 Bit symbol P4 (000CH) Read/Write After reset Function 6 5 4 3 2 P42 1 P41 R/W 0 P40 Data from external port Note4 Pull-up resistor 0: OFF 1: ON Port 4 Control Register 7 P4CR (000EH) Bit symbol Read/Write After reset 0 0: Input 6 5 4 3 2 P42C 1 P41C W 0 1: Output 0 P40C 0 Input/Output setting 0 Input 1 Output Port 4 Function Register 7 P4FC (000FH) Bit symbol Read/Write After reset Function 0 6 5 4 3 2 P42F 1 P41F W 0 0: Port 1: CS 0 P40F 0 0 1 Port (P40) CS0 0 1 Port (P41) CS1 0 1 Note 1: Note 2: Read-modify-write instructions are prohibited for registers, P4CR and P4FC. Port (P42) CS2 When port 4 is used in Input mode, the P4 register controls the internal pull-up resistor. Read-modify-write instruction is prohibited in Input mode or I/O mode. Setting the internal pull-up resistor may be depend on the states of the input pin. Note 3: When output chip select signal ( CS0 to CS2 ), set bit of control register (P4CR) to "1" after set bit of function register (P4FC) to "1". Note 4: Output latch register is set to "1", and pull-up resistor is connected. Figure 3.6.10 Register for Port 4 91CP27-61 2003-11-05 TMP91CP27 3.6.6 Port 5 (P50 to P53) Port 5 is a 4-bit input port and can also be used as the analog input pin for the AD converter. P53 can also be used as AD trigger input pin for AD converter. Port 5 Internal data bus Port 5 read P50 (AN0) P51 (AN1) P52 (AN2) P53 (AN3, ADTRG ) AD read Convertion result register AD converter Channel selector ADTRG (only P53) Figure 3.6.11 Port 5 Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset 6 5 4 3 P53 2 P52 R 1 P51 0 P50 Data from external port Figure 3.6.12 Register for Port 5 Note: The input channel selection of AD converter and the permission of AD trigger input of P53 set by AD converter mode register ADMOD1. 91CP27-62 2003-11-05 TMP91CP27 3.6.7 Port 6 (P60 to P63) Port 60 to P63 are 4-bit general-purpose I/O ports. Resetting, set to input port. All bits of output latch register P6 are set to "1". In addition to functioning as a I/O port, port 6 can also function as input or output function of serial bus interface. This function enable each function by writing "1" to applicable bit of Port 6 function register P6FC. Resetting, P6CR and P6FC reset to "0", all bit set input port. (1) Port 60 (SCK) In addition to functioning as an I/O port, port 60 can also function as clock SCK I/O port in SIO mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SCK output A S P60 (SCK) B SB Selector P6 read A SCK input Internal data bus Selector Figure 3.6.13 Port 60 91CP27-63 2003-11-05 TMP91CP27 (2) Port 61 (SO/SDA) In addition to functioning as an I/O port, port 61 can also function as data SDA I/O port in I2C mode or data SO output pin in SIO mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SO output SDA output B Open-drain possible: ODE Internal data bus A S P61 (SO/SDA) Selector Figure 3.6.14 Port 61 91CP27-64 2003-11-05 TMP91CP27 (3) Port 62 (SI/SCL) In addition to functioning as an I/O port, port 62 can also function as data receiving pin in SIO mode or clock SCL I/O pin in I2C bus mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SCL output B Internal data bus A S P62 (SI/SCL) Open-drain possible: ODE Selector Selector P6 read SI input SCL input A Figure 3.6.15 Port 62 91CP27-65 2003-11-05 TMP91CP27 (4) Port 63 (INT0) In addition to functioning as an I/O port, port 63 can also function as INT0 input pin of external interrupt. Reset Direction control (on bit basis) P6CR write Internal data bus Function control (on bit basis) P6FC write S Output latch P6 write SB Selector P6 read A Select level/edge & Select rising/falling IIMC INT0 Figure 3.6.16 Port 63 91CP27-66 2003-11-05 TMP91CP27 Port 6 Registers 7 P6 (0012H) Bit symbol Read/Write After reset 6 5 4 3 P63 2 P62 R/W 1 P61 0 P60 Data from external port (Output latch register is set to "1") Port 6 Control Register 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 0 0: Input 6 5 4 3 P63C 2 P62C W 1 P61C 0 1: Output 0 P60C 0 Port6 I/O setting 0 Input 1 Output Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 6 5 4 3 P63F W 0 0: Port 1: INT0 input 2 P62F W 0 0: Port 1: SCL output 1 P61F W 0 0: Port 1: SDA/SO output 0 P60F W 0 0: Port 1: SCK output P60 SCK output setting P6FC P61 SDA/SO output setting P6FC 1 1 1 0 Figure 3.6.17 Register for Port 6 91CP27-67 2003-11-05 TMP91CP27 3.6.8 Port 7 (P70 to P74) Port 7 is a 5-bit general-purpose I/O port. Resetting, set to input port. In addition to functioning as a I/O port, port 70 and 73 can also function as clock input pin TA0IN, TA4IN of 8-bit timer 0, 4 and port 71, 72, 74 can also function 8-bit timer output pin TA1OUT, TA3OUT, TA5OUT. This timer output function enable each function by writing "1" to applicable bit of Port 7 function register P7FC. Resetting, P7CR and P7FC reset to "0", all bit set input port. Reset Direction control (on bit basis) P7CR write S Output latch P7 write P7 read TA0IN TA4IN Internal data bus A Reset Direction control (on bit basis) P70 (TA0IN) P73 (TA4IN) S B Selector P7CR write Function control (on bit basis) P7FC write S Output latch A P7 write Timer F/F OUT TA1OUT: TMRA01 TA3OUT: TMRA23 TA5OUT: TMRA45 S P71 (TA1OUT) P72 (TA3OUT) P74 (TA5OUT) Selector B B Selector P7 read SA Figure 3.6.18 Port 7 91CP27-68 2003-11-05 TMP91CP27 Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset 6 5 4 P74 3 P73 2 P72 R/W 1 P71 0 P70 Data from external port (Output latch register is set to "1".) Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset Function 0 0 0: Input 6 5 4 P74C 3 P73C 2 P72C W 0 1 P71C 0 1: Output 0 P70C 0 Port 7 I/O setting 0 Input 1 Output Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 6 5 4 P74F W 0 0: Port 1: TA5OUT 3 2 P72F W 0 1 P71F 0 0 0: Port 0: Port 1: TA3OUT 1: TA1OUT P71 timer out 1 output setting P7FC P72 timer out 3 output setting P7FC P74 timer out 5 output setting P7FC Note 1: Note 2: Read-Modify-Write instructions are prohibited for the registers P7CR and P7FC. P70/TA0IN and P73/TA4IN pin does not have a register changing Port/Function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Figure 3.6.19 Register for Port 7 91CP27-69 2003-11-05 TMP91CP27 3.6.9 Port 8 (P80 to P83) Port 8 is a 4-bit general-purpose I/O port. Resetting, set to input port. All bits of output latch register P8 are set to "1". In addition to functioning as a I/O port, port 8 can also function as clock input of 16-bit timer, output of 16-bit timer F/F and input function of INT5 to INT6. This function enable each function by writing "1" to applicable bit of port 8 function register P8FC. Resetting, P8CR and P8FC reset to "0", all bits set input port. (1) P80 to P83 Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch SB P8 write Selector Internal data bus TB0IN0, INT5 TB0IN1, INT6 P80 (TB0IN0/INT5) P81 (TB0IN1/INT6) P8 read Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch AS A Selector B B Selector Timer F/F OUT P8 write TB0OUT0: TMRB0 TB0OUT1: TMRB0 P8 read P82 (TB0OUT0) P83 (TB0OUT1) SA Figure 3.6.20 Port 8 (P80 to P83) 91CP27-70 2003-11-05 TMP91CP27 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset 6 5 4 3 P83 2 P82 R/W 1 P81 0 P80 Data from external port (Output latch register is set to "1".) Port 8 Control Register 7 P8CR (001AH) Bit symbol Read/Write After reset 0 0 0: Input 6 5 4 3 P83C 2 P82C W 1 P81C 0 1: Output 0 P80C 0 Port 8 I/O setting 0 Input 1 Output Port 8 Function Register 7 P8FC (001BH) Bit symbol Read/Write After reset Function 6 5 4 3 P83F W 0 0: Port 2 P82F W 0 0: Port 1 P81F W 0 0: Port 0 P80F W 0 0: Port 1: TB0IN0 1: TB0OUT1 1: TB0OUT0 1: TB0IN1 INT6 input INT5 input P82 TB0OUT0 output setting P8FC P83 TB0OUT1 output setting P8FC Note: Read-modify-write instructions are prohibited for registers P8CR and P8FC. Figure 3.6.21 Register for Port 8 91CP27-71 2003-11-05 TMP91CP27 3.6.10 Port 9 (P90 to P97) * Ports 90 to 95 Ports 90 to 95 are a 6-bit general-purpose I/O port. Resetting, set to input port. All bits of output latch register are set to "1". In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0, SIO1. This function enable each function by writing "1" to applicable bit of port 9 function register P9FC. Resetting, P9CR and P9FC reset to "0", all bits set input port. * Ports 96 to 97 Ports 96 to 97 are a 2-bit general-purpose I/O port. Case of output port, this is open drain output. Resetting, output latch register and control register set to "1", and set to "High-Z" (High impedance). In addition to functioning as a I/O port, ports 96 to 97 can also function as low-frequency oscilator connection pin (XT1 and XT2) during using low speed clock function. Therefore, dual clock function can use by setting of system clock control registers SYSCR0 and SYSCR1. (1) Ports 90 and 93 (TXD0 and TXD1) In addition to functioning as a I/O port, Ports 90 and 93 can also function as TXD output pin of serial channel. And P90 and P93 have a programmable open-drain function which can be controlled by the ODE Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch TXD0, TXD1 A S P90 (TXD0) P93 (TXD1) P9 write Selector B SB Selector Open-drain possible ODE P9 read A Figure 3.6.22 Ports 90 and 93 91CP27-72 2003-11-05 TMP91CP27 (2) Ports 91 and 94 (RXD0 and RXD1) In addition to functioning as a I/O port, ports 91 and 94 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) Internal data bus P9CR write S Output latch P9 write P9 read RXD0, RXD1 P91 (RXD0) P94 (RXD1) S B Selector A Figure 3.6.23 Ports 91 and 94 (3) Ports 92 and 95 ( CTS0 /SCLK0, CTS1 /SCLK1) In addition to functioning as a I/O port, ports 92 and 95 can also function as CTS input pin or SCLK I/O pin of serial channel. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch P9 write SCLK0, 1 output Internal data bus A S P92 (SCLK0/ CTS0 ) P95 (SCLK1/ CTS1 ) Selector B SB Selector P9 read CTS0 , CTS1 A SCLK0, SCLK1 input Figure 3.6.24 Port 92, 95 91CP27-73 2003-11-05 TMP91CP27 (4) Ports 96 (XT1) and 97 (XT2) In addition to functioning as a I/O port, ports 96 and 97 can also function as low frequency oscillator connection pins. Reset S Direction control (on bit basis) P9CR write S Output latch Output buffer (Open-drain output) Low-frequency oscillation enable P96 (XT1) P9 write S B Selector Y A P9 read Internal data bus (ON at 1) S Direction control (on bit basis) P9CR write S Output latch Output buffer (Open-drain output) P97 (XT2) P9 write S B Selector Y A P9 read Low-frequency clock Figure 3.6.25 Ports 96 and 97 91CP27-74 2003-11-05 TMP91CP27 Port 9 Registers 7 P9 (0019H) Bit symbol Read/Write After reset 1 1 P97 6 P96 5 P95 4 P94 R/W 3 P93 2 P92 1 P91 0 P90 Data from external port (Output latch register is set to "1".) Port 9 Control Register 7 P9CR (001CH) Bit symbol Read/Write After reset 1 1 0 0 0: Input P97C 6 P96C 5 P95C 4 P94C W 3 P93C 0 1: Output 2 P92C 0 1 P91C 0 0 P90C 0 Port9 I/O setting 0 Input 1 Note: Ports 96 and 97 are open-drain output pins. Output Port 9 Function Register P9FC (001DH) 7 Bit symbol Read/Write After reset Function 6 5 P95F W 0 0: Port 1: SCLK1 output 4 3 P93F W 0 0: Port 1: TXD1 2 P92F W 0 0: Port 1: SCLK0 output 1 0 P90F W 0 0: Port 1: TXD0 P90 TXD0 output setting P9FC 1 1 1 1 1 1 1 1 Note 3: Figure 3.6.26 Register for Port 9 91CP27-75 2003-11-05 TMP91CP27 3.7 Chip select/Wait Controller On the TM91CP27, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS2 (which can also function as port pins P40 to P42) are the respective output pins for the CS0 to CS2 areas. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS2 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 4 control register P4CR and function register P4FC must be set. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable status, the data bus width and the number of waits for each address area. 3.7.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS2 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See section 3.7.2, "Chip Select/Wait Control Registers".) 91CP27-76 2003-11-05 TMP91CP27 (1) Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in MSAR0 (00C8H) MSAR1 (00CAH) 6 S22 1 5 S21 1 4 S20 R/W 1 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Bit symbol Read/Write After reset Function S23 1 MSAR2 MSAR3 (00CCH) (00CEH) Determines A23 to A16 of start address Sets start addresses for areas CS0 to CS3 Figure 3.7.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Start address register value (MSAR0 to MSAR3) 000000H ...................... 00H 010000H ...................... 01H 020000H ...................... 02H 030000H ...................... 03H 040000H ...................... 04H 050000H ...................... 05H 060000H ...................... 06H : : FF0000H ..................... FFH FFFFFFH Figure 3.7.2 Start Address and Start Address Register Value 91CP27-77 2003-11-05 TMP91CP27 (2) Memory address mask registers Figure 3.7.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MSAR0 to MSAR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to "0" in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (CS0 Area) 7 MAMR0 (00C9H) Bit symbol Read/Write After reset Function 1 1 1 1 Sets area size of CS0. V20 6 V19 5 V18 4 V17 R/W 3 V16 1 2 V15 1 1 V14 to 9 1 0 V8 1 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1 Area) 7 MAMR1 (00CBH) Bit symbol Read/Write After reset Function 1 1 1 1 Sets area size of CS1. V21 6 V20 5 V19 4 V18 R/W 3 V17 1 2 V16 1 1 V15 to 9 1 0 V8 1 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2 and CS3 Area) 7 MAMR2 MAMR3 (00CDH) (00CFH) Bit symbol Read/Write After reset Function 1 1 1 1 V22 6 V21 5 V20 4 V19 R/W 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets area size of CS2 and CS3. 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.7.3 Memory Address Mask Register 91CP27-78 2003-11-05 TMP91CP27 (3) Setting memory start address and address area Figure 3.7.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set "01H" in memory start address registers MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address Memory start address CS0 area size (64 Kbytes) S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 MAMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.7.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to "FFH". B0CS 91CP27-79 2003-11-05 TMP91CP27 (4) Address area size specification Table 3.7.1 shows the relationship between CS area and area size. "" indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by "", set the start address in the desired steps starting from 000000H. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.7.1 Valid Area Sizes for Each CS Area Size (Byte) CS Area CS0 CS1 CS2 CS3 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M Note: indicates areas that cannot be set by memory start address register and memory address mask register combinations. 91CP27-80 2003-11-05 TMP91CP27 3.7.2 Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. Chip Select/Wait Control Register 7 B0CS (00C0H) Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable 6 5 B0OM1 0 4 B0OM0 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B2BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 1 B0W1 0 0 B0W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B1CS (00C1H) Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1OM1 0 B1OM0 0 B1W2 0 B1W1 0 B1W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B2CS (00C2H) Bit symbol Read/Write After reset Function B2E 1 0: Disable 1: Enable B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area B2OM1 0 B2OM0 0 B2W2 0 B2W1 0 B2W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits B3CS (00C3H) Bit symbol Read/Write After reset Function B3E W 0 0: Disable 1: Enable B3OM1 0 B3OM0 0 B3W2 0 B3W1 0 B3W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits BEXCS (00C7H) Bit symbol Read/Write After reset Function BEXW2 W 0 BEXW1 0 BEXW0 0 Number of Waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: Reserved 101: 3 waits 110: 4 waits 111: 8 waits Master enable bit 0 1 Disable CS area Enable CS area Chip select output waveform selection 00 For ROM/SRAM 01 Don't care 10 Don't care 11 Don't care Number of address area waits (See section 3.7.2, "(3) Wait Control.") Data bus width selection CS2 area selection 0 16-Mbyte area 1 Specified address area 0 1 16-bit data bus 8-bit data bus Note: Read-modify-write instructions are prohibited for registers B0CS, B1CS, B2CS, B3CS and BEXCS. Figure 3.7.5 Chip Select/Wait Control Register 91CP27-81 2003-11-05 TMP91CP27 (1) Master enable bits Bit7 ( 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 32 bits 2n + 0 (Even number) 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 Note: "xxxxx" indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high impedance; also, that the write strobe signal for the bus remains inactive. 91CP27-82 2003-11-05 TMP91CP27 (3) Wait control Bits 0 to 2 ( 000 001 010 011 100 101 110 111 Number of Waits 2 1 (1 + N) 0 Reserved 3 4 8 Inserts a wait of 2 states. Inserts a wait of 1 state. Wait Operation Same operation with 1 wait because of nothing WAIT pin. Ends the bus cycle without a wait. Invalid setting Inserts a wait of 3 states. Inserts a wait of 4 states. Inserts a wait of 8 states. Note: A Reset sets these bits to "000" (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations that are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS 91CP27-83 2003-11-05 TMP91CP27 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: a. b. c. Set the Memory Start Address Registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the Memory Address Mask Registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 areas. The CS0 to CS2 pins can also function as pins P40 to P42. To output a chip select signal using one of these pins, set the corresponding bit in the port 4 function register P4FC and port 4 control register P4CR to "1". If a CS0 to CS3 address is specified which is actually an internal I/O, RAM and ROM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS2 pins. Example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is cleared to 0. MSAR0 = 01H MAMR0 = 07H B0CS = 83H Start address: 010000H Address area: 64 Kbytes ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled 91CP27-84 2003-11-05 TMP91CP27 3.7.3 Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91CP27. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. 74AC573 TMP91CP27 CS0 CS1 CS2 DQ LE CS Address data bus CS Upper byte ROM OE OE Lower byte ROM CS 8-bit RAM OE WE CS 8-bit I/O OE WE DQ LE ALE AD8 : AD15 AD0 : AD7 RD WR Figure 3.7.6 Example of External Memory Connection (ROM uses 16-bit bus, RAM and I/O uses 8-bit bus) A reset clears all bits of the port 4 control register P4CR and the port 4 function register P4FC to "0" and disables output of the CS signal. To output the CS signal, the appropriate bit must be set P4CR to "1" after set P4FC to "1". 91CP27-85 2003-11-05 TMP91CP27 3.8 8-Bit Timers (TMRA) The TMP91CP27 features 6 channels (TMRA0 to TMRA5) built-in 8-bit timers. These timers are paired into 3 modules: TMRA01, TMRA23 and TMRA45. Each module consists of 2 channels and can operate in any of the following 4 operating modes. * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.8.1 to Figure 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by 5 bytes registers (SFRs: Special function registers). Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 3.8.1 Registers and Pins for Each Module Module Specification External pins Input pin for external clock Output pin for timer flip-flop Timer RUN register SFR name (Address) Timer register Timer mode register Timer flop-flop control register TMRA01 TA0IN (Shared with P70) TA1OUT (Shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 None TA3OUT (Shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TMRA45 TA4IN (Shared with P73) TA5OUT (Shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) 91CP27-86 2003-11-05 3.8.1 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA1FF TA01RUN T1 T16 T256 Block Diagram 4 8 16 32 64 128 256 512 Run/clear TA01RUN TA01RUN Timer flip-flop output: TA1OUT External input clock: TA0IN T1 T4 T16 TA01MOD 8-bit up counter (UC1) Figure 3.8.1 Block Diagram of TMRA01 91CP27-87 Match 8-bit comparator detect (CP0) TA0TRG TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG TMRA0 Internal data bus TMRA1 match output: interrupt output: TA0TRG INTTA1 TMP91CP27 2003-11-05 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA3FF TA23RUN T1 T16 T256 4 8 16 32 64 128 256 512 Run/clear TA23RUN Selector TA23RUN Timer flip-flop output: TA3OUT Figure 3.8.2 Block Diagram of TMRA23 TA23MOD 91CP27-88 Match 8-bit comparator detect (CP2) TA2TRG TA23MOD Match 8-bit comparator detect (CP3) 8-bit timer register TA3REG TMRA2 Internal data bus TMRA3 match output: interrupt output: TA2TRG INTTA3 TMP91CP27 2003-11-05 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA5FF TA45RUN T1 T4 T16 4 8 16 32 64 128 256 512 Run/clear TA45RUN Timer flip-flop output: TA5OUT Selector 8-bit up counter (UC4) T1 T16 T256 TA45RUN External input clock:TA4IN Figure 3.8.3 Block Diagram of TMRA45 TA45MOD 91CP27-89 Match 8-bit comparator detect (CP4) TA4TRG TA45MOD Match 8-bit comparator detect (CP5) 8-bit timer register TA5REG TMRA4 Internal data bus TMRA5 match output: interrupt output: TA4TRG INTTA5 TMP91CP27 2003-11-05 TMP91CP27 3.8.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The T0 as the input clock to prescaler is a clock divided by 4, which selected using the prescaler clock selection register SYSCR0 @fc = 16MHz, fs = 32.768kHz System Clock Selection 3 Prescaler Output Clock Resolution T1 fs/2 (244 s) fc/23 (0.5 s) fc/24 (1.0 s) fc/2 (2.0 s) fc/2 (4.0 s) fc/2 (8.0 s) fc/27 (8.0 s) 7 6 5 5 T4 fs/2 (977 s) fc/25 (2.0 s) fc/26 (4.0 s) fc/2 (8.0 s) fc/2 (16 s) fc/2 (32 s) fc/29 (32 s) 9 8 7 7 T16 fs/2 (3.9 ms) fc/27 (8.0 s) fc/28 (16 s) fc/2 (32 s) fc/2 (64 s) 11 10 9 T256 fs/2 (62.5 ms) fc/211 (128 s) fc/212 (256 s) fc/213 (512 s) fc/214 (1024 s) 11 fc/2 (128 s) fc/215 (2048 s) fc/211 (128 s) fc/215 (2048 s) (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4, and T16. The clock setting is specified by the value set in TA01MOD 91CP27-90 2003-11-05 TMP91CP27 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers that can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Up counter Comparator (CP0) Timer registers 0 (TA0REG) Y Shift trigger Register buffers 0 Write Internal data bus Selector B Matching detection in PPG cycle 2n - 1 overflow of PWM Write to TA0REG A S TA01RUN Figure 3.8.4 Configuration of Timer Register 0 (TA0REG) Note: The same memory address is allocated to the timer register and the register buffer when write data to TA0REG. When The address of each timer register is as follows. TA0REG: 000102H TA2REG: 00010AH TA4REG: 000112H TA1REG: 000103H TA3REG: 00010BH TA5REG: 000113H All these registers are write only and cannot be read. 91CP27-91 2003-11-05 TMP91CP27 (4) Comparator (CP0 and CP1) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR 91CP27-92 2003-11-05 TMP91CP27 3.8.3 SFR TMRA01 Run Register 7 TA01RUN (0100H) Bit symbol Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 1 Disable Enable 0 0 6 5 4 3 I2TA01 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA01: Operation in IDLE2 mode TA01PRUN: Run prescaler TA1RUN: Run TMRA1 TA0RUN: Run TMRA0 Note: The values of bits 4, 5 and 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN (0108H) Bit symbol Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable TA2REG double buffer control 0 1 Disable Enable 0 0 6 5 4 3 I2TA23 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA23: Operation in IDLE2 mode TA23PRUN: Run prescaler TA3RUN: Run TMRA3 TA2RUN: Run TMRA2 Note: The values of bits 4, 5 and 6 of TA23RUN are undefined when read. Figure 3.8.5 Register for TMRA 91CP27-93 2003-11-05 TMP91CP27 TMRA45 Run Register 7 TA45RUN (0110H) Bit symbol Read/Write After reset Function TA4RDE R/W 0 Double buffer 0: Disable 1: Enable TA4REG double buffer control 0 1 Disable Enable 0 0 6 5 4 3 I2TA45 2 TA45PRUN 1 TA5RUN 0 R/W 0 TA4RUN 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) Count operate 0 1 Stop and clear Run (Count up) I2TA45: Operation in IDLE2 mode TA45PRUN: Run prescaler TA5RUN: Run TMRA5 TA4RUN: Run TMRA4 Note: The values of bits 4, 5 and 6 of TA45RUN are undefined when read. Figure 3.8.6 Register for TMRA 91CP27-94 2003-11-05 TMP91CP27 TMRA01 Mode Register 7 TA01MOD Bit symbol (0104H) Read/Write After reset Function TA01M1 0 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 26 - 1 10: 27 - 1 11: 28 - 1 4 PWM00 0 R/W 3 TA1CLK1 0 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode Source clock for TMRA1 Source clock for TMRA0 00: TA0TRG 00: TA0IN pin 01: T1 01: T1 10: T16 10: T4 11: T256 11: T16 TMRA0 source clock selection 00 01 10 11 TA0IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA1 source clock selection TA01MOD Comparator output from TMRA0 T1 T16 T256 TA01MOD PWM cycle selection 00 01 10 11 Reserved (26 - 1) x Clock source (27 - 1) x Clock source (28 - 1) x Clock source TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Figure 3.8.7 Register for TMRA 91CP27-95 2003-11-05 TMP91CP27 TMRA23 Mode Register 7 TA23MOD Bit symbol (010CH) Read/Write After reset Function TA23M1 0 6 TA23M0 0 5 PWM21 0 PWM cycle 00: Reserved 01: 26 - 1 10: 27 - 1 11: 28 - 1 4 PWM20 0 R/W 3 TA3CLK1 0 2 TA3CLK0 0 1 TA2CLK1 0 0 TA2CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode Source clock for TMRA3 Source clock for TMRA2 00: Reserved 00: TA2TRG 01: T1 01: T1 10: T4 10: T16 11: T256 11: T16 TMRA2 source clock selection 00 Do not set 01 10 11 T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA3 source clock selection TA23MOD TA23MOD PWM cycle selection 00 Reserved 01 10 11 (26 - 1) x Clock source (27 - 1) x Clock source (28 - 1) x Clock source TMRA23 operation mode selection 00 Two 8-bit timers 01 10 11 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.8.8 Register for TMRA 91CP27-96 2003-11-05 TMP91CP27 TMRA45 Mode Register 7 TA45MOD Bit symbol (0114H) Read/Write After reset Function TA45M1 0 6 TA45M0 0 5 PWM41 0 PWM cycle 00: Reserved 01: 26-1 10: 27-1 11: 28-1 4 PWM40 0 R/W 3 TA5CLK1 0 00: TA4TRG 01: T1 10: T16 11: T256 2 TA5CLK0 0 1 TA4CLK1 0 00: TA4IN pin 01: T1 10: T4 11: T16 0 TA4CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode Source clock for TMRA5 Source clock for TMRA4 TMRA4 source clock selection 00 01 10 11 TA4IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA5 source clock selection TA45MOD TA45MOD PWM cycle selection 00 Reserved 01 10 11 (26 - 1) x Clock source (27 - 1) x Clock source (28 - 1) x Clock source TMRA45 operation mode selection 00 Two 8-bit timers 01 10 11 16-bit timer 8-bit PPG 8-bit PWM (TMRA4) + 8-bit timer (TMRA5) Figure 3.8.9 Register for TMRA 91CP27-97 2003-11-05 TMP91CP27 TMRA1 Flip-Flop Control Register 7 TA1FFCR (0105H) Bit symbol Read/Write After reset Function Readmodify-write instruction is prohibited. 6 5 4 3 TAFF1C1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care R/W 2 TAFF1C0 1 1 TAFF1IE 0 TA1FF control for inversion 0: Disable 1: Enable R/W 0 TAFF1IS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 Inversion by TMRA0 1 Inversion by TMRA1 Inversion of TA1FF 0 Disabled 1 Enabled Control of TA1FF 00 Inverts the value of TA1FF. 01 10 11 Note: The values of bits 4, 5, 6 and 7 of TA1FFCR are undefined when read. Sets TA1FF to "1". Clears TA1FF to "0". Don't care Figure 3.8.10 Register for TMRA 91CP27-98 2003-11-05 TMP91CP27 TMRA3 Flip-Flop Control Register 7 TA3FFCR (010DH) Bit symbol Read/Write After reset Function Readmodify-write instruction is prohibited. 6 5 4 3 TAFF3C1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care R/W 2 TAFF3C0 1 1 TAFF3IE 0 TA3FF control for inversion 0: Disable 1: Enable R/W 0 TAFF3IS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 Inversion by TMRA2 1 Inversion by TMRA3 Inversion of TA3FF 0 Disabled 1 Enabled Control of TA3FF 00 Inverts the value of TA3FF. 01 10 11 Note: The values of bits 4, 5, 6 and 7 of TA3FFCR are undefined when read. Sets TA3FF to "1". Clears TA3FF to "0". Don't care Figure 3.8.11 Register for 8-Bit Timer 91CP27-99 2003-11-05 TMP91CP27 TMRA5 Flip-Flop Control Register 7 TA5FFCR (0115H) Bit symbol Read/Write After Reset Function Readmodify-write instruction is prohibited. 6 5 4 3 TAFF5C1 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don't care R/W 2 TAFF5C0 1 1 TAFF5IE 0 TA5FF control for inversion 0: Disable 1: Enable R/W 0 TAFF5IS 0 TA5FF inversion select 0: TMRA4 1: TMRA5 Inverse signal for timer flip-flop 5 (TA5FF) (Don't care except in 8-bit timer mode) 0 Inversion by TMRA4 1 Inversion by TMRA5 Inversion of TA5FF 0 Disabled 1 Enabled Control of TA5FF 00 Inverts the value of TA5FF. 01 10 11 Note: The values of bits 4, 5, 6 and 7 of TA5FFCR are undefined when read. Sets TA5FF to "1". Clears TA5FF to "0". Don't care Figure 3.8.12 Register for TMRA 91CP27-100 2003-11-05 TMP91CP27 3.8.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and counter data, be stopped operation of TMRA0 and TMRA1 registers beforehand. a. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 20 s at fc = 16 MHz, set each register as follows: * Clock state System clock: High frequency (fc) Clock gear: 1(fc) Prescaler clock: fFPH MSB LSB 76543210 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 -XX- 0XX0 - 0 - 1XX 00 -- 11 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.5 s at fc = 16 MHz) as the input clock. Set TA1REG to 20 s / T1 = 40 = 28H Enable INTTA1 and set it to level 5. Start TMRA1 counting. 00101 X 1 0 1 - - X X X - X: Don't care, -: No change Select the input clock using Table 3.8.2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Comparator output from TMRA0, T1, T16 and T256 91CP27-101 2003-11-05 TMP91CP27 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 3.0 s square wave pulse from the TA1OUT pin at fc = 16 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH MSB LSB 76543210 TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN - X X X- - 0- 00XX01-- 00000 XXXX1 XXX 01 01 1 1 Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.5 s at fc = 16 MHz) as the input clock. Set the timer register to 3.0 s / T1 / 2 = 3 Clear TA1FF to "0" and set it to invert on the match detects signal from TMRA1. Set P71 to function as the TA1OUT pin. Start TMRA1 counting. ---1- 1X 1- XXX-X- -XXX-1 X: Don't care, -: No change T1 TA01RUN 0 1 2 3 0 1 2 3 0 1 2 3 0 TA1OUT 1.5 s @fc = 16 MHz Figure 3.8.13 Square Wave Output Timing Chart (50% Duty) 91CP27-102 2003-11-05 TMP91CP27 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.8.14 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH If T16 (8.0 s at 16 MHz) is used as the input clock for counting, set the following value in the registers: 0.5 s/8.0 s = 62500 = F424H; i.e. set TA1REG to F4H and TA0REG to 24H. 91CP27-103 2003-11-05 TMP91CP27 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1 and UC0) TMRA0 comparator match detect signal 0000H 0080H 0180H 0280H 0380H 0480H Interrupt INTTA1 Timer output TA1OUT Inversion Figure 3.8.15 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (shared with P71). tH tL t TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interruput INTTA1) TA1OUT TA0REG TA1REG Figure 3.8.16 8-Bit PPG Output Waveforms 91CP27-104 2003-11-05 TMP91CP27 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT TA0IN T1 T4 T16 Selector 8-bit up counter (UC0) TA01RUN Inversion INTTA0 Comparator INTTA1 TA01MOD Comparator Selector TA0REG-WR TA0REG Shift trigger Register Buffer TA1REG TA01RUN Figure 3.8.17 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and up counter Match with TA1REG TA0REG (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TA0REG (Register buffer) write (Up counter = Q1) (Up countner = Q2) Figure 3.8.18 Operation of Register Buffer 91CP27-105 2003-11-05 TMP91CP27 Example: To generate 1/4-duty 50-kHz pulses (at fc = 16 MHz): 20 s * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Calculate the value that should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s T1 = 0.5 s (at 16 MHz); 20 s/0.5 s = 40 Therefore set TA1REG to 40 (28H) The duty is to be set to 1/4: t x 1/4 = 20 s x 1/4 = 5 s 5 s/0.5 s = 10 Therefore, set TA0REG = 10 = 0AH. MSB 76 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR P7CR P7FC TA01RUN 0 1 0 0 X X 0 0 0 X X X X LSB 5 X X 0 1 X X X X 4 X X 0 0 X - - X 3 - X 1 1 0 - 2 0 X 0 0 1 - 1 0 0 1 0 1 1 1 1 0 0 1 0 0 X - X 1 Stop TMRA0 and TMRA1 and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write 0AH Write 28H Set TA1FF, enabling inversion. Writing "10" provides negative logic pulse. Set P71 as the TA1OUT pin. Start TMRA0 and TMRA1 counting and enable double buffer. X X 1 X- -1 X: Don't care, -: No change 91CP27-106 2003-11-05 TMP91CP27 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n - 1 counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2n - 1 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) Figure 3.8.19 8-Bit PWM Output Wave Form Figure 3.8.20 shows a block diagram representing this mode. TA01RUN TA0IN T1 T4 T16 TA1OUT TA1FFCR Selector 8-bit up counter (UC 0) Clear 2n - 1 overflow control TA01MOD |