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DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
The ICS9FG104 is a Frequency Timing Generator that provides 4 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-tooutput skew of less than 35 ps. The ICS9FG104 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control.
ICS9FG104
Features/Benefits
* * * * * * * Generates common frequencies from 14.318 MHz or 25 MHz Crystal or reference input 4 - 0.7V current-mode differential output pairs Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread Unused inputs may be disabled in either driven or Hi-Z state for power management. M/N Programming
Key Specifications
* * * * * * Output cycle-to-cycle jitter < 50 ps Output to output skew < 35 ps +/-300 ppm frequency accuracy on output clocks +/- 150 ppm frequency accuracy @ 100 MHz outputs 28-pin SSOP/TSSOP package Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN OSC X2 2
R EF OU T
PROGRAMMABLE SPREAD PLL
STOP LOGIC
4 DIF(3:0)
SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC
IREF
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
XIN/CLKIN X2 VDD GND REFOUT **FS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF **FS0 **FS1 DIF_0 DIF_0# VDD GND DIF_1 DIF_1# *SEL14M_25M# **SPREAD DIF_STOP#
Functionality Table
SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.00 0 1 1 0 333.00 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.00 1 1 1 0 333.00 1 1 1 1 400.00
* Pin has internal 120K pull up ** Pin has internal 120K pull down
28-pin SSOP/TSSOP
Power Groups
Pin Number VDD GND 3 4 9,21 10,20 28 27 Description REFOUT, Digital Inputs DIF Outputs IREF, Analog VDD, GND for PLL Core
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME XIN/CLKIN X2 VDD GND REFOUT FS2** DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK DIF_STOP# SPREAD** SEL14M_25M#* DIF_1# DIF_1 GND VDD DIF_0# DIF_0 FS1** FS0** IREF GNDA VDDA PIN TYPE IN OUT PWR PWR OUT IN OUT OUT PWR PWR OUT OUT I/O IN IN IN IN OUT OUT PWR PWR OUT OUT IN IN OUT PWR PWR DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output Frequency select pin. 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Active low input to stop differential output clocks. Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable spread spectrum functionality. Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output 3.3V Frequency select latched input pin. 3.3V Frequency select latched input pin. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG104 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address DC(H ) W Rite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
Index Block Read Operation
Controlle r (Host) T starT bit Slave Address DC(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 6 24 25 16 Name FS31 FS21 FS11 FS01 Spread Enable1 Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) DIF_STOP# drive mode SPREAD TYPE Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD Pin 17 Pin 6 Pin 24 Pin 25 Pin 16 0 0 0
See Frequency Selection Table, Page 1 Off On
Hardware Select Software Select Driven Down Hi-Z Center
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 EN DIF_0 EN DIF_3 EN DIF_2 EN Name Control Function Reserved Output Enable Output Enable Reserved Reserved Output Enable Output Enable Reserved RW RW Disable Disable Enable Enable RW RW Disable Disable Enable Enable Type 0 1 PWD 1 1 1 1 1 1 1 1
SMBus Table: Output Stop Control Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 STOP EN DIF_0 STOP EN DIF_3 STOP EN DIF_2 STOP EN Name Control Function Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved RW RW Free-run Free-run Stop-able Stop-able RW RW Free-run Free-run Stop-able Stop-able Type 0 1 PWD 0 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Frequency Select Readback Register
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 6 44 45 16 Name SEL14M_25M# (FS3) FS21 FS11 FS01 SPREAD1
1
Control Function State of pin 17 State of pin 6 State of pin 24 State of pin 25 State of pin 26 Reserved Reserved Reserved
Type R R R R R
0
1
PWD Pin 17
See Frequency Selection Table, Page 1
Pin 6 Pin 24 Pin 25
Off
On
Pin 16 0 0 0
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 VENDOR ID REVISION ID Control Function Type R R R R R R R R 0 1 PWD X X X X 0 0 0 1
SMBus Table: DEVICE ID
Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 Device ID = 08 hex Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 0 0 0
SMBus Table: Byte Count Register
Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Control Function Type RW RW RW RW RW RW RW RW 0 1 ICS9FG104
PWD 0 0 0 0 0 1 1 1
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IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Reserved Register
Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0
SMBus Table: Reserved Register
Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0
SMBus Table: M/N Programming Enable
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 5 REFOUT_En Name M/N_Enable Control Function M/N Prog. Enable Reserved REFOUT Enable Reserved Reserved Reserved Reserved Reserved RW Disable Enable Type RW 0 Disable 1 Enable PWD 0 1 1 0 0 0 0 0
SMBus Table: PLL Frequency Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div8 PLL N Div9 PLL M Div5 PLL M Div4 PLL M Div3 PLL M Div2 PLL M Div1 PLL M Div0 M Divider Programming bit (5:0) Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register
Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div7 PLL N Div6 PLL N Div5 PLL N Div4 PLL N Div3 PLL N Div2 PLL N Div1 PLL N Div0 N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Control Function Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X
SMBus Table: PLL Spread Spectrum Control Register
Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL SSP7 PLL SSP6 PLL SSP5 PLL SSP4 PLL SSP3 PLL SSP2 PLL SSP1 PLL SSP0 Spread Spectrum Programming bit(7:0) Control Function Type RW RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL 0 1 PWD X X X X X X X X
SMBus Table: PLL Spread Spectrum Control Register
Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PLL SSP14 PLL SSP13 PLL SSP12 PLL SSP11 PLL SSP10 PLL SSP9 PLL SSP8 Spread Spectrum Programming bit(14:8) Name Control Function Reserved RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL Type 0 1 PWD 0 X X X X X X X
SMBus Table: Reserved Test Register
Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Reserved Test Register. Do not write to this register, erratic device operation may occur. Name Control Function Type 0 1 PWD 1 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# DIF DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV.
DIF_Stop# DIF DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 CONDITIONS MIN TYP MAX
VDD + 0.3
UNITS NOTES V V uA uA uA 1 1 1 1 1 1 1 1 1 3 1 1 1 1,2 1 1 1
3.3 V +/-5% 2 VSS - 0.3 3.3 V +/-5% VIN = VDD -5 V IN = 0 V; Inputs with no pull-5 up resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz All outputs stopped driven All outputs stopped Hi-Z VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD -200 125 110 106 48 14 1.5
0.8 5
150 125 120 60 25 7 5 6 1.8
mA mA mA mA MHz nH pF pF ms kHz ns ns
I DD3.3OP Operating Supply Current IDD3.3STOP Input Frequency3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Input Rise and Fall times
1 2
Fi Lpin CIN COUT TSTAB f MOD tDIFOE tR/tF
30
33 15 5
Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104 REV K 04/12/07
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Crossing variation over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX 850
UNITS mV
NOTES 1 1 1
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps ps ps
1 1 1 1 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 4 4 4 1
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, output to output Jitter, PCI-e SRC phase Jitter, PCI-e SRC phase Jitter, Cycle to cycle
1 2
tr tf d-tr d-tf dt3 tsk3 tjPCI-ephase14 tjPCI-ephase25 tjcyc-cyc
-300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533
Measured Differentially VT = 50% 22MHz/1.5MHz/1.5MHz/10ns, 14.31818 MHz REF Clock 22MHz/1.5MHz/1.5MHz/10ns, 25 MHz REF Clock Measured Differentially
45
700 700 125 125 55 35 42 39 50
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
3 4
Figures are for down spread. This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 +/- 150 ppm for 100 MHz outputs
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 14.318MHz output nominal Clock period Tperiod 25.000MHz output nominal Output High Voltage VOH I OH = -1 mA I OL = 1 mA Output Low Voltage VOL VOH @MIN = 1.0 V, Output High Current I OH V OH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current I OL VOL @MAX = 0.4 V Rise Time t r1 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Fall Time t f1 Duty Cycle Jitter
1 2
MIN TYP MAX UNITS -300 0 300 ppm 69.8270 69.8413 69.8550 ns 39.9880 40.0000 40.0120 ns 2.4 V 0.4 V -29 29 1 1 45 1.6 1.6 52.5 150 -23 27 2 2 55 200 mA mA ns ns % ps
Notes 1 1 1 1 1 1 1 1 1,2 1,2 1
dt1 t jcyc-cyc
VT = 1.5 V VT = 1.5 V
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
Electrical Characteristics - Phase Jitter (Applies to: Revision D Devices, Revision ID = 3)
PARAMETER SYMBOL CONDITIONS
PCIe Gen 1 specs (1.5 - 22 MHz) FBD specs (11-33 MHz) PCIe Gen 2 specs (5-16 MHz, 8-16 MHz)
MIN
TYP
40
MAX
108 3
UNITS Notes
ps ps rms ps rms 1,2 1 1
Jitter, Phase
tjphasePLL
2.23
3.1
Notes on Phase Jitter:
1
Applicable to all DIF outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. Specification applies to revision C devices and later.
2
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
Figure 1 1 1 1 1 Figure 1 1 Figure 2 2
Figure 1 Down device routing.
L1 Rs L1' Rs HSCL Output Buffer
L2 L2 Rt L3' Rt L3
L4 L4'
PCI Ex Board Down Device REF_CLK Input
Figure 1
Figure 2 PCI Express Connector Routing.
L1 L1'
Rs
L2 L2'
L4 L4' Rt L3' Rt L3 PCI Ex Add In Board REF_CLK Input
Rs HSCL Output Buffer
Figure 2
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note
ICS874003i-02 input compatible Standard LVDS
L1 L1'
R1a
L2 L2'
R3
L4 L4'
R4
R1b HSCL Output Buffer
R2a L3'
R2b L3 Down Device REF_CLK Input
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note
3.3 Volts
R5a L4 L4'
Cc Cc
R5b
R6a
R6b PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
N
c
209 mil SSOP SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1 A2 b c D E E1 e L N VARIATIONS N
In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
A A1
28
Reference Doc.: JEDEC Publication 95, MO-150
-Ce
b SEATING PLANE .10 (.004) C
10-0033
Ordering Information
ICS9FG104yFLFT
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104 REV K 04/12/07
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4.40 mm. Body, 0.65 mm. Pitch TSSOP
N
c
(173 mil) SYMBOL
L
(25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
E1 INDEX AREA
E
12
D
A A1 A2 b c D E E1 e L N aaa VARIATIONS
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
A2 A1
A
N 28
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
- Ce
b SEA TING PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
aaa C
Ordering Information
ICS9FG104yGLFT
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G= TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104 REV K 04/12/07
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ICS9FG104 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Revision History
Rev. D E F G H I J K Issue Date Description 1. Updated SMBus Byte 3 bit 7, 5, 4 and 3. 6/2/2005 2. Updated LF Ordering Information to RoHS Compliant. 1/13/2006 Corrected Pin-Type for Pins 5 and 7. 4/13/2006 Addded +/- 150 ppm accuracy spec for 100 MHz outputs. 6/5/2006 Updated SSOP Comon Dimensions Table. 12/12/2006 Updated pinout to reflect internal pull up and pull down resistors. 1/2/2007 Fixed Typos on Pin Description. 4/2/2007 Added Phase Jitter Table. 4/12/2007 Added TSSOP Ordering Information. Page # 9, 13-14 2 1, 5 13 1 2 12 16
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
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