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| DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32869A Description The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs. The IDT74SSTUBF32869A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. IDT74SSTUBF32869A must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that there are no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS and CSR input is low, the Qn, PPO and PTYERR outputs will function normally. The RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR high. The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1. When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO and PTYERR signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR signals of the first register are left floating. The PPO outputs of the first register are cascaded to the PARIN signas on the second register (back). The PPO and PTYERR signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in the diagram below. If an error occurs, and the PTYERR is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations. All registers used on an individual DIMM must be of the same configuration, i.e single or dual die. Features * 14-bit 1:2 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * 50% more dynamic driver strength than standard SSTU32864 * Supports LVCMOS switching levels on C1 and RESET inputs * Low voltage operation: VDD = 1.7V to 1.9V * Available in 150 BGA package Applications * DDR2 Memory Modules * Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A * Ideal for DDR2 667 and 800 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity Implementation and Device Wiring PARIN, W4 PARIN Register 1 (Front) NC, A8 NC, A4 NC, A8 PPO, W8 PPO, W4 Register 2 (Back) NC, A11 PTYERR, W1 Set C=0 for Register 1, and C=1 for Register 2 Block Diagram (CS Active) VREF 2 PARIN D Q 2 2 2 PARITY GENERATOR AND CHECKER 2 PTYERR PPO R Q1A D1 D Q Q1B R 11 Q14A(1) D14 (1) D Q Q14B (1) R QCSA DCS0 D Q QCSB CSR R QCKEA DCKE D Q QCKEB R QODTA DODT D Q QODTB R RESET CLK CLK NOTE: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Block Diagram RESET CLK CLK D2 - D3, D5 - D6, D8 - D14 VREF LPS0 (Internal Node) D CE CLK 11 D CE CE CLK R CE 11 D2 - D3, D5 - D6, D8 - D14 11 Q2 A- Q3A, Q5A - Q6A, Q8A - Q14A Q2B - Q3B, Q5B - Q6B, Q8B - Q14B R 11 11 D2 - D3, D5 - D6, D8 - D25 Parity Check 0 D CLK R 2 1 D CLK R CE 2 PPO PARIN 2 PTYERR C1, C2 CLK 2-Bit Counter R 0 D 1 CLK R NOTE: 1.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 3 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configuration 1 A NB 2 VDD 3 MCL (1) 4 NC 5 GND 6 VREF 7 GND 8 NC 9 MCL (1) 10 VDD 11 NC B VDD NB VDD GND GND GND GND GND VDD NB VDD C QCKEA VDD NB GND NB GND NB GND NB VDD QCKEB D Q2A VDD GND NB DCKE NB D2 NB GND VDD Q2B E Q3A VDD NB D3 NB NC NB DODT NB C1 Q3B F QODTA VDD GND NB NC NB NC NB GND VDD QODTB G Q5A VDD GND D5 NB CLK NB D6 GND VDD Q5B H Q6A NB GND NB NC NB NC NB GND NB Q6B J K QCSA VDD NB NC NB RESET NB CSR NB VDD QCSB VDD VDD GND GND NB NB NB GND VDD VDD VDD L Q8A VDD NB DCS NB CLK NB D8 NB VDD Q8B M N Q9A NB GND NB NC NB NC NB GND NB Q9B Q10A VDD GND D9 NB NC NB D10 GND VDD Q10B P Q11A VDD GND NB NC NB NC NB GND VDD Q11B R Q12A C1 NB D11 NB NC NB D12 NB VDD Q12B T Q13A VDD GND NB D13 NB D14 NB GND VDD Q13B U V Q14A VDD NB GND NB GND NB GND NB VDD Q14B VDD NB VDD GND GND GND GND GND VDD NB VDD W PTYERR VDD MCL (1) PARIN GND VREF GND PPO MCL (1) VDD NB 150-Ball BGA TOP VIEW NOTE: 1.NC denotes a no-connect (ball present but not connected to the die). NB indicates no ball is populated at that gridpoint. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 4 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE 150 Ball CTBGA Package Attributes Top Marking 11 10 9 8 7 6 5 4 3 2 1 A 1 A B C D E F G H 2 3 4 5 6 7 8 9 10 11 B C D E F G H J J K K L L M M N P R T U V W N P R T U V W TOP VIEW BOTTOM VIEW SIDE VIEW 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 5 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 RESET H H H H H H H H H H H H L 1 Outputs CLK L or H L or H L or H L or H DCS L L L L L L H H H H H H X or Floating CSR L L L H H H L L L H H H CLK L or H L or H L or H L or H Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 L 2 2 2 QCS L L Q0 L L Q0 H H Q0 H H Q02 L 2 2 2 QODT, QCKE L H Q 02 L H Q 02 L H Q 02 L H Q 02 L Q02 2 Q02 X or X or X or Floating Floating Floating 2 H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW Output Level before the indicated steady-state conditions were established. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 6 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Terminal Functions Signal Group Ungated Inputs Chip Select Gated Inputs Chip Select Inputs Terminal Name DCKE, DODT D1...D141 DCS, CSR Q1A...Q14A1, Q1B...Q14B1, QCSnA, B QCKEnA, B QODTnA, B PARIN PPO Type SSTL_18 SSTL_18 SSTL_18 Description DRAM function pins not associated with Chip Select DRAM inputs, re-driven only when Chip Select is LOW DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock Input parity is received on pin PARIN, and should maintain odd parity across the D1:D14 inputs, at the rising edge of the clock, one cycle after Chip Select is LOW. Partial Parity Output. Indicates parity out of D1-D14. When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by in total two clock cycles for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). When LOW, the register is configured as Register 1. When HIGH, the register is configured as Register 2. Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased Inputsreliability. Power Supply Voltage Ground Re-Driven Outputs SSTL_18 Parity Input Parity Output SSTL_18 SSTL_18 Parity Error Output PTYERR Open Drain Configuration Inputs Clock Inputs C1 CLK, CLK SSTL_18 SSTL_18 SSTL_18 Input 0.9V nominal Power Input Ground Input RESET Miscellaneous Inputs VREF VDD GND 1 This range does not include D1, D4, and D7, and their corresponding outputs. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 7 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 RESET H H H H H H H H H H L 1 Outputs of Inputs = H (D1 - D14)2 Even Odd Even Odd Even Odd Even Odd X X X or Floating DCS L L L L L L L L H X X or Floating CSR X X X X L L L L H X X or Floating CLK L or H X or Floating CLK L or H X or Floating PARIN3 L L H H L L H H X X X or Floating PPO L H H L L H H L PPOn0 PPOn0 L PTYERR4 H L L H H L L H PTYERRn0 PTYERRn0 H H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2 This range does not include D1, D4, and D7. 3 PARIN arrives one clock cycle (C1 = 0), or two clock cycles (C1 = 1), after the data to which it applies. 4 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 8 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Supply Voltage, VDD Input Voltage Range, VI Output Voltage Range, 1 Rating -0.5V to 2.5V -0.5V to VDD + 2.5V -0.5V to VDDQ + 0.5V 50mA 50mA 50mA 100mA 40C/W 29C/W -65 to +150C 0m/s Airflow 1m/s Airflow VO1,2 Input Clamp Current, IIK Output Clamp Current, IOK Continuous Output Clamp Current, IO Continuous Current through each VDD or GND Package Thermal Impedance (ja)3 Storage Temperature 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. Mode Select C1 0 1 Device Mode First device in pair, Front Second device in pair, Back Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V 0.1V Parameter dV/dt_r dV/dt_f dV/dt_1 1 Min. 1 1 Max. 4 4 1 Units V/ns V/ns V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Operating Characteristics, TA = 25C The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL IERROL TA Parameter I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage Dn, PARIN, AC Low-Level Input Voltage DCS, CSR, DCKEn, DC High-Level Input Voltage DODTn DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Range Differential Input Voltage High-Level Output Current Low-Level Output Current PTYERR Low-Level Output Current Operating Free-Air Temperature RESET, C1 CLK, CLK Min. 1.7 0.49 * VDD VREF - 0.04 0 VREF + 0.25 Typ. 1.8 0.5 * VDD VREF Max. 1.9 0.51 * VDD VREF + 0.04 VDD VREF - 0.25 Units V V V V VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ 0.675 600 -12 12 25 0 +70 1.125 V V V mV mA mA C 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 10 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDDQ/VDD = 1.8V 0.1V. Symbol Parameter VIK VOH VOL VERROL IIL PTYERR Output Low Voltage All Inputs Static Standby II = -18mA VDDQ = 1.7V, IOH = -100A VDDQ = 1.7V, IOH = -12mA VDDQ = 1.7V, IOL = 100A VDDQ = 1.7V, IOL = 12mA IERROL = 25mA; VDD = 1.7V VI = VDD or GND IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 250mV VICR = 0.9V, VIPP = 600mV VI = VDD or GND 2 3.5 4.5 120 A/Clock MHz A/Clock MHz/ Data 3 4.5 pF -5 200 10 mA VDDQ-0.2 1.2 0.2 0.5 0.5 +5 Test Conditions Min. Typ. Max. -1.2 Units V V V V A A IDD Static Operating Dynamic Operating (clock only) IDDD Dynamic Operating (per each data input) Dn, PARIN, DSCn inputs CIN CLK and CLK inputs RESET 247 52 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 11 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V 0.1V Symbol fCLOCK tW tACT 1 2 Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS before CLK, CLK, CSR HIGH; CSR before CLK, CLK, DCS HIGH Min. 1 Max. 410 10 15 Units MHz ns ns ns tINACT 0.6 0.5 0.5 0.5 0.4 0.4 ns ns tSU Setup Time DCS before CLK, CLK, CSR LOW DODT, DOCKE, and data before CLK, CLK PAR_IN before CLK, CLK DCS, DODT, DCKE, and data after CLK, CLK PAR_IN after CLK, CLK tH Hold Time 1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V 0.1V Symbol fMAX tPDM tPD 1 2 1 Parameter Max Input Clock Frequency Propagation Delay, single-bit switching, CLK / CLK to Qn Propagation Delay, single-bit switching, CLK / CLK to Qn Propagation Delay, simultaneous switching, CLK / CLK to Qn LOW to HIGH Propagation Delay, CLK / CLK to PTYERR HIGH to LOW Propagation Delay, CLK / CLK to PTYERR Propagation Delay from CLK / CLK to PPO HIGH to LOW Propagation Delay, RESET to Qn LOW to HIGH Propagation Delay, RESET to PTYERR Min. 340 1.1 0.4 1.2 0.5 Max. 1.5 0.8 1.6 3 3 1.6 3 3 Units MHz ns ns ns ns ns ns ns ns tPDMSS tLH tHL tPD tPHL tPLH 1 2 Design target as per JEDEC specifications. Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.) 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 12 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V 0.1V Parameter dV/dt_r dV/dt_f dV/dt_ 1 1 Min. 1 1 Max. 4 4 1 Units V/ns V/ns V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 13 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 (1) tPD CLK to Q Q1 - Q14 PARIN (2) (1) tSU tH tPD CLK to PPO PPO (2) tPD CLK to PTYERR tPD CLK to PTYERR PTYERR (2) NOTES: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 2.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 14 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 (1) tPD CLK to Q Q1 - Q14 PARIN (2) (2) (1) tSU tH PPO (not used) (2) tPD CLK to PPO PTYERR tPD CLK to PTYERR tPD CLK to PTYERR NOTES: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 2.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 15 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD/2 RL = 1K DUT TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point Out CL = 30 pF TL = 350ps, 50 ZO = 50 Test Point Test Point DUT CLK Test Point Out CLK RL = 50 ZO = 50 Test Point RL = 1K CLK Inputs ZO = 50 Production-Test Load Circuit Simulation Load Circuit CLK CLK VICR tPLH Output VTT VICR tPHL VOH VTT VOL VID LVCMOS RESET Input tINACT IDD VDD VDD/2 VDD/2 0V tACT 90% 10% LVCMOS RESET Input Voltage Waveforms - Propagation Delay Times VIH VDD/2 VIL tRPHL VOH Voltage and Current Waveforms Inputs Active and Inactive Times Output VTT VOL tW Input VICR VICR VID Voltage Waveforms - Propagation Delay Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID Voltage Waveforms - Setup and Hold Times 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 16 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD DUT Out RL = 50 Test Point DUT Out RL = 1K Test Point CL = 10 pF CL = 10 pF Load Circuit: High-to-Low Slew-Rate Adjustment Load Circuit: Error Output Measurements Output 80% VOH LVCMOS RESET Input tPLH VCC VCC/2 0V 20% dv_f dt_f VOL VOH Output Waveform 2 0.15V 0V Voltage Waveforms: High-to-Low Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) DUT Out CL = 10 pF Test Point RL = 50 Timing Inputs VICR tHL VICR VI(PP) Output Waveform 1 VCC VCC/2 VOL Load Circuit: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) dt_r dv_r 80% VOH Timing Inputs VICR tHL VICR VI(PP) VOH 20% Output VOL Output Waveform 2 0.15V 0V Voltage Waveforms: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 17 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) DUT OUT CL = 5pF (1) Testpoint RL = 1K Partial Parity Out Load Circuit CLK VICR CLK tPLH tPHL VICR VI(PP) VTT Output VTT Partial Parity Out Voltage Waveform, Propagation Delay Time with Respect to CLK Input VTT = VTT/2 VICR Cross Point Voltage VI(PP) = 600mV tPLH and tPHL are the same as tPD. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 18 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Application Information The typical values below are measured on standard JEDEC raw cards, using the JEDEC DDR2 register validation board running patterns 0x43, 0x4F, and 0x5A. Raw Card Values Raw Card1 W tPDMSS 1.48 Overshoot 446 Undershoot 444 1 All values are valid under nominal conditions and minimum/maximum of typical signals on one typical DIMM. Measurements include all jitter and ISI effects. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 19 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 TOP VIEW BOTTOM VIEW 0.08 M C 0.15 M C A B d = 0.35 ~ 0.48(150X) A1 CORNER 1 A 0.25 REF B C D E F G H J K L M N P R T U V W h = 0.25 ~ 0.37 1.20 MAX 0.12 C 0.65 E T A B E1 6.50 8.00 0.05 D C SEATING PLANE A1 CORNER 2 3 4 5 6 7 8 9 10 11 b 0.03 REF B // 0.20 C 0.65 11 10 9 8 7 6 5 4 3 2 1 A C D E F G H 13.00 0.05 J D1 11.70 K L M N P R T U V W 0.15(4X) ALL DIMENSIONS IN MILLIMETERS D 13.00 Bsc E 8.00 Bsc T Min/Max 0.90/1.20 e 0.65 Bsc BALL GRID Horiz Vert Total 11 19 150 d Min/Max 0.35/0.48 h Min/Max 0.25/0.37 D1 11.70 Bsc c E1 6.50 Bsc REF. DIMS b c 0.65 0.75 NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 20 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Ordering Information IDT74SSTUBF XX Family XX XXX Device Type Package X Shipping Carrier T Tape and Reel BKG Low Profile, Fine Pitch, Ball Grid Array 869A 14-Bit Configurable Registered Buffer for DDR2 32 Double Density 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 21 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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