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PD - 97096
IP2002PBF
Synchronous Buck Multiphase Optimized BGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives

Output current 30A continuous with no derating up to TPCB = 90C and TCASE = 90C Operating frequency up to 1MHz Dual sided heatsink capable Very small 11mm x 11mm x 2.6mm profile iP2001PbF footprint compatible Internal features minimize layout sensitivity * Optimized for very low power losses
IP2002PBF Power Block
Description The IP2002PBF is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.6mm BGA power block. The only additional components required for a complete multiphase converter are a PWM IC, the external inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection.
IP2002PBF Internal Block Diagram
VIN PRDY ENABLE PWM VDD SGND MOSFET Driver with dead time control
VSW
PGND
* All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that at least four 10uF ceramic input decoupling capacitors are provided to the VIN pin of each power block. No additional
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5/16/06
1
IP2002PBF All specifications @ 25C (unless otherwise specified)
Absolute Maximum Ratings : Parameter VIN to PGND VDD to SGND PWM to SGND Enable to SGND Output RMS Current Block Temperature Recommended Operating Conditions : Parameter Supply Voltage Input Voltage Range Output Voltage Range Output Current Range Operating Frequency Operating Duty Cycle Symbol VDD VIN VOUT IOUT fsw D Min 4.6 3.0 0.8 150 Typ 5.0 Max 5.5 13.2 3.3 30 1000 85 Units V V V A kHz %
see Figs. 2 & 3 see Figs. 2, 4 & 8 see Fig. 2 see Figs. 2 & 5
Min -0.3 -0.3 -40
Typ -
Max 16 6.0 VDD+0.3 VDD+0.3 30 125
Units V V V V A C
Conditions
not to exceed 6.0V not to exceed 6.0V
Conditions
Electrical Specifications @ VDD = 5V (unless otherwise specified) : Parameter Block Power Loss Turn On Delay Turn Off Delay VIN Quiescent Current VDD Quiescent Current Under-Voltage Lockout Start Threshold Hysteresis Enable Input Voltage High Input Voltage Low Power Ready Logic Level High Logic Level Low PWM Input Logic Level High Logic Level Low
Fig. 8).
Symbol P BLK td(on) td(off) IQ-VIN IQ-VDD UVLO VSTART VHys-UVLO Enable VIH VIL PRDY VOH VOL PWM VOH VOL
Min 4.2 2.0 4.5 2.0 -
Typ 7.2 63 26 4.4 .05 4.6 0.1 -
Max 8.9 1.0 10 4.5 0.8 0.2 0.8
Units W ns mA A V
Conditions
VIN = 12V, VOUT = 1.3V, IOUT = 30A, fSW = 1MHz
Enable = 0V, VIN = 12V Enable = 0V, VDD = 5V
V
V
VDD = 4.6V, ILoad = 10mA VDD < UVLO Threshold, ILoad = 1mA
V
Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9). 2 www.irf.com
IP2002PBF
Pin Description Table
Pin Name VDD VIN
PGND
VSW
SGND
Ball Designator A1 - A3, B1 - B3 A5 - A12, B5 - B12, C5 - C10 C11, C12, D11, D12, E11, E12, F6, F7, F12, G6, G7, G12, H6, H7, H12, J6, J7, J12, K5 - K7, K12, L5, L6, L12, M5 - M7, M12 D5 - D10, E5 - E10, F8 - F11, G8 - G11, H8 - H11, J8 - J11, K8 - K11, L8 - L11, M8 - M11 C1 - C3, D1 -D3, E1 -E3
Pin Function
Supply voltage for the internal circuitry. Input voltage for the DC-DC converter.
Power Ground - connection to the ground of bulk and filter capacitors.
Switching Node - connection to the output inductor.
ENABLE
F1
Signal Ground. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current is less than 10A. Power Ready - This pin indicates the status of ENABLE or VDD. This output will be driven low when ENABLE is logic low or when VDD is less than 4.4V (typ.). When ENABLE is logic high and VDD is greater than 4.4V (typ.), this output is driven high. This output has a 10mA source and 1mA sink capability.
PRDY
K1
PWM NC
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TTL-level input signal to MOSFET drivers. H1 B4, C4, D4, E4, F2 - F4, G2 - This pin is not for electrical connection. It G4, H2 - H4, J1, J2 - J4, K3, should be attached only to dead copper. L1, L2, M1 - M4
3
IP2002PBF
11 10 9 8 7
VIN = 12V VOUT = 1.3V fSW = 1MHz TBLK = 125C L = 0.30uH
Maximum
Power Loss (W)
Typical
6 5 4 3 2 1 0 0 5 10 15 20 25 30
Output Current (A)
Fig. 1: Power Loss vs. Current
Case Temperature (8A
0 10 20 30 40 50 60 70 80 90 100 110 120
32 30 28 26 24 22
Output Current (A)
20 18 16 14 12 10 8 6 4 2 0 0 10 20 30
Safe Operating Area
TX
VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH
40 50 60 70 80 90 100 110 120
PCB Temperature (C)
Fig. 2: Safe Operating Area (SOA) vs. TPCB & TCASE 4 www.irf.com
IP2002PBF
Typical Performance Curves
1.30 1.27 1.24 1.21 1.18 1.15 1.12 1.09 1.06 1.03 1.00 0.97 3 4 5 6 7 8 9 10 11 12 13 10.0
1.33 1.30 1.27
10.0
Power Loss (Normalized)
Power Loss (Normalized)
VOUT = 1.3V IOUT = 30A fSW = 1MHz L = 0.30uH TBLK = 125C
9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0
1.23 1.20 1.17 1.13 1.10 1.07 1.03 1.00 0.97 0.93 0.90 0.8
VIN = 12V IOUT = 30A fSW = 1MHz L = 0.30uH T BLK = 125C
9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0
SOA Temp Adjustment (C)
SOA Temp Adjustment (C)
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Input Voltage (V)
Output Voltage (V)
Fig. 3: Normalized Power Loss vs. VIN
1.00 0.0
Fig. 4: Normalized Power Loss vs. VOUT
1.09 3.5
0.97
Power Loss (Normalized)
Power Loss (Normalized)
0.95
0.92
0.89
VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.30uH TBLK = 125C
-1.0
1.08
-2.0
1.07
-3.0
1.05
-4.0
VIN = 12V VOUT = 1.3V IOUT = 30A fSW = 1MHz TBLK = 125C
3.0
SOA Temp Adjustment (C)
SOA Temp Adjustment (C)
2.5
2.0
1.04
1.5
0.86
-5.0
1.03
1.0
0.84
-6.0
1.01
0.5
0.81
-7.0
0.78
-8.0
1.00
0.0
0.75
-9.0
0.99
-0.5
0.73 250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
-10.0 1000
0.97 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-1.0
Switching Frequency (kHz)
Output Inductance (uH)
Fig. 5: Normalized Power Loss vs. Frequency
Fig. 6: Normalized Power Loss vs. Inductance
70
60
Average IDD (mA)
50
40
30
20
Does not include PRDY current TBLK = 25C
300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
10 250
Switching Frequency (kHz)
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Fig. 7: IDD vs. Frequency
5
IP2002PBF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn Case Temperature (8A out through the printed circuit board and the top of the case.
0 10 20 30 40 50 60 70 80 90 100 110 120
Procedure
Output Current (A)
32 30 28 26
3
1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current.
24 22 20 18 16 14 12 10 8 6 4 2 0 0 10 20 30
Safe Operating Area
VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH
40 50 60 70 80 90
1 2
TX
100
110
120
PCB Temperature (C)
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 2, determine your maximum PCB Temp & Case Temp at the maximum operating current of each IP2002PBF. Then, add the correction temperature from the normalized curves in Figs. 3, 4, 5 or 6 to the TX axis intercept (see procedure no. 2 above) in Fig. 2. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 2. See example no. 2. Operating Conditions for the following examples: Output Current = 30A Sw Freq= 900kHz Input Voltage = 10V Inductor = 0.2uH Output Voltage = 3.3V
Example 1) Adjusting for Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) (Fig. 5) (Fig. 6) Maximum power loss = 11W Normalized power loss for input voltage 0.98 Normalized power loss for output voltage 1.28 Normalized power loss for frequency 0.955 Normalized power loss for inductor value 1.02 Adjusted Power Loss = 11W x 0.98 x 1.28 x 0.955 x 1.02 13.44W
6
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IP2002PBF
Example 2) Adjusting for SOA Temperature: (Fig. (Fig. (Fig. (Fig. 3) 4) 5) 6) Normalized Normalized Normalized Normalized SOA Temperature for input voltage -0.8C SOA Temperature for output voltage 8.4C SOA Temperature for frequency -1.8C SOA Temperature for inductor value 0.75C
TX axis intercept temp adjustment = - 0.8C + 8.4C - 1.8C + 0.75C 6.6C Assuming TCASE = 100C & TPCB = 90C: The following example shows how the SOA current is adjusted for a TX increase of 6.6C.
Case Temperature (8A
0 10 20 30 40 50 60 70 80 90 100 110 120
32 30 28 26 24 22
Unadjusted SOA Current Adjusted SOA Current
Output Current (A)
20 18 16 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120
VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH
Safe Operating Area
PCB Temperature (C)
TX
90%
PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT
PRDY Average VDD Current A V
DC
Average Input Current A
DC
V
Average Input Voltage
PWM
10%
VIN
ENABLE PWM VDD SGND VSW
Average Output Current A
90%
Average VDD Voltage
PGND
iP2001 IP2002PBF
Averaging Circuit V
Average Output Voltage
Average Output Voltage (V OUT)
VSW
10%
td(on)
td(off)
Fig. 8: Power Loss Test Circuit www.irf.com
Fig. 9: Timing Diagram 7
5
4
3
FB
COMP
DROOP
8
+5V
VINS
R6
R1
VOUTS
R35 TP13
Vin VIN1 SGND1
VIN
200
3.92K
IP2002-1 IP2002PBF-1
VDD1
0
R2
6800pF
C26 C1 C3
PWM1
10uF 10uF 10uF 10uF 330uF 330uF 330uF
C25 C4 C5 TP19
PGND
TP18 C33 C39 C40 C41
3.92k
1800pF
8.2pF
4.42k 10k
R3 R19 TP17 R21
10k
R36
+5V
PGNDS
open
+5V ENABLE1
2.49k VSW1
R5
ENABLE1 VSW1
TP6
IP2002PBF
VCC
1
C2
VSW1
0.3uH 10uF open
R22 C15
100uF 100uF open
L1
VOUT
TP10
VOUT
ISEN1 PGND1 PRDY1 PWM1
0
14
C16
C42
TP11
VOUT
TP12
VOUT
PRDY1
R31
13
R10
3.92k
6
VSEN
R32
ISEN2 VDD2 VIN2 SGND2 PWM2
10uF 10uF 10uF 10uF 0
C47
11 Vin +5V
IP2002-2 IP2002PBF-2
TP14
PGND
4.42k
open
TP15
PGND
D1
12 PWM2 +5V
R11 R16 TP7 R23 R7
VSW2 10k 10k
C6
C7
C8
C30 TP16
PGND
PRDY1
CMPD3003A
3
2.49k
TP5
ISEN3 ENABLE2 10 ENABLE2 VSW2 VSW2
C35 R30
+5V
open open
1
PGOOD
PRDY2
2
0.22uF
2
PGOOD
TP21 L2
0.3uH
C36 R24
9
0
VOUTS
VOUTS
0.22uF
7 PWM3
FS/EN
R12 R29
+5V PGND2 PRDY2 PRDY2
open
C17
100uF
C18
100uF
C43
open
C34
0.1uF
C46
10uF
PRDY3 PWM4 16
R4
PGNDS
3
20K
C37 R13
0
1
TP22
PGNDS
PRDY4
0.22uF
2
C38 D2
0.22uF
CMPD3003A
IP2002-3 IP2002PBF-3
ISEN4 VDD3 VIN3 SGND3 15 +5V Vin
8
GND
U1 C9
10uF
ISL6558CB
C10
10uF
C11
10uF
C31
10uF
PWM3 +5V
R17
10k 10k
R25
ENABLE3 ENABLE3 VSW3 VSW3
R8
2.49k
TP8
VSW3
R26
open
L3
0.3uH
C19
100uF
C20
100uF
C44
open
12V / 5V CONVERTER
PGND3 PRDY3 +5V PRDY3
U6
Vin
Vin
Vdd
C27
10uF
C29
1uF
IP2002-4 IP2002PBF-4
+5V VDD4 VIN4 SGND4 Vin
4-Phase Reference Design Schematic
C12
PWM4 +5V
10uF
C13
10uF
C14
10uF
C32
10uF
R18
10K 10K
R27
ENABLE4 ENABLE4 VSW4
R9
2.49k
TP9
VSW4
R28
open
VSW4
L4
0.3uH
C21
100uF
C22
100uF
C45
open
PGND4 PRDY4 PRDY4
Title Size
IP2002_4 phase demo board
Number Revision
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IP2002PBF
Quantity 1 17 8 2 1 1 1 1 1 4 3 5 3 5 9 2 1 1 4 1 7 2 1 1 4 1 1 4 1 Designator C1 C10 C11 C12 C13 C14 C3 C30 C31 C32 C33 C4 C46 C5 C6 C7 C8 C9 C15 C16 C17 C18 C19 C20 C21 C22 C2 C29 C25 C26 C27 C28 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C47 R1 R2 R31 R10 R11 R12 R13 R35 R16 R17 R18 R19 R21 R23 R25 R27 R34 R3 R32 R33 R4 R5 R7 R8 R9 R6 R22 R24 R26 R28 R29 R30 R36 D1 D2 D5 D6 L1 L2 L3 L4 L5 U1 U2 U3 U4 U5 U6 Value 1 6800pF 10.0uF 100uF 10.0uF 8.20pF 1800pF 1.00uF 0.010uF 0.100uF 0.22uF 330uF Open 3.92K 0 10.0K 4.42K 30.1K 20.0K 2.49K 200 Open 30V 40V 30V 0.3uH 15uH 4.5 - 5.5V 30A 4.7 - 25V Value 2 50V 16V 6.3V 6.3V 50V 50V 16V 50V 50V 6.3V 16V 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W 1/8W Type 2 X7R X5R X5R X5R NPO X7R X7R X7R X7R X5R WA series thin film thick film thick film thin film thick film thick film thick film thick film Tolerance 10% 10% 20% 10% 3% 10% 10% 10% 10% 10% 20% 0.10% <50m 1% 0.10% 1% 1% 1% 1% Package 0805 1206 1210 1206 0805 0805 0805 0805 0805 0603 SMD 0805 0805 0805 0805 0805 0805 0805 0805 Mfr. PHICOMP Murata TDK TDK PHICOMP PHICOMP MuRata TDK ROHM TDK Panasonic BC Component ROHM KOA BC Component KOA KOA KOA KOA Mfr. Part No. 08052R682K9BB0 GRM31CR61C106KC31B C3225X5R0J107M C3216X5R0J106K 0805CG829C9BB0 08052R182K9BB0 GRM40X7R105K016 C2012X7R1H103KT MCH215C104KP C1608X5R0J224K EEF-WA1C331P 2312-241-73922 MCR10EZHJ000 RK73H2A1002F 2312-241-74422 RK73H2A3012F RK73H2A2002F RK73H2A2491F RK73H2A2000F CMPD3003A 10MQ040N CMPSH-3 ETQP2H0R3BFA 1008PS-153M ISL6558CB iP2002 IP2002PBF LT1616
200mA schottky sot23 Central 2.1A schottky D-64 IRF 100mA schottky sot23 Central 36A ferrite 20% SMT Panasonic 0.70A ferrite 20% SMT Coilcraft 0.8 - 5V PWM controller 0 - 70C 16 Ld SOIC Intersil Power Block 11mm x 11mm International Rect 1.8 - 5V PWM controller -40 to +85C S6 Linear Technology
4-Phase Reference Design Bill of Materials
Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products:
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGAs on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1047: Graphical solution for two branch heatsinking Safe Operating Area Detailed explanation of the dual axis SOA graph and how it is derived. www.irf.com 9
IP2002PBF
VDD NC NC SGND NC NC
ENABLE
VIN
PGND
NC NC
PWM
NC NC NC NC NC PGND
VSW
NC
PRDY
NC
NC
Dimensions shown in inches (millimeters)
Recommended PCB Footprint (Top View)
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IP2002PBF
0.15 [.006] C 2X 6 11.00 [.433] B A 5 C 0.45 [.0177] 0.35 [.0138]
BALL A1 CORNER ID 11.00 [.433]
0.12 [.005] C
NOTES: 1. 2. 3. 4. 5 6 7 DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETER SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C.
TOP VIEW
0.15 [.006] C 2X 6
133X O
0.55 [.0216] 0.45 [.0178]
7
0.15 [.006] 0.08 [.003]
CAB C
0.40 [.016] 4X BOTTOM VIEW
0.80 [.032] 22X
(4X 1.1 [.043])
2.31 [.0909] 2.11 [.0831] 2.76 [.1087] 2.46 [.0969] SIDE VIEW
Mechanical Drawing
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11
IP2002PBF
0123 XXXX IP2002PBF iP2002
Part Marking
0123 601000 iP2002 IP2002PBF
0123 601000 iP2002 IP2002PBF
24mm
16mm
FEED DIRECT ION
NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541.
Tape & Reel Information
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IRs Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.5/06 12 www.irf.com

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