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Datasheet File OCR Text:

STA011
L-band RF front-end for digital radio
Preliminary Data
Features

Single chip receiver for satellite and terrestrial digital radio Super-heterodyne tuner with low IF output High input intercept point Low noise IC RF image rejection mixer Adjustable RF and IF gain 54 dB IF VGA gain range Integrated RF and IF VCOs Integrated synthesizers Low cost external components I2C-bus slave control interface Unregulated 2.7 to 3.3V supply voltage TQFP44
Description
The STA011 is an RF IC using STMicroelectronics BiCMOS6G high speed technology for one chip solution for the digital satellite radio receiver. The STA011 is assembled in a TQFP44 package. The front-end architecture is a double conversion receiver (see block diagram). The chip includes all the RF functions up to low IF and it manages the signals going to and coming from the base-band.
Table 1.
Device summary
Order code STA011 Package TQFP44 (10x10x1.4mm)(1) Packing Tube
1. ECOPACK(R) (see Chapter 8).
November 2007
Rev 1
1/38
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STA011
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 Absolute maximum/minimum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 Receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synthesizers, PLL, charge pump and VCOs . . . . . . . . . . . . . . . . . . . . . . 16 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 I2C-bus specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 Power ON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write operation (single byte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write operation (multibyte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.1 Write mode (multibyte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/38
STA011
Contents
5.3
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.1 Bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Programming specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 RFPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reference divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VCO output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Charge pump current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PFD programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fractional spurious compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
RF path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.1 6.2.2 6.2.3 Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RF gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IF buffer setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 6.4 6.5
IF path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1 Blocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Lock detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 IFVCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PFD programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge pump enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reference divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6 6.7
XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 8 9
Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of tables
STA011
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum/minimum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply currents, (Tamb = 25C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LNA, RF mixer and IF1 buffer, (Tamb = 25C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . 10 IFVGA amplifiers, IF mixer and output buffer (Tamb = 25C, VP-VN = 3V). . . . . . . . . . . . . 11 Base-band output performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Crystal oscillator, (T=25C, VP-VN=3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PLLs, Synthesizers, (Tamb = 25C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RF VCO, (Tamb = 25CC, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IF VCO, (Tamb = 25C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface . . . . . . . . . . . 14 Additional optional interface (REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Start and stop electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ACK electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6th data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reference divider division ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VCO output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Charge pump current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Frequency phase detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fractional spurious compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DAC current adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Down Asym delay setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RF gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IF Buffer setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Blocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Lock detector setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IFVCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Frequency phase detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge pump enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reference divider division ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4/38
STA011
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical IF overall gain vs control voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System clock input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Validity on I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing diagram of the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ack on I2Cbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TQFP44 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/38
Block diagram
STA011
1
Block diagram
Figure 1. Block diagram
SIP,SIN LNI
LNA RFMixer IF1 Buffer
SOP,SON
VGAs
IFAGC
IFMixer
IF2 Buffer
RXI,NRXI
NLNI 2nd PLL /8 PADJ1,2
DIGITAL I2CBUS
N2 SCL
Charge Pump PFD
CIRCUITRY INTERFACE
FLT2
VCO
SDA
R2 1st PLL /2 N1 M_CLK1,2
VCO Charge Pump PFD
R1
MUX MUX
OSC
FLT1
XOSEL
REF
XTAL1,2
AC00335
6/38
STA011
Pins description
2
Pins description
Figure 2. Pins connection (top view)
AGC2 AGC1 NTK2 FLT2 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 VP2 TK1 VP2 XTAL1 XTAL2 REF XOSel NTK1 FLT1 VN2 TLCK SON SOP VN4 VN4 VP4 VP4 TK2
44 43 42 41 40 39 38 37 36 35 34 VP1 SIP SIN VN1 LNI NLNI VN1 Address PADJ1 PADJ2 ENRFOSC 1 2 3 4 5 6 7 8 9 10 11 RXI NRXI GADJ2 GADJ1 CE VP3 SCL SDA VN3 M_CLK1 M_CLK2
AC00336
Table 2.
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pins description
Name VP1 SIP SIN VN1 LNI NLNI VN1 Address PADJ1 PADJ2 ENRFOSC VP2 TK1 NTK1 VP2 FLT1 VN2 Positive supply 1 SAW filter input connection SAW filter input connection Negative supply1 RF input RF input Negative supply 1 Device address selection RF gain adjust connection1 RF gain adjust connection2 RF oscillator hardware enable Positive supply 2 External LO1 connection1 External LO1 connection2 Positive supply 2 1st PLL loop filter connection Negative supply 2 Function
7/38
Pins description Table 2.
N. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
STA011 Pins description (continued)
Name XTAL1 XTAL2 REF XOSel TLCK M_CLK2 M_CLK1 VN3 SDA SCL VP3 CE GADJ1 GADJ2 NRXI RXI FLT2 VP4 TK2 NTK2 VP4 AGC1 AGC2 VN4 SON SOP VN4 Function Quartz oscillator connection 1 Quartz oscillator connection 2 External optional TCXO input Internal/external XO selection Lock detector output Master Clock differential output2 Master Clock differential output1 Negative supply 3 Data Serial Input Clock Input Positive supply 3 Chip Enable IF gain adjust connection 1 IF gain adjust connection 2 Low IF Signal output 2 Low IF Signal output 1 2nd PLL loop filter connection Positive supply 4 External LO2 connection1 External LO2 connection2 Positive supply 4 VGA control pin 1 VGA control pin 2 Negative supply 4 SAW filter negative output connection 2 SAW filter output connection 1 Negative supply 4
8/38
STA011
Electrical specifications
3
3.1
Table 3.
Symbol Tstg Top VMax VMin Vpmax VESD,HBM
Electrical specifications
Absolute maximum/minimum ratings
Absolute maximum/minimum ratings
Parameter Storage temperature Operating ambient temperature Maximum voltage on each pin Minimum voltage on each pin Minimum/Maximum power supply Between VP1,2,3,4 and VN1,2,3,4 Electrostatic discharge Voltage (ESD, Human Body Model) GND-0.3 -0.3 3.6 2 kV Min. -40 -40 25 Typ. Max. 125 85 3.6 Unit C C V V
3.2
Table 4.
Symbol VP Tj
Operating conditions
Operating conditions
Parameter Operating supply voltage Junction temperature Test conditions/notes Min. 2. 7 Typ. Max. 3.3 125 Unit V C
3.3
Table 5.
Symbol Rth j-amb
Thermal data
Thermal data
Parameter Thermal resistance junction to ambient Test conditions/notes According to JEDEC specification on a layers board Min. Typ. 45 Max. Unit C/W
9/38
Electrical specifications
STA011
3.4
Table 6.
Symbol ICC1
Electrical characteristics
Supply currents, (Tamb = 25C, VP-VN = 3V)
Parameter Current supplied by VP1 Test conditions/notes Powered circuits: LNA, RFMixer, IF buffer Powered circuits: RFVCO, divider by 2 and LO buffer Min. 12.5 Typ. 17 Max. 21.5 Unit mA
5.5
9
12.5 mA
ICC2
Current supplied by VP2 Powered circuits: external LO1, divider by 2 and LO buffer Powered circuits: Digital cells, Crystal oscillator (XOSel high) 11.5 5.5 15 7 18.5 11.5
ICC3
Current supplied by VP3 Powered circuits: Digital cells, external REF (XOSel low) Powered circuits: VGAs, IFMixer, output buffer, IFPLL Current supplied by VP4 VAGC1=VAGC2=1.2V, IFgain=75dB ICC1+ ICC2+ ICC3+ ICC4 Standby current CE = high, XOSel high, RFVCO enabled CE = low 3.5 6 8
mA
ICC4
8.5
13
17.5
mA
ICCTOT ICCTOT,SB
36
46
56 20
mA A
Table 7.
Symbol BWi BW0 GV
LNA, RF mixer and IF1 buffer, (Tamb = 25C, VP-VN = 3V)
Parameter Input signal BW Output signal BW Voltage gain Input LNI, NLNI pins; output SIP, SIN pins. RL = 200, PADj1,2 pins floating Input LNI, NLNI pins; output SIP,SIN pins. RL=200, Rext=0 Programmable via software mode Balanced @ LNi, NLNI pins, R//C Balanced @ SIP, SIN pins LNI,NLNI pins Measurements condition: Input LNI, NLNI pins; output SIP,SIN pins,RL=200, PADj1,2 pins floating, Rs=50 Test conditions/notes Min. 1452 114 26 30 Typ. Max. 1492 116.5 34 Unit MHz MHz dB
GV,trim GV Zi Zo
Voltage gain Voltage gain variation Input impedance Output impedance Return loss
19
25
29
dB
2.5 75 0.2 50 14
dB pF dB
NF
Noise figure
5
7
dB
10/38
STA011 Table 7.
Symbol NFtrim
Electrical specifications LNA, RF mixer and IF1 buffer, (Tamb = 25C, VP-VN = 3V) (continued)
Parameter Noise figure @ minimum gain Test conditions/notes Measurements condition: Input LNI, NLNI pins; output SIP,SIN pins,RL=200, Rext=0, Rs=50 Input LNI, NLNI pins; output SIP,SIN pins. RL=200, PADj1,2 pins floating Input LNI, NLNI pins; output SIP,SIN pins. RL=200, Rext=0 Input LNI, NLNI pins; output SIP,SIN pins. RL=200,PADj1,2 pins floating Input LNI, NLNI pins; output SIP,SIN pins. RL=200, Rext=0 RFin = LO-IF Connected between PADJ1 and PADJ2, to obtain intermediate gain between min and max -21 Min. Typ. 6.5 Max. 8.5 Unit dB
IIP3
Input IP3
-17
-12
dBm
IIP3trim
Input IP3 @ minimum gain 1dB compression point 1dB compression point Image rejection REXT usable range LO1 to IF1 leakage LO1 to RF leakage LNI,NLNI common mode DC voltage SIP,SIN common mode DC voltage
-18
-14.5
-7
dBm
1dB C.P.
-29
-26
dBm
1dB C.P.trim IR REXT trim IF1leak RFleak VDC,RFin VDC,IFout
-27 15 10
-24
dBm dB 100 -24 -29 k dBm dBm V V
AC coupled to the balun AC coupled to the SAW filter
VP-1.3 VP-1.45
VP-1.1 VP-1.2
VP-0.9 VP-0.95
Table 8.
Symbol BWi BWo Gmin
IFVGA amplifiers, IF mixer and output buffer (Tamb = 25C, VP-VN = 3V)
Parameter Input signal BW Output BW Minimum gain Input SOP, SON pins; output RXI,RXIN pins, RLoad high impedance, VAGC1,2 = 0V Input SOP, SON pins; output RXI,RXIN pins, RLoad high impedance, VAGC1,2 = 3V 80 Test conditions/notes Min. 114 0.6 32 Typ. Max. 116.5 3.1 38 Unit MHz MHz dB
Gmax IAGC ZAGC
Maximum gain Input current in AGC pin AGC input impedance
86 10
dB A k
150
600
11/38
Electrical specifications Table 8.
Symbol
STA011
IFVGA amplifiers, IF mixer and output buffer (Tamb = 25C, VP-VN = 3V) (continued)
Parameter Test conditions/notes Measurements condition: Input SOP, SON pins; output RXI, NRXI pins, Rs=50, Double Side Band, IFGain=65dB Gain=65dB Gain=81dB Gain=65dB Gain=81dB Balanced @ SOP, SON, Balanced @ RXI, RXIN Corresponding to 1.75mA in each emitter follower AC coupled to the SAW filter VP-1.3 VP-2.1 VP-0.3 Balanced GADJ1, GADJ2 pins Obtained by using low pass filter at the output Obtained by using SAW filter at the input 650 -53 -69 -45 -61 Min. Typ. Max. Unit
NF
Noise Figure
9
12
dB
1dB cp 1dB cp,fg IIP3 IIP3,fg Zin Zout
1dB compression point 1dB compression point, full gain Input IP3 Input IP3 Input impedance Output impedance SIP, SIN common mode DC voltage
-50 -66 -41 -57 50 50
dBm dBm dBm dBm
VDC,IFin VDC,RXout VDC,PADJ Zadj BBleak IF2leak
VP-1.1 VP-1.8 VP-0.12 800 -49 -44
VP-0.9 VP-1.65 VP-0.5 950 -30 -30
V V V W dBm dBm
RXI,NRXI common mode AC coupled to the base-band DC voltage PADJ1,2 common mode DC voltage Gain adjustment pins impedance LO2 to BB leakage LO2 to IF1 leakage
Figure 3.
Typical IF overall gain vs control voltage
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
60
90
IF TOTAL VOLTAGE GAIN (dB)
IF TOTAL VOLTAGE GAIN (dB)
55
85
50
IF gain (dB)
80
IF gain (dB)
45
75
40
70
65
35
60
30 0.7 0.75 0.77 0.79 0.8 0.82 0.84 0.86 0.88 0.9
1 1.1
1.2 1.3
1.4 1.5
1.6 1.7
1.8 1.9
2 2.1
2.2 2.3
2.4 2.5
2.6 2.7
V(AGC1, AGC2) (Volt)
V(AGC1, AGC2) (Volt)
12/38
STA011 Table 9.
Symbol
Electrical specifications Base-band output performance
Parameter Baseband Output load resistance Baseband output load capacitance Test conditions/notes The output resistance the IC is loaded SE to GND The output capacitance the IC is loaded SE to GND Min. Typ. Max. Unit
Rload
5
K
Cload
10
pF
Table 10.
Symbol fXTAL1 fXTAL2 Pn VDC,XTAL
Crystal oscillator, (T=25C, VP-VN=3V)(1)
Parameter Quartz frequency Quartz frequency Phase Noise XTAL1,2 common mode voltage Test conditions/notes Resonance mode: series Using 14.72 Resonance mode: series Using 14.725 f=1kHz VP-1.1 Min. Typ. 14.72 14.725 -120 VP-.9 -118 VP-.7 Max. Unit MHz MHz dBc V
1. A 18pF capacitor connected from XTAL1 pin to gnd is suggested for start-up robustness (see Figure 4).
Figure 4.
System clock input/output
REF MUX Output Buffer M_CLKP CD to baseband Cp
TCXO
XTAL2
yy ;; yy ;; yy ;;
XTAL1
18pF
AC00414
Table 11.
Symbol ts Pn fREF1 fREF2 PSP
PLLs, Synthesizers, (Tamb = 25C, VP-VN = 3V)
Parameter RF pll loop setting time Total phase noise contribution RF pll comparison frequency IF pll comparison frequency Spurious power level 100Hz13/38
Electrical specifications Table 11.
Symbol
STA011
PLLs, Synthesizers, (Tamb = 25C, VP-VN = 3V) (continued)
Parameter RF PLL selectable division ratios IF PLL selectable division ratios REF1 division ratio REF2 division ratio Test conditions/notes From REF1 to LO1, fcomp=3.68MHz fcomp=113.23KHz Programmable via software mode Programmable via software mode Min. 360.75 (363.625 1st used) 987 1 1034 4 130 Typ. Max. 376.5 (373.75 last used) 1081 16 Unit
Nprog1
Nprog2 NREF1 NREF2
Table 12.
Symbol fosc FLO1_1 FLO1_2 VFLT1
RF VCO, (Tamb = 25CC, VP-VN = 3V)
Parameter VCO frequency oscillation LO1 frequency range LO1 frequency range Freq control voltage range after divider by 2, by using 14.72MHz crystal after divider by 2, by using 14.725MHz crystal FLT1 pin Test conditions/notes Min. 2676.28 1338.14 Typ. Max. 2750.8 1375.4 Unit MHz MHz MHz V
1338.134375 to 1375.407031 VN+0.2 VP-0.2
Table 13.
Symbol fosc fLO2_1 fLO2_2 VFLT2
IF VCO, (Tamb = 25C, VP-VN = 3V)
Parameter VCO frequency oscillation LO2 frequency range LO2 frequency range Frequency control voltage range after divider by 8, by using 14.72MHz crystal after divider by 8, by using 14.725MHz crystal FLT2 pin Test conditions/notes Min. 894.08 111.76 111.8 VN+0.2 Typ. 936.64 117.08 117.12 Max. 979.2 122.4 122.44 VP-0.2 Unit MHz MHz MHz V
Table 14.
Symbol
Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface (Tamb = 25C, VP-VN = 3V)
Parameter Test conditions/notes Min. Typ. Max. Unit
Input parameters (SCL, SDA, ENRFOSC, XOSEL)
VIH VIL Tt Rin Input edge transition Input resistance 10 High Digital input signals Low VN VN+.7 0.1 V s/V M VP-.7 VP V
14/38
STA011 Table 14.
Symbol
Electrical specifications Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface (continued) (Tamb = 25C, VP-VN = 3V)
Parameter Test conditions/notes Min. Typ. Max. Unit
Output parameter (TLCK)
VOH VOL tr tf Rise time Fall time High Digital output signals Low C=5pF C=5pF VN 0.4 0.4 VN+.7 0.6 0.6 V s/V s/V VP-.7 VP V
Differential digital interface (M_CLK1, M_CLK2)
VOH VOL VDC,M_CLK tr tf Zout FM_CLK1 FM_CLK2 Digital output signals, V(M_CLK1)-V(M_CLK2) M_CLK1,2 Common mode voltage Rise time Fall time Output impedance M_CLK frequency M_CLK frequency Cl=5pF each pin C=5pF balanced Using a 14.72MHz quartz Using a 14.725MHz quartz High Low VP-1.65 0.3 -0.3 VP-1.4 10 10 500 14.72 14.725 VP-1.2 12 12 ns ns MHz MHz V V
Table 15.
Symbol PREF VDC Rin
Additional optional interface (REF)
Parameter External reference input power REF DC voltage Input resistance Test conditions/notes It must be AC coupled to REF, XOSel low XOSel low Min. -2 VP-1.2 Typ. 0 VP-1.35 70 VP-1.6 Max. Unit dBm V k
15/38
Functional description
STA011
4
4.1
Functional description
Receiver chain
The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz carrier directly usable by the channel decoder. In front of the STA011 IC there it must be an external LNA and a band-pass filter; the band-pass filter limits the input bandwidth and guarantees a suitable rejection to the image frequency. The STA011 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is down-converted, using an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz. The RF gain can be reduced by 5dB by using an external trimmer/resistor connected between the PADJ1 and PADJ2 pins, and it can also be reduced by 7.5dB (2.5 step) via thesoftware mode. A 54 dB typical gain range is guaranteed at IF level. By connecting an external trimmer/resistor to pins GADJ1, GADJ2, the IF output signal level can be decreased to the desired value. Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and trimming the gain by connecting an external resistor between GADJ1 and GADJ2. By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static gain is obtained. The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is down-converted to a second IF of 1.84 MHz. A differential clock output of 14.72 MHz is available for use from the base-band.
4.2
Synthesizers, PLL, charge pump and VCOs
The first voltage controlled oscillator is controlled by an integrated PLL, and it's able to cover a frequency range of 37 MHz with a step size of 460 KHz. The second voltage controlled oscillator produces a fixed 8 x 117.08MHz frequency, scaled by a divider by 8, and controlled by a second integrated PLL. Moreover, the 2nd PLL is able cover the frequency range from 111.76MHz to 122.4MHz, suitable for anapplication test. The other components of the first PLL synthesizer are a low frequency programmable divider and a dual modulus prescaler; a fixed divider is instead used to synthesize the second VCO fre-quency. Other internal programmable dividers are used to obtain the comparison frequencies of both loops. Channel selection is made through the I2CBUS interface, directly from the P.
4.3
Power supplies
The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the base-band chips are operate between these supplies unless otherwise specified.
4.4
Interface specification
All the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power supply (GND). The interface voltage levels are therefore fully compatible with the base-band circuits. The digital levels are all CMOS threshold compatible with the ex-ception of M_CLK1, M_CLK2 pins (ECL type). For a total solution all other interface signals are also included.
16/38
STA011
I2C-bus interface
5
I2C-bus interface
Data transmission from the microprocessor to the STA011 takes place through the 2 wires (SDA and SCL) of the I2C-bus interface. The STA011 is always a slave device.
5.1
I2C-bus specifications
The I2C-bus protocol defines any device that sends data to the bus as a transmitter, and any device that reads the data as a receiver. The device that controls the data transfer is known as the Master and the others as the slave. The master will always initiate the transfer and will provide the serial clock for synchronization.
5.1.1
Power ON reset
The device at Power ON is able to configure itself to a fixed configuration, with all the circuitry ON and the RFPLL output frequency set to 1356.54MHz (fcomp=3.68MHz, N=368.625)
5.1.2
Data validity
Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH are used to identify START or STOP condition.
5.1.3
Start condition
Start is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer.
5.1.4
Stop condition
A LOW to HIGH transition of the data bus SDA identifies a stop while the clock signal SCL is stable in the HIGH state. A STOP condition terminates communications between the STA011 and the Bus Master.
5.1.5
Byte format
Every byte transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
5.1.6
Acknowledge
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits of data.
17/38
I2C-bus interface
STA011
5.1.7
Transmission without acknowledge
To avoid detecting an acknowledge from the STA011, the P can use a simpler transmission: simply it waits one clock period without checking the STA011 acknowledging, and sends the new data. This approach of course is less protected from data corruption.
5.1.8
Device addressing
To start the communication between the master and the STA011, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corre-sponding to the device select address and read or write mode. The first 7 MSBs are the device address identifier, corresponding to the I2C-bus definition. For the STA011 these are fixed as 110000A. The A bit is reset to 0 internally by a pull-down re-sistor but it can be changed through the corresponding external pin Address. In this way if the Address pin is floating the address is fixed to the previous configuration (110000), otherwise if the pin is set high the address is fixed to 1100001. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STA011 identifies on the Bus the device address and, if matched, it will acknowledge the identification on the SDA bus during the 9th clock pulse. The following byte after the device identification byte, is the internal sub-address byte that provides access to any of the internal registers.
5.1.9
Write operation (single byte write)
Following a START (S) condition the master sends a device select code with the RW bit set to 0. The I2C gives the acknowledgement and waits for the 1 byte of internal sub address. This byte provides access to any of the internal registers. After the reception of the internal byte sub address the I2C again responds with an acknowledgement. The master terminates the transfer by generating a STOP (P) condition. A single byte write with sub-address 00H would affect DATA_OUT[119:112], so a single byte write with sub-address 02H would affect DATA_OUT[103:96] and so on A single byte address with sub-address out of ranges 00H - 0FH produces illegal_subaddress signal to go high and DATA_OUT[119:0] will not change until a successive write operation request with the correct range for sub-address will be made. For example if the sub-address is 15H will be produced illegal_subaddress = '1' and DATA_OUT will no change.
S 110000A R/W 0 ack Sub-address byte ack DATA IN ack P
5.1.10
Write operation (multibyte write)
The multi-byte write mode can start from any internal sub address (the same as a single byte write). Following a START (S) condition the master sends a device select code with the RW bit set to 0. The I2C gives the acknowledgement and waits for 1 byte from the internal sub address. This byte provides the starting byte of the internal registers.
18/38
STA011
I2C-bus interface The master sends the data and each byte isacknowledged by the I2C. The master terminates the transfer by generating a STOP (P) condition. The sub-address decides the starting byte. A Multi-byte with sub-address 00H and 5 DATA_IN bytes would affect the bytes starting from DATA_OUT [119:112] to DATA_OUT [87:80] and so on. A Multi byte with sub-address from the ranges 00H - 0FH produces illegal sub-address signal to go high, and DATA_OUT[119:0] will not change until a successive write operation request, with the correct range for sub-address will be made.
S
110000A
R/W 0
ack
Sub-address byte
ack
DATA IN
ack
............
DATA IN
ack
P
5.1.11
Read operation
Current byte address read
For the I2C of STA011 this is the only read mode operation implemented. In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1. The I2C acknowledges this and outputs the byte data by reading from the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition.
S 110000A R/W 1 ack DATA No ack P
This method operation is not used.
Data validity
Figure 5. Validity on I2C-bus
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Timing diagram of the I2C-bus:
Figure 6. Timing diagram of the I2C-bus
SCL I2CBUS SDA
D99AU1032
START
STOP
19/38
I2C-bus interface
STA011
Acknowledge on the I2C-bus:
Figure 7.
SCL
Ack on I2Cbus
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
5.1.12
Timing specification
Figure 8. Data and clock
SDA SCL
tcwl tcs tch tcwh
AC00337
Table 16.
Timing electrical characteristics
Parameter Data to clock set up time Data to clock hold time Clock pulse width high Clock pulse width low Minimum time (ns) 100 50 100 100
Symbol tcs tch tcwh tcwl
5.1.13
Start and stop
Figure 9. Start and stop
SDA SCL
tstart1 tstart2
tstop2tstop1
AC00338
20/38
STA011 Table 17. Start and stop electrical characteristics
Parameter Clock to data start time Data to clock down stop time
I2C-bus interface
Symbol Tstart1,2 Tstop1,2
Minimum time (ns) 100 100
5.1.14
ACK
Figure 10. ACK
SDA SCL 8 9
td1
td2
AC00339
Table 18.
ACK electrical characteristics
Parameter Ack begin delay Ack end delay Maximum time (ns) 200 200
Symbol td1 td2
21/38
I2C-bus interface
STA011
5.2
5.2.1
MSB S MSB 1
Software specification
Write mode (multibyte write)
device address 1 0 0 0 0 LSB A 0 LSB ack MSB S7 MSB S6 sub-address byte S5 S4 S3 S2 S1 LSB S0 LSB ack
1st data byte
2nd data byte
D119 D118 D117 D116 D115 D114 D113 D112 ack D111 D110 D109 D108 D107 D106 D105 D104 ack MSB 3rd data byte D98 D97 LSB D96 LSB D82 D81 D80 LSB D66 D65 D64 LSB D50 D49 D48 LSB D34 D33 D32 LSB D18 D17 D16 ack ack ack ack ack ack MSB D95 MSB D79 MSB D63 MSB D47 MSB D31 MSB D15 D14 D13 D12 D30 D29 D28 D46 D45 D44 D62 D61 D60 D78 D77 D76 D94 D93 D92 4th data byte D91 D90 D89 LSB D88 LSB D73 D72 LSB D57 D56 LSB D41 D40 LSB D25 D24 LSB D9 D8 ack ack ack ack ack ack
D103 D102 D101 D100 D99 MSB D87 MSB D71 MSB D55 MSB D39 MSB D23 MSB D7 D6 D22 D21 D38 D37 D54 D53 D70 D69 D86 D85 5th data byte D84 D83
6th data byte D75 D74
7th data byte D68 D67
8th data byte D59 D58
9th data byte D52 D51
10th data byte D43 D42
11th data byte D36 D35
12th data byte D27 D26
13th data byte D20 D19
14th data byte D11 D10
13th data byte D5 D4 D3 D2 D1
LSB D0 ack P
ack = Acknowledge S = Start P = Stop
Bits description
1st data byte
RFPLL Loop divider M counter D119 D118 D117 D116 D115 D114 D113 D112
22/38
STA011 2nd data byte
RF PLL Loop divider Loop divider A counter D111 D110 D109 D108 D107 K (fractional) D106
I2C-bus interface
D105
D104
3rd data byte
RF PLL Reference divider Division ratio D103 D102 D101 D100 D99 D98 D97 D96 Div 2 Enable Loop div Enable CP Enable
4th data byte
RFPLL VCO Enable D95 ext LO Enable D94 VCO output voltage setting D93 D92 Prescaler Enable D91 Charge Pump current setting D90 D89 D88
5th data byte
RF PLL Phase frequency detector PFD setting D87 D86 D85 D84 D83 Down ASYM enable D82 Down Split enable D81 DAC Enable D80
Table 19.
6th data byte
RFPLL DAC current adjustment Down Asym delay setting D75 D74 D73 Not used D72
D79
D78
D77
D76
23/38
I2C-bus interface 7th data byte
RF path LNA enable D71 RF Mixer enable D70 D69 RF Gain Setting D68 IF Buffer enable D67 IF Buffer Current setting D66 IFpath Pre VGA enable D65
STA011
VGA1 enable D64
8th data byte
IF path VGA2 enable D63 IF Mixer enable D62 IF2 amp enable D61 D60 IFPLL Lock detector setting D59 D58 VCO Enable D57 ext LO Enable D56
9th data byte
IF PLL PFD setting D55 D54 D53 D52 D51 CP enable D50 Ref div Division ratio D49 D48
10th data byte
IF PLL Reference divider division ratio D47 D46 D45 D44 D43 D42 D41 Loop div ratio D40
11th data byte
IF PLL Loop divider Division ratio D39 D38 D37 D36 D35 D34 D33 D32
24/38
STA011 12th data byte
IF PLL Loop divider division ratio D31 Not used D31 D30 Not used D30 M_CLK output disable D29 Not used ... Double/ single ended D28 Not used ... XTAL Cut-off frequency setting D27 Not used ... D26 ... ...
I2C-bus interface
Loop gain setting D25 ... ....
Not used D24 . ....
5.3
Read mode
Current byte address read
MSB S 1 1 0 chip address 0 0 0 A R/W 1 MSB ack B7 B6 data byte B5 B4 B3 B2 B1 LSB B0 P
ack = acknowledge s = start p = stop
5.3.1
Bits description
In read mode, only one byte is provided to the master.
PLL's Lock B7 Not used B6 Not used B5 Not used B4 Not used B3 Not used B2 Not used B1 Not used B0
The last six not used bits are fixed to 0.
25/38
Programming specifications
STA011
6
6.1
6.1.1
Programming specifications
RFPLL
Loop divider division ratio
M counter D119 D118 D117 D116 D115 D114 D113 D112 Notes
... 0 ... 0 ...
... 0 ... 0 ...
... 1 ... 1 ...
... 0 ... 1 ...
... 1 ... 1 ...
... 1 ... 0 ...
... 1 ... 0 ...
... 0 ... 0 ... M=46, startup configuration
A counter D111 D110 D109 D108
K (fractional) D107 D106 D105 D104
Description N=M*P+A+K/32 (P=8)
1 ... 0 ... 1 ... 1
0 ... 0 ... 1 ... 0
1 ... 0 ... 0 ... 1
1 ... 1 ... 0 ... 1
1 ... 0 ... 0 ... 1
0 ... 1 ... 1 ... 0
0 ... 0 ... 1 ... 0
1 ... 0 ... 1 ... 1 N=368.625, LO1=368.625x3.68= 1356.54 MHz, startup configuration
26/38
STA011
Programming specifications
6.1.2
Reference divider division ratio
Table 20.
D103 0 0 ... 0 ... 0 ... 1
Reference divider division ratio
D101 0 0 ... 1 ... 0 ... 0 D100 0 1 ... 0 ... 0 ... 0 D99 1 0 ... 0 ... 0 ... 0 R=16 fcomp=.92MHz R=8 fcomp=1.84MHz R=1 R=2 ... R=4 XTAL=14.72MHz fcomp=3.68MHzKHz, startup configuration Description Notes XTAL or TCXO=14.72MHz fcomp=14. 72MHz, ...
D102 0 0 ... 0 ... 1 ... 0
6.1.3
Blocks enable
Table 21. Blocks enable
Description D98 0 1 D97 0 1 D96 0 1 D91 0 1 Prescaler OFF Prescaler ON Startup configuration Charge Pump OFF Charge Pump ON Startup configuration Loop Divider OFF Loop Divider ON Startup configuration Divider by 2 OFF Divider by 2 ON Startup configuration Notes
27/38
Programming specifications
STA011
6.1.4
VCO enable
Table 22.
D95 1 1
VCO enable
D94 0 1 Description Internal RFVCO External RFLO Notes Startup configuration
The internal RFVCO can also be enabled via hardware mode through the ENRFOSC pin. With the ENRFOSC pin high the software mode is disabled and the RFVCO is turned ON; with the ENRFOSC pin low the software mode is enabled, depending on the truth table described above .
6.1.5
VCO output voltage
Table 23.
D93 0 0 1 1
VCO output voltage
D92 0 1 0 1 Vout=1Vpp Vout=2Vpp Vout=3Vpp Vout=4Vpp Description Notes Startup configuration
6.1.6
Charge pump current setting
Table 24.
D90 0 ... 0 . 1 1 1
Charge pump current
D89 0 ... 1 D88 0 ... 1 ICP=300uA ....... ICP=400uA ....... ICP=600uA Startup configuration Description Notes
28/38
STA011
Programming specifications
6.1.7
Table 25.
D87 x x x 0 0 1 1 D82
PFD programming
Frequency phase detector setting
D86 x x x 0 1 0 1 D85 1 1 1 0 0 0 0 D84 x 0 1 x x x x D83 1 0 0 x x x x Description Normal operation Reference divider test, available @Lock Loop divider test available @ Lock Charge pump test, high impedance state Charge pump test, DEC active Charge pump test, INC active Charge pump test, DEC&INC active Down ASYM 0 1 UP and DOWN sym UP and DOWN asym Startup configuration Notes Default configuration Synthesizer test reserved configuration Synthesizer test reserved configuration Synthesizer test reserved configuration Synthesizer test reserved configuration Synthesizer test reserved configuration Synthesizer test reserved configuration
D81 0 1 Down Split disabled Down Split enabled Startup configuration
6.1.8
Fractional spurious compensation
Table 26.
D80 0 1 DAC OFF DAC ON Startup configuration
Fractional spurious compensation
Description Notes
Table 27.
D79 0
DAC current adjustment
D78 0 D77 1 D76 1 D75 1 N=7 Description Notes startup configuration
Table 28.
D74 0 .. 1
Down Asym delay setting
D73 0 .. 1 Maximum delay Description Minimum delay Notes Startup configuration
29/38
Programming specifications
STA011
6.2
6.2.1
RF path
Blocks enable
Table 29. Blocks enable
Description D71 0 1 D70 0 1 D67 0 1 Buffer OFF Buffer ON Startup configuration Mixer OFF Mixer ON Startup configuration LNA OFF LNA ON Startup configuration Notes
6.2.2
RF gain setting
Table 30.
D69 1 1 0 0
RF gain setting
D68 1 0 1 0 High Gain Medium1 Medium2 Low Gain Startup configuration Description Notes
6.2.3
IF buffer setting
Table 31.
D66 0 1 Itail=3mA Itail=4mA
IF Buffer setting
Description lower output linearity Higher output linearity, startup configuartion Notes
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STA011
Programming specifications
6.3
6.3.1
IF path
Blocks disable
Table 32.
D65 D65 0 1 D64 0 1 D63 0 1 D62 0 1 D61 0 1 IF2Amp OFF IF2Amp ON Startup configuration Mixer OFF Mixer ON Startup configuration VGA2 OFF VGA2 ON Startup configuration VGA1 OFF VGA1 ON Startup configuration preVGA OFF preVGA ON Startup configuration
Blocks disable
Description Notes
6.4
Lock detector setting
Table 33.
D60 0 0 1 x x
Lock detector setting
D59 0 0 0 1 1 D58 0 1 0 0 1 Description Lock test on RF PLL Lock test on IF PLL Lock test on RF PLL and IF PLL Test on RF PLL dividers Test on IF PLL dividers Notes Test condition Test condition Startup configuration Test condition Test condition
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Programming specifications
STA011
6.5
6.5.1
IF PLL
IFVCO enable
Table 34.
D57 1 1
IFVCO enable
D56 0 1 Description Internal IFVCO External IFLO Notes Startup configuration Test condition
6.5.2
PFD programming
Table 35.
D55 x x x 0 0 1 1 D54 x x x 0 1 0 1
Frequency phase detector setting
D53 1 1 1 0 0 0 0 D52 x 0 1 x x x x D51 1 0 0 x x x x Description Normal operation Reference divider test, available @Lock Loop divider test available @ Lock Notes Default configuration Synthesizer test reserved configuration Synthesizer test reserved configuration
Charge pump test, high impedance Synthesizer test state reserved configuration Charge pump test, DEC active Charge pump test, INC active Charge pump test, DEC&INC active Synthesizer test reserved configuration Synthesizer test reserved configuration Synthesizer test reserved configuration
6.5.3
Charge pump enable
Table 36.
D50 0 1
Charge pump enable
Description Charge Pump OFF Charge Pump ON Startup configuration Notes
6.5.4
Reference divider division ratio
Table 37.
D49 0 D48 1
Reference divider division ratio
D47 0 D46 0 D45 0 D44 0 D43 0 D42 1 D41 0 Description R=130 Notes fcomp=113.23KHz startup configuration
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STA011
Programming specifications
6.5.5
Table 38.
D40 ... 0 ... 1 ... 1 ... D39 ... 1 ... 0 ... 0 ...
Loop divider division ratio
Loop divider division ratio
D38 ... 1 ... 0 ... 0 ... D37 ... 1 ... 0 ... 0 ... D36 ... 1 ... 0 ... 0 ... D35 ... 0 ... 0 ... 1 ... D34 ... 1 ... 0 ... 1 ... D33 ... 1 ... 1 ... 1 ... D32 ... 0 ... 0 ... 0 ... D31 ... 1 ... 1 ... 0 ... D30 ... 1 ... 0 ... 1 ... N=1081 N=1034 Startup configuration N=987 Description Notes
6.6
XTAL
Table 39. XTAL
Description D29 0 1 D28 0 1 M_CLK double ended output M_CLK single ended output Cut-off frequency setting D27 0 0 1 1 D25 0 1 open loop gain set low open loop gain set high Startup configuration D26 0 1 0 1 Maximum cut-off frequency Intermediate 1 Intermediate 2 Minimum cut-off frequency Startup configuration Startup configuration M_CLK output buffer ON M_CLK output buffer OFF Startup configuration Notes
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Programming specifications
STA011
6.7
Startup configuration
Table 40. Startup configuration
Binary 00101110 00010100 00100111 10001011 00101011 00111000 11101111 11110010 00101101 00000101 00000010 10001010 Dec Value 46 20 39 139 43 80 239 242 45 5 2 140 Data Byte 1 2 3 4 5 6 7 8 9 10 11 12
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7
STA011
VREG
1 2 J1 VP3 3 2 1
AGC ctrl Ext IF LO
2
Ban2m m
1
1
1
SW1 Se Pri m2 c ct n/u Se Pri m c R7 CE 100K 3 3 3 R2 0 6 5 4 C33 tbd tbd C50 C58 C15 2 10nF 27pF 1uF 10nF 10nF 1 D1 J5 C22 10uF C4 C51 TP1 TP2 10nF R12 tbd 10nF C36 C52 R15 0 ohm tbd R16 100nF C41 CAP 0 ohm C23 10uF C5 100nF tbd C21 10uF C9 TP5 C53 10nF C54 10nF R14 tbd TP4 C37 tbd R18 R17 0 ohm C44 nc 0 ohm C24 10uF C10 C42 Y1 14.72MHz C43 C18 U9 LDB182G72 18pF 4 3 2 1 C8 100nF 1 2 D2 3 R11 tb d 10nF C56 27pF C59 J8 Ext RF LO 1uF C19 C45 tbd R27 51 C38 tbd C61 C55 C25 R21 51ohm R23 1K R24 1K U10 1nF 10nF 10uF AD8009 nc VsOut I N + Vs+ I N nc nc 100nF +5V 1 7 6 5 R20 51 oh m InI n+ Vs- Vs+ PD Out Re f FB U8 AD8130 +5V 1 7 6 5 U6 VN4 SOP SON VN4 AGC2 AGC1 VP4 NTK2 TK 2 VP4 FLT2 10nF TP 6 R19 3 fltIF_Test C2 100nF tbd R9 C39 EnRfOsc 2 2 2 A ddr
U2 ADT2-1T-1P
CE
EnRFOsc
Add r
1 XOsel 2 XOsel 3
U1 11 Vin 4 C1 Gnd 3 100nF C20 Vout LF30ABDT 10uF
VP1
2 R8 100K C3 100nF U3 C48 6 2 4 C46 J3 ADT1-1WT 3 5 1 Pri m Sec nu ct Prim2 Sec
1
R28
Ban2mm
0
VP1
C11
C27
1uF nc
R1 0
VP2a
2
1
R31
Ba n2mm
VP2a
0
C12
C29
1IF In
Evaluation board
1uF nc
R5 0
VP2b
U5 RF Out J4 ADT4-1WT 10nF C47 1 2 3 Prim Sec n/ u ct Prim2 Sec 6 5 4 C49 TP 7
2
1
R29
0
C13
C30
1uF nc
44 43 42 41 40 39 38VP4b 37 36 35VP4a 34
Ban2mm
VP2b
RX Out
U7 AD8130 InI n+ Vs- Vs+ PD Out Re f FB 51 oh m J6
R3 0
VP3
U4 C34 tbd L1 C35 tbd 1 2 3 RF Balun gnd ba l unbal gnd gnd ba l 4 5 6
2
1
R30
Figure 11. Evaluation board schematic
Ban2mm
0
C14
VP3
C28
1uF nc
R4 0 LDB31
STA011
R10 L2 tbd tbd C40
J2
VP4a
VP2 TK 1 NTK1 VP2 FLT1 VN2 XT AL 1 XT AL 2 REF XOsel TL ck
2
1
R33
Ba n2m m VP2a STA011
0
C17
C32
VP4a
VP1 1 2 3 4 5 6 tbd 7 Addr 8 R13 tbd 9 10 EnRfOsc 11 VP1 SIP SIN VN1 LNI NLN1 VN1 Addre ss PADJ1 PADJ2 ENRFOSC RXI NRXI GADJ2 GADJ1 CE VP3 SCL SDA VN3 M_Clk1 M_Clk2 33 32 31 30 29 CE 28 VP3 27 SCL 26 SDA 25 24 23
8 2 3 4 -5V
RF in
MClk J7
R6 0 12 13 14 VP2b 15 16 17 18 19 20 21 22 XOsel
1uF nc
VP4b
Ba n2m m
0
C16
VP4b
C31
8 2 3 4
2
1
R32
D4 -5V TP3 LED 100nF D3 3 1 2 Q1 BSN20 gsd R22 300ohm +5V
1uF nc
Very close to fitting pin
VP4a VP4b C7 100nF VP2b C64 100pF 100pF C65 1 2 3 VP1 1nF 1uF C60 VP3 C6 Unbal bal n/c n/c Gnd bal 100nF 4 5 6 tbd
GND
2
1
Ba n2mm
GND1
C63 100pF
VP2a
2
1
Ba n2mm
-5V
+5V
5 6 7 8
C62 C57 C26 J1 0 Ext Ref 1nF 10nF 10 uF
R26 1K SCL SDA R251K
PROG 1 2
1
1
-5V
+5V
Ban2m m
Ban2m m
AC00415
J9 fltRF_Test
J1 1 TestDiv
2
2
Evaluation board
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Package information
STA011
8
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 12. TQFP44 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
0076922 D
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STA011
Revision history
9
Revision history
Table 41.
Date 21-Nov-2007
Document revision history
Revision 1 Initial release. Changes
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STA011
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