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HV7370 Quad, High Speed, 100V 850mA, Ultrasound Damper
Features
HVCMOS(R) technology for high performance High density integration ultrasound transmitter 0 to 100V open-drain voltage 850mA source and sink current Up to 20MHz operation frequency Matched delay times 1.8 to 5V CMOS logic interface
General Description
The Supertex HV7370 is a four-channel, monolithic high voltage, high-speed damper. It is designed for working with the HV738, HV748 or HV758 for medical ultrasound waveform generators requiring fast return-to-zero applications. The HV7370 consists of a controller logic interface circuit, level translators, MOSFET gate drives and high current power Pchannel and N-channel MOSFETs as the output stage for each channel. The output stages of each channel are designed to provide peak output currents of over 0.85A for damping to ground, with up to 100V swing. The control from inputs to outputs uses direct coupling topology, which not only saves components and PCB layout space, but also makes the damping frequency function down to DC.
Applications
Medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator
Block Diagram
+1.8 to 3.3V
+9.0V
+75V
VPP -9.0V
0 to +75V
C1 VLL OTP EN MC0 MC1 PIN1 (+Pulse) NIN1 (-Pulse)
EN_PWR
C2 VDD
C3 VSUB
SUB
C4 VPF VPP
C5
RGND RP1 P-Driver TXP1 D1 D2
Level Trans.
Level Trans.
Pulser
N-Driver RN1 Supertex HV748
1 of 4 Channels
TXN1 RGND
HVOUT1
GREF +1.8 to 3.3V Logic
VSS
VNF C7 VNN +9.0V
VNN C6 0 to -75V
+1.8 to 3.3V +9.0V
+9.0V -9.0V
C1
VLL
C2 VDD
C3
VSUB
SUB
C4
VDP
RGND
X1
EN
EN_PWR
Level Trans. IN1 (Damp)
P-Driver
PD1
D3 D4
Level Trans.
Damper
N-Driver
ND1
Supertex HV7370
1 of 4 Channels
VSS
VDN
RGND
C7
+9.0V
HV7370
Ordering Information
Package Option Device
5.00x5.00mm body 1.00mm height (max) 0.50mm pitch
32-Lead QFN
HV7370
-G indicates package is RoHS compliant (`Green')
HV7370K6-G
Absolute Maximum Ratings
Parameter VSS, power supply reference VLL, positive logic supply VDD, positive logic, level translator supply (RGND - VDP), P-Gate driver supply (VDN - RGND), N-Gate driver supply RGND, RTZ-Ground voltage All logic input PINX, NINX and EN voltages VSUB substrate voltage (NDX - RGND) damping N-MOSFET BVSUB voltage (PDX - RGND) damping P-MOSFET BVSUB voltage Maximum junction temperature Storage temperature Thermal resistance, JA Value 0V -0.5V to +7.0V -0.5V to +13V +0.5V to -13V -0.5V to +13V -2.0V to +2.0V -0.5V to +7.0V +120V +120V -120V +150C -65C to 150C 21.6C/W
Pin Configuration
32 1
32-Lead QFN (K6)
(top view)
Package Marking
HV7370 LLLLLL YYWW AAACCC
L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
32-Lead QFN (K6)
Power-Up Sequence of Pulser & Damper
Step 1 2 3 4 5 6 Description VSUB VLL with logic signal low VDD, VDN, and VDP (VPP- VPF) and (VNF- VNN) VPP and VNN Logic control signals
Power-Down Sequence of Pulser & Damper
Step 1 2 3 4 5 6 Description All logic control signals go to low VPP and VNN (VPP- VPF) and (VNF- VNN) VDD, VDN, and VDP VLL VSUB
2
HV7370
Operating Supply Voltages and Current (4 Channel Active)
Sym VLL VDD VDP VDN VSUB RGND ILL IDDQ IDDEN IDDEN IDPQ IDPEN IDNQ IDNEN Parameter Logic voltage reference Internal voltage supply P-Gate driver supply N-Gate drive supply IC substrate voltage RTZ-Ground voltage VLL Current EN = Low VDD Current EN = Low VDD Current EN = High VDD Current VDP Current EN = Low VDP Current VDN Current EN = Low VDN Current
1
(Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V VPP/VNN = 75V, TA = 25C)
Min 1.8 5.0 -12 5.0 5.0 -2.0 -
Typ 3.3 8.0 to 11 -VDD VDD VDD 0 35 10 1.5 6.0 50 30 50 12
Max 5.0 12 -5.0 12 100 +2.0 120 3.0 -
Units V V V V V V A A mA mA A mA A mA
Conditions ----Negative voltage supply Positive voltage supply --------f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads
Note: 1. P&N-FETs best matching when VDD = VDN = +10V, VPN = -10V
Under Voltage
Sym VUVDD VUVLL VUVVDN VUVVDP Parameter VDD threshold VLL threshold UV threshold for VDN UV threshold for VDP Min 2.0 1.0 3.5 1.75 Typ 3.7 1.25 4.25 4.5 Max 7.0 1.5 4.75 6.0 Units V V V V Conditions ------Typ VUVVDP -(VDN/2), [VDN = +9.0V]
Electrical Characteristics
Sym IOUT RON COSS IOUT RON COSS Parameter
(Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V, VPP/VNN = 75V, TA = 25C)
Output P-Channel MOSFET, PDx
Output saturation current Channel resistance Output capacitance Output saturation current Channel resistance Output capacitance
Min 0.6 0.6 -
Typ 0.85 13 50 0.85 12.5 20
Max -
Units A pF A pF
Conditions --ISD = 100mA VSUB = 25V, f = 1.0MHz --IDS = 100mA VSUB = 25V, f = 1.0MHz
Output N-Channel MOSFET, NDx
3
HV7370
Logic Inputs
Sym VIH VIL IIH IIL CIN Parameter Input logic high voltage Input logic low voltage Input logic high current Input logic low current Input logic capacitance Min (VLL -0.4) 0 -10 Typ 5 Max VLL 0.4 10 Units V V A A pF Conditions -----------
AC Electrical Characteristics
Sym trp tfn fOUT tEN tEN tdrp tdfp tdrn tdfn tDELAY tJ Parameter P-FET output rise time N-FET output fall time Output frequency range Enable time Disable time P-FET on delay time P-FET off delay time N-FET on delay time N-FET off delay time |tdr - tdf| delay time matching Delay time jitter, rise or fall
(Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V,VDD = VDN = +9V, VDP = -9V, VPP - VPF = +9V, VNN - VNF = -9V, VSUB = +75V VPP/VNN = 75V, TA = 25C)
Min -
Typ 26 26 180 2.8 19 17 19 17 3.0 15
Max 20 500 10 -
Units ns ns MHz s
Conditions 330pF//2.5k load --100 resistor load, +10V to NDX and -10V to PDX
ns
8.2 resistor load (see timing diagram)
ns ps
P to N, channel to channel VPP/VNN = 25V, input rising 50% to output PDX/NDX rising/falling 50%, with 100 load
4
HV7370
Switch Test Timing Diagram
PINx (Pulser)
NINx (Pulser)
INx (Damper)
0V
VLL
VPP
trp
Output
90%
VPP
10%
0V
90%
0V tfn
10%
VNN
VLL
VDD
VSUB
VDP
EN
SUB EN_PWR
Level Translator
P-Driver
PD1 ND1
IN1
Level Translator N-Driver
R1 R2 VNN VPP
1 of n Channels
GREF
VSS VDN
50%
50%
INx tdrn
INx tdfn
IOUT
50% NDx 0A
tdfp
tdrp
PDx
0A
50%
IOUT
5
HV7370
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VLL VSS IN1 IN2 IN3 IN4 VSS VDD NC VSUB VDP RGND RGND RGND VDN VSUB ND4 PD4 ND3 PD3 ND2 PD2 ND1 PD1 VSUB VDN RGND RGND RGND VDP VSUB EN P-FET drive floating power supply, (RGND - VDP) = +9.0V. Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. Chip power enable Hi = on, Low = off. Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB. VSUB normally is connected to VDD = +9.0V or +75V (pulser VSUB). Return ground. N-FET drive floating power supply, (VDN - RGND) = +9.0V. Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. Output damping N-FET drain (open drain output) for channel 4. Output damping P-FET drain (open drain output) for channel 4. Output damping N-FET drain (open drain output) for channel 3. Output damping P-FET drain (open drain output) for channel 3. Output damping N-FET drain (open drain output) for channel 2. Output damping P-FET drain (open drain output) for channel 2. Output damping N-FET drain (open drain output) for channel 1. Output damping P-FET drain (open drain output) for channel 1. Substrate of the damper HV7370, must VSUB = VDD , or VSUB of the pulser. N-FET drive floating power supply, (VDN - RGND) = +9.0V. Return ground. Description Logic Hi voltage reference input (+3.3V). Power supply return (0V). Input logic control of damping P&N-FET of channel 1, Hi = on, Low = off. Input logic control of damping P&N-FET of channel 2, Hi = on, Low = off. Input logic control of damping P&N-FET of channel 3, Hi = on, Low = off. Input logic control of damping P&N-FET of channel 4, Hi = on, Low = off. Power supply return (0V). Positive internal voltage supply (+9.0V). No connection. Substrate of the damper HV7370, must VSUB = VDD, or VSUB of the pulser. P-FET drive floating power supply, (RGND - VDP) = +9.0V.
Thermal Pad (VSUB)
Note: Thermal pad must be connected to VSUB.
6
HV7370
32-Lead QFN Package Outline (K6)
32
5.00x5.00mm body, 1.00mm height (max), 0.50mm pitch
D D2
32
Note 1 (Index Area D/2 x E/2)
1
1
Note 1 (Index Area D/2 x E/2)
e E b E2
View B
Top View
Bottom View
Note 3
A A1
A3
Seating Plane
Note 2
L L1
Side View
View B
Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.
Symbol Dimension (mm) MIN NOM MAX
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 4.85* 5.00 5.15*
D2 1.05 3.55
E 4.85* 5.00 5.15*
E2 1.05 3.55
e 0.50 BSC
L 0.30 0.50
L1 0.00 0.15
0O 14O
0.40
JEDEC Registration MO-220, Variation VHHD-6, Issue K, June 2006. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. This dimension is a non-JEDEC dimension. Drawings not to scale. Supertex Doc. #: DSPD-32QFNK65X5P050, Version A071408.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV7370 NR090508
7

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