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M66288FP
Description
262144-word x 8-bit x 3-FIFO MEMORY
REJ03F0156-0310 Rev. 03.10 Apr.4.2008
The M66288FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit configuration (2M-bit), which uses high-performance silicon gate CMOS process technology. One of three FIFO memories consists of two FIFO memories of 262144-word x 4-bit (1M-bit). Eight types of operation can be performed by mode settings.
Features
Memory configuration High - speed cycle High - speed access Output hold Supply voltage Variable length delay bit Eight modes can be selected Write and Read function can be operated completely independently and asynchronously Output type 3 state output Package 100pin 14x14mm body LQFP (PLQP0100KB-A, 100P6Q-A) Total memory capacity is 6M-bit (static memory). Eight types of memory configurations can be selected. 12.5 ns (Min.) fmax 80MHz 9.0 ns (Max.) 2.0 ns (Min.) Internal = 1.8 V 0.18 V, I/O = 3.3 V 0.3 V
Application
W-CDMA base station, Digital PPC, Digital television, VTR and so on.
Pin Configuration (Top view)
MODE1 MODE2 MODE3 RRESC RRESB RRESA VccIO VccIO RCKC RCKB RCKA GND GND GND REC QB7 QB6 QB5 QB4 QB3 QB2 QB1
52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VccIO GND Vcc18 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 GND VccIO DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 GND Vcc18 TEST1 TEST2
51
QB0
REB
REA
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9
50 49 48 47 46 45 44 43 42 41 40 39
GND Vcc18 GND VccIO QC7 QC6 QC5 QC4 QC3 QC2 QC1 QC0 GND VccIO DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 GND Vcc18 GND
M66288FP
38 37 36 35 34 33 32 31 30 29 28 27 26
WCKB
WRESB
WCKA
WRESA
WEB
WEA
WCKC
WRESC
VccIO
VccIO
WEC
TEST3
Vcc18
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 1 of 23
VccIO
GND
GND
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
M66288FP
Mode Descriptions Drawing
256K-word MODE 1
DA<7:0> WCKA WRESA WEA 8 256K-w x 8-bit FIFO 8 256K-w x 8-bit FIFO 8 QA<7:0> RCKA RRESA REA 8
1K-word = 1024-word
12-bit bus I/F MODE 3
QA<7:0> RCKA RRESA REA
DA<7:0> WCKA WRESA WEA 8 256K-w x 8-bit FIFO 8 QA<7:0> RCKA RRESA REA
8-bit bus I/F MODE 2
DA<7:0> WCKA WRESA WEA 8 256K-w x 8-bit FIFO 8
MODE 4
DA<11:0> WCKA WRESA WEA 12 256K-w x 12-bit FIFO 12 QA<11:0> RCKA RRESA REA
DA<11:0> WCKA WRESA WEA
MODE 5
12 256K-w x 12-bit FIFO 12 QA<11:0> RCKA RRESA REA
DB<7:0> WCKB WRESB WEB
QB<7:0> RCKB RRESB REB
8
256K-w x 8-bit FIFO
8
QB<7:0>
8
256K-w x 8-bit FIFO
8
QB<7:0>
DB<11:0> WCKB
8 256K-w x 8-bit FIFO 8
12 256K-w x 12-bit FIFO
12
QB<11:0> RCKB RRESB REB
12
DC<7:0> WCKC WRESC WEC
8 256K-w x 8-bit FIFO
8
QC<7:0> RCKC RRESC REC
8
256K-w x 8-bit FIFO
8
DC<7:0>
QC<7:0> RCKC RRESC REC
WRESB WEB
256K-w 12 x 12-bit FIFO
QB<11:0>
QC<7:0>
WCKC WRESC WEC
The three pieces of 256K-word x 8-bit FIFO can be operated completely independently. 3-system individual input 3-system individual output
The three pieces of 256K-word x 8-bit FIFO are cascade-connected. (Note 1) 1-system input The simultaneous output of the 1, 2, 3 line delay data.
The two pieces of 256K-word x 8-bit FIFO are cascade-connected and, a piece of 256K-word x 8-bit FIFO can be operated completely independently. (Note 1) (1) 1-system input (2) 1-system input (1) The simultaneous output of the 1, 2 line delay data. (2) 1-system output
The two pieces of 256K-word x 12-bit FIFO can be operated completely independently. (Note 2) 2-system individual input. 2-system individual output.
The two pieces of 256K-word x 12-bit FIFO are cascade-connected (Note 1, Note 2) 1-system input The simultaneous output of the 1, 2 line delay data.
768K-word MODE 6
DA<7:0> WCKA WRESA WEA 8 768K-w x 8-bit FIFO 8
512K-word & 256K-word 8-bit bus I/F MODE 7
QA<7:0> RCKA RRESA REA DA<7:0> WCKA WRESA WEA 8 512K-w x 8-bit FIFO 8 QA<7:0> RCKA RRESA REA DA<11:0> WCKA WRESA WEA
512K-word 12-bit bus I/F MODE 8
12 512K-w x 12-bit FIFO 12 QA<11:0> RCKA RRESA REA
DC<7:0> WCKC WRESC WEC
8 256K-w x 8-bit FIFO
8
QC<7:0> RCKC RRESC REC
A piece of 768K-word x 8-bit FIFO can be operated completely independently. 1-system input 1-system output
A piece of 512K-word x 8-bit FIFO and a piece of 256K-word x 8-bit FIFO can be operated completely independently. 2-system individual input 2-system individual output
A piece of 512K-word x 12-bit FIFO can be operated completely independently. (Note 2) 1-system input 1-system output
Note1: Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line FIFO. Maximum number of words on this mode is 256K-word. Line delay is achieved without outer connection. Note2: Please refer to pin assignment tables in "Operation Description" of Mode 4, Mode 5, and Mode 8 for assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 2 of 23
M66288FP
Block Diagram
Data input DA<7:0>
DB<7:0>
DC<7:0>
INPUT BUFFER
Mode setting Mode setting input input MODE<3:1> MODE<3:1> Write control inputs for A-system WRITE CONTROL CIRCUIT
MODE CONTROL CIRCUIT
Read control inputs for A-system READ CONTROL CIRCUIT RCKA RRESA REA Read control inputs for B-system RCKB RRESB REB Read control inputs for C-system RCKC RRESC REC
WRITE ADDRESS COUNTER
WCKA WRESA WEA Write control inputs for B-system WCKB WRESB WEB Write control inputs for C-system WCKC WRESC WEC Test setting input Test setting input TEST<3:1> TEST<3:1> VCC 18 Vcc18 GND
MEMORY ARRAY
256K-WORD x 8-BIT 256K-word x 8bit READ ADDRESS COUNTER
256K-word x 4bit 256K-WORD x 4-BIT 256K-word x 4bit 256K-WORD x 4-BIT 256K-word x 8bit 256K-WORD x 8-BIT
MODE CONTROL CIRCUIT
OUTPUT BUFFER
VccIO VCC IO
GND
Data output Data output QA<7:0> QA<7:0>
QB<7:0>
QB<7:0>
QC<7:0>
QC<7:0>
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 3 of 23
M66288FP
Pin Function Descriptions
Pin name WCK x Name Write clock input Input / Output Input Number of pins 3 Function They are write clock inputs.
WE x
Write enable input
Input
3
They are write enable control inputs. When they are "L", a write enable status is provided. They are write reset inputs to initialize a write address counter of internal FIFO. When they are "L", a write reset status is provided. They are read clock inputs.
WRES x
Write reset input
Input
3
RCK x
Read clock input
Input
3
RE x
Read enable input
Input
3
They are read enable control inputs. When they are "L", a read enable status is provided. They are read reset inputs to initialize a read address counter of internal FIFO. When they are "L", a read reset status is provided. They are 8-bit input data bus.
RRES x
Read reset input
Input
3
Dx <7:0>
Data input
Input
24
Qx <7:0>
Data output
Output
24
They are 8-bit output data bus.
MODE<3:1>
Mode setting input
Input
3
They are operation mode setting inputs. For setting, refer to Mode setting table of Page5. They are test setting inputs. Setting of TEST1 depends on the rising time of the 1.8 V system power supply. For further details, refer to page 12. TEST2 and TEST3 should be fixed at "L". This is a 3.3 V power supply pin for I/O. This is a 1.8 V power supply pin for internal circuit. This is a ground pin.
TEST<3:1>
Test setting input
Input
3
VccIO Vcc18 GND
Power supply pin for I/O Power supply pin for internal circuit Ground pin
-
9 5 14
Note: X of the pin name shows A, B and C. A = A-system, B = B-system, C = C-system.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 4 of 23
M66288FP
Mode Setting
MODE<3:1> should be set to "L" or "H" as shown below to select the 8 operation modes. MODE 3 L L L L H H H H MODE 2 L L H H L L H H MODE 1 L H L H L H L H Operation mode MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 MODE 8
Mode1 Operation Description

DA<7:0> WCKA WRESA WEA
8 8
256K-w x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 1, three pieces of 256K-word x 8-bit FIFO can be controlled completely independently. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) and FIFO (C) are the same as that of FIFO (A).
DB<7:0> WCKB WRESB WEB
8
8
256K-w x 8-bit FIFO(B)
QB<7:0> RCKB RRESB REB
When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address
DC<7:0> WCKC WRESC WEC
8
8
256K-w x 8-bit FIFO(C)
QC<7:0> RCKC RRESC REC
counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", this IC disable to read data from FIFO (A) and the read address counter of FIFO (A) is not incremented. Also QA<7:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 5 of 23
M66288FP
Mode2 Operation Description
In mode 2, three pieces of 256K-word x 8-bit FIFO are cascade-connected and it is possible to generate delay data for 3-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of all FIFOs are incremented. Also the data of the upper FIFO is written into the lower FIFO in synchronization with the rising of RCKA. At this time, the write address counters of FIFO (B) and FIFO (C) are incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A), FIFO (B) and FIFO (C) and the read address counter of each FIFO is not incremented. All data outputs become high impedance state. And this IC also disable to write data into FIFO (B) and FIFO (C) and the write address counter of FIFO (B) and FIFO (C) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write/read address counters of FIFO (B) and FIFO (C) are initialized. In mode 2, only all pins for the A-system, QB<7:0> and QC<7:0> are used. Therefore, the write/read control pins for the B/C-system, DB<7:0> and DC<7:0> should be fixed at "L" or "H".
Note: Write and read operation of FIFO (B) and FIFO (C) after the 2nd line is controlled by the read system pin of the 1st line FIFO (A). Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 6 of 23
M66288FP
Mode3 Operation Description

DA<7:0> WCKA WRESA WEA
8 8
256K-w x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 3, two pieces of 256K-word x 8-bit FIFO are cascade-connected and the other FIFO is configured completely independently. This makes it possible to generate delay data for 2-lines without external wiring and to control the other independent one FIFO memory.
8
8
256K-w x 8-bit FIFO(B)
QB<7:0>
When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0> and QB<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented. Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B) and the read address counter of each FIFO is not incremented. QA<7:0> and QB<7:0> become high impedance state. And this IC also disable to write data into FIFO (B) and the write address counter of FIFO (B) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write/read address counter of FIFO (B) are initialized. The operation of FIFO (C) is the same as that of mode 1. In mode 3, only all pins for the A/C-system and QB<7:0> are used. Therefore the write/read control pins for the B-system and DB<7:0> should be fixed at "L" or "H".
DC<7:0> WCKC WRESC WEC
8
8
256K-w x 8-bit FIFO(C)
QC<7:0> RCKC RRESC REC
Note: Write and read operation of FIFO (B) at the 2nd line is controlled by the read system pin of the 1st line FIFO (A). Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 7 of 23
M66288FP
Mode4 Operation Description

DA<7:0> DB<3:0> WCKA WRESA WEA
12 12
256K-w x 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA REA
In mode 4, two pieces of 256K-word x 12-bit FIFO can be controlled completely independently. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) is the same as that of FIFO (A). When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock
DC<7:0> DB<7:4> WCKB WRESB WEB
12
12
256K-w x 12-bit FIFO(B)
QC<7:0> QB<7:4> RCKB RRESB REB
input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO(A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> and QB<3:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", this IC disable to read data from FIFO (A) and the read address counter of FIFO (A) is not incremented. Also QA<7:0> and QB<3:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 4, only all pins for the A/B-system, DC<7:0> and QC<7:0> are used. Therefore the write/read control pins for the C-system should be fixed at "L" or "H".
External pin Data input name bus of FIFO (A) DA<7> 11th-bit th DA<6> 10 -bit th DA<5> 9 -bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit
External pin Data output name bus of FIFO (A) QA<7> 11th-bit th QA<6> 10 -bit th QA<5> 9 -bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit
External pin Data input name bus of FIFO (B) DC<7> 11th-bit th DC<6> 10 -bit th DC<5> 9 -bit DC<4> 8th-bit DC<3> 7th-bit DC<2> 6th-bit DC<1> 5th-bit DC<0> 4th-bit DB<7> 3rd-bit DB<6> 2nd-bit DB<5> 1st-bit DB<4> 0th-bit
External pin Data output Name bus of FIFO (B) QC<7> 11th-bit th QC<6> 10 -bit th QC<5> 9 -bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 8 of 23
M66288FP
Mode5 Operation Description
In mode 5, two pieces of 256K-word x 12-bit FIFO are cascade-connected and it is possible to generate delay data for 2-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0>, QB<3:0> and QC<7:0>,QB<7:4> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented. Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B) and the read address counter of each FIFO is not incremented. Also all data outputs become high impedance state. And this IC also disable to write data into FIFO (B) and the write address counter of FIFO (B) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write /read address counter of FIFO (B) are initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 5, only all pins for the A-system, DB<3:0>, QB<7:0> and QC<7:0> are used. Therefore the write/read control pins for the B/C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H". External pin Data input Name bus of FIFO (A) DA<7> 11th-bit DA<6> 10th-bit DA<5> 9th-bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit External pin Data output name bus of FIFO (A) QA<7> 11th-bit QA<6> 10th-bit QA<5> 9th-bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit External pin Data output Name bus of FIFO (B) QC<7> 11th-bit QC<6> 10th-bit QC<5> 9th-bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit
DA<7:0> DB<3:0> WCKA WRESA WEA
12
12
256K-w x 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA REA
12
12
256K-w x 12-bit FIFO(B)
QC<7:0> QB<7:4>
Note: Write and read operation of FIFO(B) at the 2nd line is controlled by the read system pin of the 1st line FIFO(A). Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 9 of 23
M66288FP
Mode6 Operation Description
In mode 6, one FIFO memory of the 768K-word x 8-bit composition can be
DA<7:0> WCKA WRESA WEA
8 8
controlled.
QA<7:0> RCKA RRESA REA
768K-w x 8-bit FIFO(A)
The operation of FIFO (A) is the same as that of mode 1. In mode 6, only all pins for the A-system are used. Therefore, the all input pins for the B/C-system should be fixed at "L" or "H". Also QB<7:0> and QC<7:0> become high impedance state.
Mode7 Operation Description

DA<7:0> WCKA WRESA WEA
8 8
512K-w x 8-bit FIFO(A)
QA<7:0> RCKA RRESA REA
In mode 7, one of 512K-word x 8-bit FIFO and one of 256K-word x 8-bit FIFO memory can be controlled completely independently. The operation of FIFO (A) and FIFO (B) are the same as that of mode 1. In mode 7, only all pins for the A/C-system are used. Therefore, the all input pins for the B-system should be fixed at "L" or "H".
DC<7:0> WCKC WRESC WEC
8
8
Also QB<7:0> become high impedance state.
QC<7:0> RCKC RRESC REC
256K-w x 8-bit FIFO(B)
Mode8 Operation Description

DA<7:0> DB<3:0> WCKA WRESA WEA
12 12
512K-w x 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA REA
In mode 8, one FIFO memory of the 512K-word x 12-bit composition can be controlled. The operation of FIFO (A) is the same as that of mode 4. Also, please set the 12-bit I/O buses of FIFO (A) as mentioned in the table of mode 4 FIFO (A). In mode 8, only all pins for the A-system, DB<3:0> and QB<3:0> are used. Therefore, the write/read control pins for the B/C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H". Also QB<7:4> and QC<7:0> become high impedance state.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 10 of 23
M66288FP
Electrical Characteristics
Absolute Maximum Ratings
Symbol VCC18 VCCIO VI VO Pd Tstg
(Ta = 0 ~ 70C, unless otherwise noted)
Parameter Supply voltage (1.8 V power supply ) Supply voltage (3.3 V power supply ) Input voltage Output voltage Maximum power dissipation Storage temperature
Conditions A value based on GND
Ratings -0.3~+2.5 -0.3~+3.8 -0.3~VCCIO+0.3 -0.3~VCCIO+0.3 800 -55~150
Unit V V V V mW C
Ta = 70 C
Recommended Operating Conditions
Symbol VCC18 VCCIO Topr Parameter Supply voltage for internal circuit (1.8 V power supply ) Supply voltage for I/O (3.3 V power supply ) Operating ambient temperature Test conditions A value based on GND Min. 1.62 3.0 0 Limits Typ. 1.8 3.3 Unit Max. 1.98 3.6 70 V V C
DC Characteristics (Ta = 0 ~ 70C, Vcc18 = 1.8 0.18 V, VccIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC18 ICCIO Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current "L" input current Off state "H" output current Off state "L" output current Average operating supply current (1.8 V) Average operating supply current (3.3 V) Input capacitance Off state output capacitance IOH = -4mA IOL = 4mA VI = VCCIO VI = GND VO = VCCIO VO = GND VCC18 = 1.8 V 0.18 V VCCIO = 3.3 V 0.3 V VI = repeat "H" and "L" VO= Output open tWCK = tRCK = 12.5 ns f = 1 MHz f = 1 MHz VccIO - 0.4 0.4 10 -10 10 -10 180 120 Test conditions A value based on GND Min. 0.8 x VccIO Limits Typ. Unit Max. V 0.2 x VccIO V V V A A A A mA mA
CI CO
10 15
pF pF
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 11 of 23
M66288FP
Power - on
After power-on, this IC initializes some circuits of internal FIFO (1.8 V), using the built-in power-on reset circuit. This power-on reset is performed by using the VCC18 = 1.8 V system power supply. Either of the following conditions (1) or (2) should be met according to the power-on time of the VCC18. (1) When the power-on time of the VCC18 is 1 msec or less: Some circuits of internal FIFO are initialized by the built-in power-on reset circuit. No restriction is imposed on the power-on sequence between VCC18 and VCCIO = 3.3 V system power supply. When powering on again after power-on, provide an interval of 100 ms or more for the VCC18. At this time, the TEST1 (pin 99) pin should be fixed at "L".
1ms(max)
100ms(min)
VCC18 Vcc18
GND
Vcc18 VCC18 Vcc18 X 10% VCC18 x 10%
Vcc18 X 10% VCC18 x 10%
(2) When the power-on time of the VCC18 is more than 1 msec: Some circuits of internal FIFO should be initialized by the TEST1 (pin 99) pin. Input an initialize reset pulse of 200 ns or more after the power supplies (VCCIO, VCC18) reach to the VCC level. There is no problem even if reaching to the VCC level on which power supply.
3.0V~3.6V 3.0V~3.6V
VCCIO VccIO
VCCIO VccIO
GND
1ms or more 1.62V~1.98V
Vcc18 VCC18
GND
VCC18 Vcc18
200ns(min)
200ns(min)
VCCIO VccIO
TEST1
GND
Note: Some circuits of internal FIFO can be initialized by the TEST1 pin even if the power-on time of the Vcc18 is 1 msec or less.
Note: Important matter; Provide write reset cycles and read reset cycles of 100 cycles or more, respectively after the Vcc reaches to the specified voltage after power-on. When inputting a reset pulse using the TEST1 (pin 99) pin, provide write reset cycles and read reset cycles of 100 cycles or more, respectively after inputting a reset pulse at power-on. There is no problem in this reset operation if a total of 100 cycles or more is achieved, even if discontinuous reset input is made.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 12 of 23
M66288FP
Timing Requirements
(Ta = 0 ~ 70C, Vcc18 = 1.8 0.18 V, VccIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol t WCK t WCKH t WCKL t RCK t RCKH t RCKL t DS t DH t RESS t RESH t NRESS t NRESH t WES t WEH t NWES t NWEH t RES t REH t NRES t NREH t r, t f Write clock (WCK) cycle
Parameter Min. 12.5 5 5 12.5 5 5 3.5 1 3.5 1 3.5 1 3.5 1 3.5 1 3.5 1 3.5 1 Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset non-select setup time to WCK or RCK Reset non-select hold time to WCK or RCK Write enable setup time to WCK Write enable hold time to WCK Write enable non-select setup time to WCK Write enable non-select hold time to WCK Read enable setup time to RCK Read enable hold time to RCK Read enable non-select setup time to RCK Read enable non-select hold time to RCK Input pulse rise / fall time
Limits Typ. Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 ns
Switching Characteristics
(Ta = 0 ~ 70C, Vcc18 = 1.8 0.18 V, VccIO = 3.3 0.3 V, GND = 0 V, unless otherwise noted)
Symbol t AC t OH t OEN t ODIS Output access time to RCK Output hold time to RCK
Parameter Min. 2 2 2
Limits Typ. Max. 9 9 9
Unit ns ns ns ns
Output enable time to RCK Output disable time to RCK
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 13 of 23
M66288FP
Switching Characteristics Measurement Circuit
Vcc IO RL = 1 K SW1 Qn Qn SW2 CL = 10 pF: tAC, tOH RL = 1 K CL = 3 pF: tOEN, tODIS
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Input pulse level Decision voltage input : 0 ~ VCCIO : 1/2 VCCIO of that for decision).
SW1 Close Open Close Open Open Close Open Close
SW2
Input pulse rise/fall time : 1 ns Decision voltage output : 1/2 VCCIO (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
tODIS and tOEN Measurement Condition
VIH
RCK
1/2 VccIO
1/2 VccIO VIL
VIH
RE
VIL tODIS(HZ) 90% tOEN(ZH) VOH 1/2 VccIO
Qn
tODIS(LZ) tOEN(ZL)
Qn
1/2 VccIO 10% VOL
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 14 of 23
M66288FP
Operating Timing
Write Cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK tWCK WE tDS tDH Dn tDS tDH tWCKH tWCKL tWEH tNWES tNWEH tWES
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
Write Reset Cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
WCK tWCK WRES tNRESH tRESS tRESH tNRESS
tDS tDH Dn (n-1)
tDS tDH (n) (0) (1)
In case of WE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 15 of 23
M66288FP
Combination Cycle of Write Reset and Write Enable
n cycle
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE tNRESH tRESS tRESH tNRESS WRES tDS tDH Dn (n) (n+1) tDS tDH (n+2) (0) (1)
Note: There are no restrictions of WE to WRES.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 16 of 23
M66288FP
Read Cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES
RE tAC Qn (n) tOH (n+1) (n+2) tOH RRES = "H" tODIS HIGH-Z tOEN (n+3) (n+4)
Read Reset Cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
RCK tRCK RRES tNRESH tRESS tRESH tNRESS
tAC Qn (n-1)
tAC (n) tOH
tAC (0) tOH In case of RE = "L" (1)
tOH
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 17 of 23
M66288FP
Combination Cycle of Read Reset and Read Enable
n cycle
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
RCK tRCK RE tNRESH tRESS tRESH tNRESS tRCKH tRCKL tREH tNRES tNREH tRES
RRES tAC Qn (n) tOH (n+1) tAC (n+2) tOH tODIS
HIGH-Z
tOEN (0)
tAC (1)
tOH
Note: There are no restrictions of RE to RRES.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 18 of 23
M66288FP
Attentions when Write Cycle and Read Cycle Approach Each Other
The interval m of 16 cycles or more between a write cycle and a read cycle should be secured, when the write cycle goes ahead of the read cycle on the following conditions, that is to say the interval less than 15 cycles is forbidden. WRES, RRES="H"; WE, RE="L", and Both write side and read side are activated continuously Either write side or read side is temporarily stopped owing to the stop of WCK or RCK When this restriction to the interval is broken on these conditions, writing data is guaranteed, but reading data isn't guaranteed not only during breaking it but also during the following 16 cycles after it is applied. In this 16 cycles, read disable and read reset cycles are not counted. But the following condition is an exception to restrict to forbid the intervals less than 15 cycles. Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles (WE or RE ="H")
Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the interval m of 16 cycles or more between a write and read cycles should be secured, taking account that they are cyclic and serial lines.
n+16 cycle n+17 cycle
Write disable cycle
n+18 cycle n+19 cycle n+20 cycle n+21 cycle
n+22 cycle n+23 cycle
WCK WE Dn
( n+16 ) ( n+17 ) ( n+18 ) ( n+19 ) ( n+20 ) ( n+21 ) ( n+22 ) ( n+23 )
m15; WRES,RRES=H; "m", the interval between a write cycle and a read cycle WE,RE=L
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
n+5 cycle
n+6 cycle
n+7 cycle
Read disable cycle
RCK RE Qn
(n) ( n+1 ) ( n+2 ) ( n+3 ) HIGH-Z invalid invalid
read data are defined owing to write disable cycle.
read data of forbidden cycles are undefined.
read data of 16 cycles after forbidden cycles are undefined.
The conditions that the read cycle goes ahead of the write cycle or that write cycle and read cycle are accordant, are exceptions to the restriction to forbid the intervals less than 15cycles.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 19 of 23
M66288FP
Variable Length Delay Bits
The 1-line length (cycle number) of each mode is shown in the table. Operation MODE 1-line length MODE 1 - MODE 5 262144-cycle MODE 6 786432-cycle MODE 7 524288-cycle (A-system), 262144-cycle (C-system) MODE 8 524288-cycle The following, the case of the MODE 1 - MODE 5 (1-line length = 262144-cycle) is explained to an example.
1-line (262144-bit) Delay
In read cycles, an output data is read at the (first) rising edge of RCK (i.e. the start of the cycle ) . In write cycles, an input data is written at the (second) rising edge of WCK (i.e. the end of the cycle ) . So 1-line delay can be made easily according to the control method of the following figure.
Reset cycle 0 cycle 1 cycle 2 cycle 262142 cycle 262143 cycle 262144 cycle (0') 262145 cycle (1') 262146 cycle (2')
WCK RCK tRESS tRESH WRES RRES tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(262141)
(262142)
(262143)
(0')
(1')
(2')
262144 cycle
tAC
tOH
Qn
(0)
(1)
(2)
WE, RE = "L"
N-bit Delay 1
(Reset at a cycle corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n cycle Reset cycle 0 cycle (0') 1 cycle (1') 2 cycle (2')
WCK RCK tRESS tRESH WRES RRES tDS tDH tDS tDH tRESS tRESH
Dn
(0)
(1)
(2)
(n-1)
(n)
(0')
(1')
(2')
Delay length n Qn
tAC
tOH
(0)
(1)
(2)
262144 n 16 WE, RE = "L"
Note: The interval of 16 cycles or more between a write cycle and a read cycle should be secured to read data written in a certain cycle.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 20 of 23
M66288FP
N-bit Delay 2
(Sliding timings of WRES and RRES at a cycle corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle Reset cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle
*****Write side *****Read side
WCK RCK tRESS tRESH WRES tRESS tRESH RRES Dn tDS tDH
(0) (1) (2) (n-2) (n-1)
tDS tDH
(n) (n+1) (n+2) (n+3)
Delay length n Qn
tAC
tOH
(0) (1) (2) (3)
262144 n 16 WE, RE = "L"
N-bit Delay 3
(Sliding address by disabling RE at a cycle corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle
*****Write side *****Read side
WCK RCK tRESS tRESH WRES RRES RE tDS tDH Dn
(0) (1) (2) (n-2) (n-1)
tNREH tRES
tDS tDH
(n) (n+1) (n+2) (n+3)
Delay length n Qn HIGH-Z
tAC
tOH
(0) (1) (2) (3)
262144 n 16 WE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 21 of 23
M66288FP
Shortest Reading of Written Data in N Cycle when Write and Read Operated Asynchronously
The interval of 16 cycles or more between a write cycle and a read cycle should be secured and WCK and RCK should be inputted for 16 cycles or more based on beginning of write n cycle at any timing to read written data (data fetched at the rising edge of WCK shown *1 in the following figure) with n cycles on write side. On read side, n cycles should be started after the completion of n+15 cycles on write side (t 0 in the following figure). Output data becomes undefined when these restrictions are not filled.
Reference
16 cycles or more are required in WCK. n-1 cycle n cycle n+1 cycle n+14 cycle n+15 cycle n+16 cycle n+17 cycle n+18 cycle n+19 cycle
WCK
*1
Dn
(n-1)
(n)
(n+1)
(n+14)
(n+15)
(n+16)
(n+17)
(n+18)
(n+19)
16 cycles or more are required in RCK.
t0
n cycle n+1 cycle
n-1 cycle
RCK
Qn
invalid
(n)
(n+1)
Longest Reading of Written Data in N Cycle: 1-line Delay
Data output Qn of n cycle <1>* can be read immediately before until the start of n cycle <1>* on read side and the start of n cycle <2>* on write side over lap each other.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 22 of 23
M66288FP
PACKAGE OUTLINE
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REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 23 of 23

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