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| VNQ600P-E QUAD CHANNEL HIGH SIDE DRIVER Table 1. General Features TYPE VNQ600P-E (*) Per each channel Figure 1. Package Ilim 25A VCC 36 V RDS(on) (*) 35m DC SHORT CIRCUIT CURRENT: 22A s CMOS COMPATIBLE INPUTS s PROPORTIONAL LOAD CURRENT SENSE s UNDERVOLTAGE & OVERVOLTAGE SHUT-DOWN s OVERVOLTAGE CLAMP s THERMAL SHUT-DOWN s CURRENT LIMITATION s VERY LOW STAND-BY POWER DISSIPATION s PROTECTION AGAINST: LOSS OF GROUND & LOSS OF VCC s REVERSE BATTERY PROTECTION (**) s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE s SO-28 (DOUBLE ISLAND) DESCRIPTION The VNQ600P-E is a quad HSD formed by assembling two VND600-E chips in the same SO28 package. The VND600-E is a monolithic device designed in| STMicroelectronics VIPower M0-3 Technology. The VNQ600P-E is intended for driving any type of multiple loads with one side connected to ground. This device has four independent channels and four analog sense outputs which deliver currents proportional to the outputs currents. Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection. Table 2. Order Codes Package SO-28 Note: (**) See application schematic at page 11. Tube VNQ600P-E Tape and Reel VNQ600PTR-E Rev. 1 October 2004 1/20 VNQ600P-E Figure 2. Block Diagram VCC 1,2 OVERVOLTAGE UNDERVOLTAGE DEMAG 1 DRIVER 1 OUTPUT 1 ILIM1 INPUT 1 LOGIC INPUT 2 GND 1,2 OVERTEMP. 1 OVERTEMP. 2 IOUT2 DRIVER 2 IOUT1 K CURRENT SENSE 1 OUTPUT 2 DEMAG 2 ILIM2 K CURRENT SENSE 2 OVERVOLTAGE UNDERVOLTAGE DEMAG 3 DRIVER 3 VCC 3,4 OUTPUT 3 ILIM3 INPUT 3 LOGIC INPUT 4 GND 3,4 OVERTEMP. 3 OVERTEMP. 4 IOUT4 DRIVER 4 IOUT3 K CURRENT SENSE 3 OUTPUT 4 DEMAG 4 ILIM4 K CURRENT SENSE 4 2/20 VNQ600P-E Table 3. Absolute Maximum Ratings Symbol VCC -VCC IOUT IR IIN VCSENSE IGND Parameter Supply voltage (continuous) Reverse supply voltage (continuous) Output current (continuous), for each channel Reverse output current (continuous), for each channel Input current Current sense maximum voltage Ground current at Tpins < 25C (continuous) Electrostatic Discharge (Human R=1.5K; C=100pF) VESD - INPUT - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tstg (L=0.11mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=40A) Power dissipation (per island) at Tlead=25C Junction operating temperature Storage temperature 126 6.25 Internally Limited -55 to 150 mJ W C C Body Model: 4000 2000 5000 5000 V V V V Value 41 -0.3 15 -15 +/- 10 -3 +15 -200 Unit V V A A mA V V mA Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins VCC 1,2 GND 1,2 INPUT 2 INPUT 1 CURRENT SENSE 1 CURRENT SENSE 2 VCC 1,2 VCC 3,4 GND 3,4 INPUT 4 INPUT 3 CURRENT SENSE 3 CURRENT SENSE 4 VCC 3,4 14 15 1 28 VCC 1,2 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 1 OUTPUT 1 OUTPUT 1 OUTPUT 4 OUTPUT 4 OUTPUT 4 OUTPUT 3 OUTPUT 3 OUTPUT 3 VCC 3,4 Connection / Pin Floating To Ground Current Sense Through 1K resistor N.C. X X Output X Input X Through 10K resistor 3/20 VNQ600P-E Figure 4. Current and Voltage Conventions IS3,4 VCC3,4 IIN1 VIN1 VSENSE1 VIN2 VSENSE2 VIN3 ISENSE1 IIN2 ISENSE2 IIN3 ISENSE3 INPUT1 CUR. SENSE1 INPUT2 CUR. SENSE2 INPUT3 CUR. SENSE3 INPUT4 CUR. SENSE4 GND3,4 IGND3,4 OUTPUT3 IOUT4 OUTPUT4 GND1,2 IGND1,2 VOUT4 VOUT3 OUTPUT2 IOUT3 VOUT2 OUTPUT1 IOUT2 IOUT1 VOUT1 VCC3,4 VCC1,2 IS1,2 VF1 (*) VCC1,2 VSENSE3 IIN4 VIN4 ISENSE4 VSENSE4 (*) VFn = VCCn - VOUTn during reverse battery condition Table 4. Thermal Data Symbol Rthj-case Rthj-amb Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient (one chip ON) Thermal resistance junction-ambient (two chips ON) (MAX) (MAX) (MAX) Value 15 60 (1) 46 (1) 44 (2) 31 (2) Unit C/W C/W C/W Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 4/20 VNQ600P-E ELECTRICAL CHARACTERISTICS (8V Note: 3. Vclamp and VOV are correlated. Typical difference is 5V. Note: (**) Per island. Table 6. Switching (VCC =13V) Symbol td(on) td(off) (dVOUT/ dt)on (dVOUT/ dt)off Parameter Turn-on delay time Turn-off delay time Turn-on voltage slope Test Conditions RL=2.6 channels 1,2,3,4 (see fig. 1) RL=2.6 channels 1,2,3,4 (see fig. 1) RL=2.6 channels 1,2,3,4 (see fig. 1) Min. Typ. 40 40 See relative diagram See relative diagram Max. Unit s s V/s Turn-off voltage slope RL=2.6 channels 1,2,3,4 (see fig. 1) V/s Table 7. VCC - Output Diode Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=2.3A; Tj=150C Min Typ Max 0.6 Unit V 5/20 VNQ600P-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Logic Input Symbol VIL VIH VI(hyst) IIL IIN VICL Parameter Low level input voltage High level input voltage Input hysteresis voltage Input current Input current Input clamp voltage VIN=1.5V VIN=3.5V IIN=1mA IIN= -1mA 6 6.8 -0.7 3.25 0.5 1 10 8 Test Conditions Min. Typ. Max. 1.25 Unit V V V A A V V Table 9. Protections (See note 4) Symbol Ilim TTSD TR Thyst Vdemag VON Parameter DC Short circuit current Thermal shut-down temperature Thermal reset temperature Thermal hysteresis Turn-off output voltage clamp Output voltage drop limitation IOUT=2A; L=6mH IOUT=0.5A; Tj= -40C...+150C VCC=13V 5.5V 6/20 VNQ600P-E ELECTRICAL CHARACTERISTICS (continued) Table 10. CURRENT SENSE (9V VCC 16V) (See Figure 5) Symbol K1 dK1/K1 Parameter IOUT/ISENSE Current Sense Ratio Drift Test Conditions IOUT1 or IOUT2=0.5A; VSENSE=0.5V; other channels open; Tj= -40C...150C IOUT1 or IOUT2=0.5A; VSENSE=0.5V; other channels open; Tj= -40C...150C IOUT1 or IOUT2=5A; VSENSE=4V; other channels open; Tj=-40C Tj=25C...150C dK2/K2 Current Sense Ratio Drift IOUT1 or IOUT2=5A; VSENSE=4V; other channels open; Tj=-40C...150C K3 IOUT/ISENSE IOUT1 or IOUT2=15A; VSENSE=4V; other channels open; Tj=-40C Tj=25C...150C dK3/K3 Current Sense Ratio Drift Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog Sense Output Impedance in Overtemperature Condition Current sense delay response IOUT1 or IOUT2=15A; VSENSE=4V; other channels open; Tj=-40C...150C VCC=5.5V; IOUT1,2=2.5A; RSENSE=10k VCC>8V, IOUT1,2=5A; RSENSE=10k VCC=13V; RSENSE=3.9k 4200 4400 -6 2 4 5.5 4900 4900 5500 5250 +6 % V V V Min 3300 -10 Typ 4400 Max 6000 +10 % Unit K2 IOUT/ISENSE 4200 4400 -6 4900 4900 6000 5750 +6 % VSENSE1,2 VSENSEH RVSENSEH VCC=13V; Tj>TTSD; All channels open 400 tDSENSE to 90% ISENSE (see note 5) 500 s Note: 5. Current sense signal delay after positive input slope. 7/20 VNQ600P-E Figure 5. IOUT/ISENSE versus IOUT IOUT/ISENSE 6500 6000 max.Tj=-40C 5500 max.Tj=25...150C 5000 4500 4000 3500 3000 min.Tj=25...150C typical value min.Tj=-40C 0 2 4 6 IOUT (A) 8 10 12 14 16 Figure 6. Switching Characteristics (Resistive load RL=2.6) VOUT 80% dVOUT/dt(on) tr ISENSE 90% 10% 90% dVOUT/dt(off) tf t INPUT tDSENSE t td(off) td(on) t 8/20 VNQ600P-E Table 11. Truth Table (Per channel) CONDITIONS Normal operation INPUT L H L H L H L H L Short circuit to GND H H Short circuit to VCC Negative output voltage clamp L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (Tj Overtemperature Undervoltage Overvoltage Table 12. Electrical Transient Requirements on VCC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 I C C C C C C IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 9/20 VNQ600P-E Figure 7. Waveforms (Per each chip) NORMAL OPERATION INPUTn LOAD CURRENTn SENSEn UNDERVOLTAGE VCC INPUTn LOAD CURRENTn SENSEn OVERVOLTAGE VOV VUSD VUSDhyst VCC INPUTn LOAD CURRENTn SENSEn VCC < VOV VCC > VOV SHORT TO GROUND INPUTn LOAD CURRENTn LOAD VOLTAGEn SENSEn SHORT TO VCC INPUTn LOAD VOLTAGEn LOAD CURRENTn SENSEn ISENSE= VSENSEH RSENSE TTSD TR 10/20 VNQ600P-E Figure 8. Application Schematic +5V Rprot INPUT1 VCC1,2 VCC3,4 Dld Rprot Rprot C. SENSE 1 INPUT2 OUTPUT1 C Rprot Rprot INPUT3 Rprot Rprot Rprot C. SENSE 4 GND1,2 GND3,4 C. SENSE 3 INPUT4 OUTPUT4 OUTPUT3 C. SENSE 2 OUTPUT2 RSENSE1,2,3,4 VGND RGND DGND Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / 2(IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 11/20 VNQ600P-E Figure 9. Off State Output Current IL(off1) (A) 4 3.5 Figure 10. Low Level Input Current Iil (A) 6 5.5 Vcc=13V 3 5 4.5 Vcc=13V Vin=1.5V 2.5 2 1.5 1 4 3.5 3 2.5 2 0.5 0 -50 -25 0 25 50 75 100 125 150 175 1.5 1 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 11. Input Clamp Voltage Vicl (V) 10 9.5 Figure 13. Input High Level Vih (V) 5 4.5 4 Iin=1mA 9 8.5 8 7.5 7 6.5 3.5 3 2.5 2 6 5.5 5 -50 -25 0 25 50 75 100 125 150 175 1.5 1 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 12. Input Low Level Vil (V) 4 3.5 3 Figure 14. Input Hysteresis Voltage Vhyst (V) 1.5 1.4 1.3 1.2 2.5 2 1.5 1 1.1 1 0.9 0.8 0.7 0.5 0 -50 -25 0 25 50 75 100 125 150 175 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) 12/20 VNQ600P-E Figure 15. Overvoltage Shutdown Vov (V) 55 52.5 50 60 47.5 45 42.5 40 37.5 20 35 32.5 30 -50 -25 0 25 50 75 100 125 150 175 10 0 -50 -25 0 25 50 75 100 125 150 175 50 40 30 Figure 16. ILIM Vs Tcase Ilim (A) 80 70 Vcc=13V Tc (C) Tc (C) Figure 17. Turn-on Voltage Slope dVout/dt(on) (V/ms) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175 Figure 19. Turn-off Voltage Slope dVout/dt(off) (V/ms) Vov (V) 55 1 0.9 52.5 Vcc=13V Rl=2.6Ohm 0.8 50 0.7 47.5 0.6 45 0.5 42.5 0.4 40 0.3 37.5 0.2 35 32.5 0.1 0 30 -50 -50 Vcc=13V Rl=2.6Ohm -25 -25 00 25 25 50 50 75 75 100 100 125 125 150 175 Tc (C) Tc (C) Tc (C) Figure 18. On State Resistance Vs Tcase Ron (mOhm) 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 Vcc=13V Iout=5V Tc (C) 13/20 VNQ600P-E Figure 20. Maximum Turn Off Current Versus Load Inductance ILMAX (A) 100 A B C 10 1 0.001 0.01 0.1 L(mH ) 1 10 100 A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 14/20 VNQ600P-E SO-28 Thermal Data Figure 21. SO-28 Double Island PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 3cm2, 6cm2). Table 13. Thermal Calculation According to the PCB Heatsink Area Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1Pdchip2 Note:RthA = Thermal resistance Junction to Ambient with one chip ON Note:RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 Note:RthC = Mutual thermal resistance Figure 22. Rthj-amb Vs PCB Copper Area In Open Box Free Air Condition RTHj_am b (C/W) 70 60 50 RthA 40 30 20 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7 RthB RthC 15/20 VNQ600P-E Figure 23. SO-28 Thermal Impedance Junction Ambient Single Pulse Zth(C /W ) 10 0 0,5 cm ^2/is lan d 3 cm ^2/is lan d 6 cm ^2/is lan d 10 One channel ON Two channels ON on same chip 1 0 .1 0.0 1 0.0 00 1 0 .0 01 0 .01 0 .1 1 tim e (s) 10 100 10 0 0 Figure 24. Thermal Fitting Model of a Quad Channels HSD in SO-28 Pulse Calculation Formula TH = R TH + Z THtp ( 1 - ) = tp T where Tj_1 C1 C2 C3 C4 C5 C6 R1 Pd1 R2 R3 R4 R5 R6 Table 14. Thermal Parameter Area/island (cm2) R1=R7=R13=R15 (C/W) R2=R8=R14=R16 (C/W) R3=R9 (C/W) R4=R10 (C/W) R5=R11 (C/W) R6=R12 (C/W) C1=C7=C13=C15 (W.s/C) C2=C8=C14=C16 (W.s/C) C3=C9 (W.s/C) C4=C10 (W.s/C) C5=C11 (W.s/C) C6=C12 (W.s/C) R17=R18 (C/W) 0.5 0.05 0.3 3.4 11 15 30 0.001 5.00E-03 1.00E-02 0.2 1.5 5 150 6 Tj_2 C13 C14 R13 Pd2 R14 R17 R18 Tj_3 Pd3 C7 C8 C9 C10 C11 C12 R7 R8 R9 R10 R11 R12 13 Tj_4 C15 C16 R15 Pd4 R16 T_amb 8 16/20 VNQ600P-E PACKAGE MECHANICAL Table 15. SO-28 Mechanical Data Symbol A a1 b b1 C c1 D E e e3 F L S 7.40 0.40 8 (max.) 17.7 10.00 1.27 16.51 7.60 1.27 0.10 0.35 0.23 0.50 45 (typ.) 18.1 10.65 millimeters Min Typ Max 2.65 0.30 0.49 0.32 Figure 25. SO-28 Package Dimensions 17/20 VNQ600P-E Figure 26. SO-28 Tube Shipment (no suffix) C B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm. 28 700 532 3.5 13.8 0.6 A Figure 27. Tape and Reel Shipment (suffix "TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 12 1.5 1.5 7.5 6.5 2 End All dimensions are in mm. Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components 18/20 VNQ600P-E REVISION HISTORY Table 16. Revision History Date Oct. 2004 Revision 1 First issue. Description of Changes 19/20 VNQ600P-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 20/20 |
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