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HD74LS669
Synchronous Up / Down 4-bit Binary Counter
REJ03D0493-0200 Rev.2.00 Feb.18.2005 This synchronous preset table 4-bit binary counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock input trigger the four master-slave flip-flops on the rising (positive-going) edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. the load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count enable inputs and a carry output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined by the level of the up / down input. when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up and approximately equal to the low portion of the QA output when counting down. This low level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diodeclamped to minimize transmission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, up / down) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
* Ordering Information
Part Name HD74LS669FPEL Package Type SOP-16 pin (JEITA) Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel)
PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS669
Pin Arrangement
U/D CK A Data Inputs B C D Enable P GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC Ripple Carry Output QA QB Outputs QC QD Enable T Load
(Top view)
Block Diagram
Clock U/D DQ CK Q Load Enable P Enable T DQ Data A CK Q Data B DQ CK Q QC QB QA
Data C DQ CK Q QD
Data D
Ripple Carry Output
Rev.2.00, Feb.18.2005, page 2 of 8
HD74LS669
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Count frequency Clock pulse width Input Data A, B, C, D Setup time Enable P, T Load Up/Down Hold time th tsu Symbol VCC IOH IOL Topr count tw (CK) Min 4.75 -- -- -20 0 25 25 35 30 35 0 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- -- -- ns ns Unit V A mA C MHz ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL A, B, C, D, P, U/D Clock, T Load A, B, C, D, P, U/D Clock, T Load A, B, C, D, P, U/D Clock, T min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- -- II -- typ.* -- -- -- -- -- -- -- -- -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 20 20 40 -0.4 -0.4 -0.8 0.1 0.1 mA VCC = 5.25 V, VI = 7 V Unit V V V V V A Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, IOL = 8 mA VIH = 2 V, VIL = 0.8 V VCC = 5.25 V, VI = 2.7 V
IIH
Input current
IIL
mA
VCC = 5.25 V, VI = 0.4 V
Load -- -- 0.2 Short-circuit output current IOS -20 -- -100 mA VCC = 5.25 V Supply current** ICC -- 20 34 mA VCC = 5.25 V Input clamp voltage VIK -- -- -1.5 V VCC = 4.75 V, IIN = -18 mA Notes: * VCC = 5 V, Ta = 25C ** ICC is measured after applying a momentary 4.5 V, then ground, to clock input with all other inputs grounded the outputs open.
Rev.2.00, Feb.18.2005, page 3 of 8
HD74LS669
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Inputs Outputs Ripple Carry QA to QD Ripple Carry Ripple Carry min. 25 -- -- -- -- -- -- -- -- typ. 32 26 40 18 18 11 29 22 26 max. -- 40 60 27 27 17 45 35 40 Unit MHz ns ns ns ns CL = 15 pF, RL = 2 k Condition
Clock Clock Enable T Up/Down
Propagation delay time
Count Sequence
Load A Data Inputs B C D Clock U/D P and T QA QB QC QD Ripple Carry Output
13 Load
14
15
0
1
2
2 Inhibit
2
1
0
15
14
13
Count Up
Count Down
Rev.2.00, Feb.18.2005, page 4 of 8
HD74LS669
Testing Method
Test Circuit
VCC 4.5V RL QA CL U/D Input CK Output QB Output QC Output QD Output RCO Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Output
Load circuit 1
See Waveforms
P.G. Zout = 50 Input P.G. Zout = 50
A B C D E*P Load E*T
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.2.00, Feb.18.2005, page 5 of 8
HD74LS669 Waveforms 1
tTHL 90% 1.3V 10% 10% tw (CK) tsu tw (CK) th 1.3V tsu tTLH
3V Clock
90% 1.3V 1.3V 1.3V 1.3V
0V 3V 0V
Load
1.3V tsu th
3V Data Inputs A, B, C, D
1.3V 1.3V
0V
tsu th
Enable P or Enable T
3V
1.3V tsu th tsu th 1.3V
0V 3V
Up/Down
1.3V
1.3V
1.3V
1.3V
0V 3V Enable T Input
1.3V tPHL 1.3V
0V
tPLH
Ripple Carry Output
VOH
1.3V 1.3V
VOL
Notes:
1. tPLH and tPHL from enable T input to ripple carry output assume that the counter is at the maximum count (QA through QD high). 2. Propagation delay time from up / douwn to ripple carry must be measured with the counter at either aminimum or a maximum count. As the logic level of the up / down input is changed, the riiple carry output will follow. If the count is minimum (0) are ripple carry output transition will be in phase. If the count is macimum (15) the ripple carry output will be out of phase. 3. Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Rev.2.00, Feb.18.2005, page 6 of 8
HD74LS669 Waveforms 2
tTLH tTHL 3V 10% tw (CK) 1.3V tPHL (Measure at tn + 2) 1.3V tPHL tPLH (Measure at tn + 2) (Measure at tn + 4) QB 1.3V 1.3V VOL tPLH (Measure at tn + 4) tPHL (Measure at tn + 8) QC 1.3V tPHL (Measure at tn + 16) QD tPLH Ripple Carry Output (Measure before 1 clock of tn + 16) 1.3V 1.3V tPHL (Measure at tn + 16) VOH 1.3V VOL 1.3V VOL tPLH (Measure at tn + 8) VOH 1.3V VOL VOH VOL VOH 1.3V 0V VOH 1.3V
Clock 10% tPLH QA
90% 1.3V 1.3V (Measure at tn + 1)
Notes:
1. Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50%. 2. For max tTLH = tTHL 2.5 ns. 3. tn is the bit-time when all outputs are low.
Rev.2.00, Feb.18.2005, page 7 of 8
HD74LS669
Package Dimensions
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 8 of 8
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Keep safety first in your circuit designs!
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