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| NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free D PRODUCT SUMMARY V(BR)DSS -20 RDS(ON) 118m[ ID -3A 1 :GATE 2 :DRAIN 3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -20 12 -3 -1.4 UNITS V V TC = 25 C TC = 70 C ID IDM A -10 1.25 0.8 W TC = 25 C TC = 70 C PD Tj, Tstg Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Ambient 1 2 -55 to 150 C UNITS C / W SYMBOL RJA TYPICAL MAXIMUM 166 Pulse width limited by maximum junction temperature. Duty cycle 1% ELECTRICAL CHARACTERISTICS (TC = 25 C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current 1 Drain-Source On-State Resistance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) VGS = 0V, ID = -250A VDS = VGS, ID = -250A VDS = 0V, VGS = 12V VDS = -16V, VGS = 0V VDS = -16V, VGS = 0V, TJ = 125 C VDS = -5V, VGS = -4.5V VGS = -2.5V, ID =-1A VGS = -4.5V, ID = -2A VGS = -10V, ID = -2A Forward Transconductance1 gfs VDS = -5V, ID = -2A -6 150 98 72 16 215 118 85 S -20 -0.45 -0.8 -1.2 100 -1 -10 A m[ nA A V LIMITS UNIT MIN TYP MAX Mar-25-2005 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge2 Gate-Source Charge Gate-Drain Charge2 Turn-On Delay Time2 Rise Time 2 2 2 Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 C) VDD = -10V ID -1A, VGS = -4.5V, RG = 6[ VDS = 0.5V (BR)DSS, VGS = -4.5V, ID = -2A VGS = 0V, VDS = -6V, f = 1MHz 430 235 95 7.6 3.2 2 11 32 38 32 22 55 68 55 nS 10 nC pF Turn-Off Delay Time Fall Time2 Continuous Current Pulsed Current 3 Forward Voltage1 1 2 IS ISM VSD IF = -1A, VGS = 0V -1.6 -3 -1.2 A V Pulse test : Pulse Width 300 sec, Duty Cycle 2H. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH "21YWW", DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. Mar-25-2005 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free Mar-25-2005 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature 10 -Is - Reverse Drain Current(A) V GS = 0V 1 T A = 125C 0.1 25C -55C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1.0 -V - Body Diode Forward Voltage(V) 1.2 Mar-25-2005 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free SOT-23 (M3) MECHANICAL DATA mm Dimension Min. A B C D E F G 0.85 2.4 1.4 2.7 1 0 0.35 1.6 2.9 1.1 Typ. Max. 1.15 3 1.8 3.1 1.3 0.1 0.5 H I J K L M N Dimension Min. 0.1 0.37 Typ. 0.15 Max. 0.25 mm H 2 C 1 A 3 B I D E G F Mar-25-2005 5 |
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