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TDA7463AD
LOW VOLTAGE TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
1

FEATURES
2 STEREO INPUT 1 STEREO OUTPUT TREBLE BOOST BASS CONTROL BASS AUTOMATIC LEVEL CONTROL VOLUME CONTROL IN 1dB STEPS MUTE STAND-BY FUNCTION SOFTWARE CONTROLLED ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
Figure 1. Package
SSO20P
Table 1. Order Codes
Part Number TDA7463AD Package SSO20P
The control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
2
DESCRIPTION
The TDA7463AD is a volume tone (bass and treble) processor for quality audio applications in Low voltage supply portable systems. Bass ALC (Automatic Level Control) function can be adjusted by a dedicated pin. Figure 2. Block Diagram
R5 5.6K C14 3.3nF 100nF C13
100nF C12
TREBLE-R 17 C1 0.47F IN2-R 18 INPUT SELECT -63dB CONTROL TREBLE
BASSI-R 16
BASSO-R 15
RB
50K C2 0.47F IN1-R 19
0/-10dB x1 BASS x5 14 OUT-R
50K I2C 1 10 HALF_WAVE RECTIFIER + I2C BUS DECODER + LATCHES 9 SDA SCL R3 1K R4 1K 2 3 4 VS DGND SCL SDA
VS BASS_ALC CONTROL C3 0.47F ALC R1 1M 20
VS
C4 0.47F IN1-L
2 TREBLE 50K -63dB CONTROL BASS 0/-10dB
x5 x1 7
OUT-L
C5 0.47F IN2-L
3
50K 4 5 TREBLE-L C6 3.3nF
RB 6 BASSI-L C7 100nF
VREF 11 BASSO-L
SUPPLY 12 GND CREF C9 22F
VS 1 C10 100nF
VS C11 100F
D99AU1049
C8 100nF R2 5.6K
November 2005
REV. 4 1/13
TDA7463AD
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Parameter Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Value 5 -10 to 85 -55 to 150 Unit V C C
Figure 3. Pin Connection (Top view)
VS IN1-L IN2-L TREBLE-L BASSI-L BASSO-L OUT-L N.C. SDA SCL
1 2 3 4 5 6 7 8 9 10
D99AU1050
20 19 18 17 16 15 14 13 12 11
ALC IN1-R IN2-R TREBLE-R BASSI-R BASSO-R OUT-R N.C. CREF GND
Table 3. Thermal Data
Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
Table 4. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 0.1Vrms; f = 1KHz Signal to Noise Ratio V out = 0.1Vrms (mode = OFF) Channel Separationf = 1KHz Volume Control (1dB step) -10dB damping 14dB Treble Control Bass Control Mute Attenuation -63 -10 0 0 0 100 80 80 0 0 14 8 14 Parameter Min 1.8 0.2 0.1 Typ 2.4 Max 3 Unit V Vrms % dB dB dB dB dB dB dB dB
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Table 5. ELECTRICAL CHARACTERISTCS (refer to the test circuit Tamb = 25C, VS =2.4V, RL = 10K, RG = 600, all controls flat, unless otherwise specified)
Symbol SUPPLY VS IS IST-BY SVR RIN VCL CRANGE AV MIN AV MAX ASTEP Amute A-10dB G14dB Gb RB Gt VCLIP RL VDC GENERAL ENO Output Noise Outout Muted All gains = 0dB; BW = 20Hz to 20KHz flat All gains 0dB; VO = 0.1VRMS ; AV = 0; VI = 0.1VRMS ; 5 8 0 80 80 0.1 0.5 1.9 VIN = 0.4V IO = 1.6mA -5 5 0.4 1 V V dB dB dB % V V A V Supply Voltage Supply Current Stand-By Current Ripple Rejection Input Resistance Clipping Level Control Range Min Attenuation Max. Attenuation Step Resolution Mute Attenuation -10dB damping 14dB gain Control Range Internal Feedback Resistance Control Range Clipping Level Output Load Resistance DC Voltage Level Max. Boost on d = 0.3% 0.2 10 0.8 Max. Boost/on 33.75 80 -1 62 THD = 0.3% 35 0.2 63 0 63 1 100 10 14 14 45 8 56.25 1 64 1.8 2.4 4 50 70 50 65 3 V mA A dB K& Vrms dB dB dB dB dB dB dB dB K dB VRMS K& V Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE
VOLUME CONTROL
BASS CONTROL (1)
TREBLE CONTROL (1) AUDIO OUTPUTS
Et S/N SC d VIL VIH IIN VO
Total Tracking Error Signal to Noise Ratio Channel Separation Left/Right Distortion Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge
BUS INPUT
Note: 1. BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
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3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7463AD and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 6). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 4. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 5. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
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Figure 6. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
4
SOFTWARE SPECIFICATION
4.1 Interface Protocol The interface protocol comprises: A start condition (S)

A chip address byte, containing the TDA7463AD address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
Figure 7.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
5
DATA BYTES
Address = (HEX) 10001000 5.1 FUNCTION SELECTION: The first byte (subaddress)
MSB D7 D6 X X X
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1
LSB SUBADDRESS D5 X X X D4 B B B D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 STAND-BY & TREBLE & OTHERS BASS VOLUME
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5.1.1 STAND_BY & TREBLE & OTHERS
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 STAND-BY 1 ALL CIRCUITS STOP TREBLE 1 1 0 1 0 0 0 0 0 0 0 STAND-BY (Treble block stops) BOOST OFF BOOST ON High Boost (+8dB) Low Boost (+4dB) MUTE 1 0 1 0 Input Mute ON Input Mute OFF Output Mute ON Output Mute OFF BASS 1 0 Release Current Circuit ON Release Current Circuit OFF INPUT Select 1 0 INPUT 1 INPUT 2
5.1.2 BASS
MSB D7 D6 D5 D4 D3 D2 D1 1 0 0 0 LSB D0 1 BASS STAND-BY (Bass block stops) BASS (boost OFF) BASS (boost ON) High boost (Ex. + 14dB) Low boost (Ex. + 6dB) ALC mode OFF (ALC block stops) ALC mode ON Attack time resistor (12.5K&) Release current (0.4 A) Attack time resistor (25K&) Release current (0.2 A) Attack time resistor (50K&) Release current (0.1 A) Attack time resistor (100K&) Release current (0.05 A) Threshold1 (0.2Vrms) Threshold2 (0.14Vrms) Threshold3 (0.1Vrms) Threshold4 (0.07Vrms)
1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
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5.1.3 VOLUME
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -8 -16 -24 -32 -40 -48 -56 OUTPUT GAIN 1 0 0dB +14dB OUTPUT ATTENUATION 1 0
VOLUME: 0 ~ -63dB
VOLUME 1 dB STEPS
0dB -10dB
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5.2 ALC IN general: 5.2.1 VOLUME setting with ALC
Target Volume [dB] 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 : : -70 -71 -72 -73 Volume [dB] -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -14 -15 -16 -17 : : -60 -61 -62 -63 0 -10 0 0 Output Gain 0/+14dB 0/+14dB +14 Output Attenuation 0/-10dB [dB] 0
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TDA7463AD
Figure 8. PIN: IN-L, IN-R Figure 11. PIN: OUT-L, OUT-R
VS 20A
VS 20A 10
50K
GND
GND
Vref
D99AU1106
D99AU1107
Figure 9. PIN: TREBLE-L, TREBLE-R
Figure 12. PIN: SCL, SDA
VS 20A
25K GND
D99AU1108
GND
D99AU1109
Figure 10. PIN: BASSI-L, BASSI-R
Figure 13. PIN: BASSO-L, BASSO-R
VS 20A
VS 20A
GND
45K
45K GND
D99AU1110
BASSO-L,BASSO-R
BASSI-L,BASSI-R
D99AU1111
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TDA7463AD
Figure 14. PIN: ALC Figure 16. BASS ALC: Threshold Curve
VO (Vrms)
VS=1.8V; f=100Hz; Volume=-14dB; Output gain=+14dB Intern. release circuit=ON
D99AU1115
VS 20A
Bass boost without ALC Bass boost with ALC Threshold: 8dB 11dB
0.1
17dB
14dB
100K
Bass= +14dB boost flat
GND
D99AU1112
0.01 0.01 0.1 VI(Vrms)
Figure 15. PIN: CREF
Figure 17. BAS ALC: THD
THD V =1.8V; f=100Hz; S (%) Volume=-14dB; 10
Output gain=+14dB Intern. release circuit=ON Bass boost with ALC
D99AU1114
VS 20A 1K
1
Threshold
B 14d 11d B 8dB
0.1
17dB
Bass boost without ALC
GND
D99AU1113
0.01
flat
0.001 0.01
0.1
VI(Vrms)
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TDA7463AD
Figure 18. SSOP20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b c D (1) E 0.050 1.650 0.220 0.090 6.900 7.400 7.200 7.800 5.300 0.650 0.550 0.750 1.250 0.950 0.022 1.750 1.850 0.380 0.250 7.500 8.200 5.600 TYP. MAX. 2.000 0.002 0.065 0.009 0.005 0.272 0.291 0.197 0.283 0.307 0.209 0.026 0.029 0.049 0.037 0.069 0.073 0.015 0.010 0.295 0.323 0.220 MIN. TYP. MAX. 0.079 inch
OUTLINE AND MECHANICAL DATA
E1 (1) 5.000 e (2) L L1 k ddd
0 (min.), 4 (typ.), 8 (max.) 0.100 0.004
Notes: 1. D and E1 does not include mold flash or protrusions, but do include mold mismatch and are measured at datum plane "H". Mold flash or potrusions shall not exceed 0.20mm (.008inch) both side. 2. "b" dimensions does not include dambar protusion/intrusion.
SSOP20
0061436 C (Jedec MO-150-AE)
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Table 6. Revision History
Date January 2004 June 2004 November 2005 Revision 2 3 4 Description of Changes First Issue in EDOCS DMS Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide" Add section 3 and 4
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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