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| FDD5810 N-Channel Logic Level Trench(R) MOSFET October 2007 FDD5810 N-Channel Logic Level Trench(R) MOSFET 60V, 36A, 27m Features RDS(ON) = 22m (Typ.), VGS = 5V, ID = 29A Qg(5) = 13nC (Typ.), VGS = 5V Low Miller Charge Low Qrr Body Diode UIS Capability (Single Pulse / Repetitive Pulse) Qualified to AEC Q101 RoHS Compliant Applications Motor / Body Load Control ABS Systems Powertrain Management Injection System DC-DC converters and Off-line UPS Distributed Power Architecture and VRMs Primary Switch for 12V and 24V systems A REE I DF M ENTATIO LE N MP LE D G S D G D-PAK TO-252 (TO-252) S (c)2006 Fairchild Semiconductor Corporation FDD5810 Rev. A (W) 1 www.fairchildsemi.com FDD5810 N-Channel Logic Level Trench(R) MOSFET Absolute Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS VGS ID EAS PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (VGS = 10V) Drain Current Continuous (VGS = 5V) Pulsed Single Pulse Avalanche Energy (Note 1) Power Dissipation Derate above 25oC Operating and Storage Temperature Continuous (TA = 25oC, VGS = 10V, with RJA = 52oC/W) Ratings 60 20 37 33 7.4 Figure 4 45 72 0.48 -55 to 175 Units V V A A A A mJ W W/oC o C Thermal Characteristics RJC RJA Maximum Thermal resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 2.1 52 oC/W oC/W Package Marking and Ordering Information Device Marking FDD5810 Device FDD5810 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units Electrical Characteristics TJ = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 48V VGS = 0V VGS = 20V TC = 150oC 60 1 250 100 V A nA On Characteristics VGS(TH) RDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 32A, VGS = 10V ID = 29A, VGS = 5V ID = 32A, VGS = 10V, TJ = 175oC 1 1.6 18 22 43 2 22 27 53 m V Dynamic Characteristics Ciss Coss Crss RG Qg Qg Qg(th) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V ID = 35A 1420 150 65 3.5 24 13 1.3 4.0 2.7 5.0 1890 200 100 34 18 pF pF pF nC nC nC nC nC nC FDD5810 Rev. A (W) 2 www.fairchildsemi.com FDD5810 N-Channel Logic Level Trench(R) MOSFET Switching Characteristics ton td(on) tr td(off) tf toff Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 30V, ID = 35A VGS = 5V, RGS = 11 12 75 26 34 130 90 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr Qrr Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovery Charge ISD = 32A ISD = 16A IF = 35A, di/dt = 100A/s IF = 35A, di/dt = 100A/s 1.25 1.0 39 35 V V ns nC Notes: 1: Starting TJ = 25C, L = 110H, IAS = 28A, VDD = 54V, VGS = 10V. FDD5810 Rev. A (W) 3 www.fairchildsemi.com FDD5810 N-Channel Logic Level Trench(R) MOSFET Typical Characteristics TJ = 25C unless otherwise noted 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 40 30 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 (oC) 150 175 TC , CASE TEMPERATURE VGS = 10V 20 VGS = 5V 10 0 25 50 75 TC, CASE 100 125 150 175 TEMPERATURE(oC) Figure 1. Normalized Power Dissipation vs Case Temperature 2 1 THERMAL IMPEDANCE Figure 2. Maximum Continuous Drain Current vs Case Temperature ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x RJC + TC 10-3 10-2 10-1 100 101 0.01 10-5 10-4 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 600 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 IDM, PEAK CURRENT (A) 100 VGS = 5V 30 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability FDD5810 Rev. A (W) 4 www.fairchildsemi.com FDD5810 N-Channel Logic Level Trench(R) MOSFET Typical Characteristics TJ = 25C unless otherwise noted 200 100 ID , DRAIN CURRENT (A) 500 IAS, AVALANCHE CURRENT (A) 10us 100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(on) 100us 10 STARTING TJ = 150oC STARTING TJ = 25oC 1 SINGLE PULSE TJ = MAX RATED o TC = 25 C 1ms 10ms DC 0.1 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200 0.001 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability VGS = 4.5V 60 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 6V ID, DRAIN CURRENT (A) 60 VGS = 10V VGS = 5V 40 ID , DRAIN CURRENT (A) 40 TJ = 25oC 20 VGS = 4V VGS = 3.5V 20 VGS = 3V TJ = 175oC 0 0 1.0 2.0 TJ = -55oC 0 3.0 4.0 5.0 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0.5 1.0 1.5 TC = 25oC 2.0 2.5 VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 30 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE Figure 8. Saturation Characteristics 2.8 2.4 2.0 1.6 1.2 0.8 0.4 -80 ID = 32A VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX RDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 26 ID = 35A 22 18 ID = 1A 14 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) -40 TJ, JUNCTION TEMPERATURE(oC) 0 40 80 120 160 200 Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDD5810 Rev. A (W) 5 www.fairchildsemi.com FDD5810 N-Channel Logic Level Trench(R) MOSFET Typical Characteristics TJ = 25C unless otherwise noted 1.4 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 VGS = VDS, ID = 250A ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.1 1.1 0.8 1.0 0.5 0.2 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 10000 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 30V 8 Ciss C, CAPACITANCE (pF) 1000 Coss Crss 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 1A 0 5 10 15 20 25 100 2 10 0.1 VGS = 0V, f = 1MHz 0 1 10 60 VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Current FDD5810 Rev. A (W) 6 www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) (R) Fairchild(R) Fairchild Semiconductor(R) FACT Quiet SeriesTM FACT(R) FAST(R) FastvCoreTM FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) (R) PDP-SPMTM Power220(R) Power247(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM The Power Franchise(R) TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyPWMTM TinyWireTM SerDesTM UHC(R) UniFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I31 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production (c) 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com |
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