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HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348-0400Z (Previous ADE-205-108C (Z)) Rev.4.00 Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to be taken high to put the output into the high impedance condition, whereas the device requires the control input to be low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
* * * * * * * VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information
Package Type SOP-14 pin (JEITA) TSSOP-14 pin Package Code FP-14DAV TTP-14DV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LVC125AFPEL HD74LVC125ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs C H L L H: L: X: Z: High level Low level Immaterial High impedance A X L H Outputs Y Z L H
Rev.4.00 Jul. 23, 2004 page 1 of 6
HD74LVC125A
Pin Arrangement
1C 1 1A 2 1Y 3 2C 4 2A 5 2Y 6 GND 7
14 VCC 13 4C 12 4A 11 4Y 10 3C 9 3A 8 3Y
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings -0.5 to 6.0 -50 -0.5 to 6.0 -50 50 -0.5 to VCC +0.5 -0.5 to 6.0 50 100 -65 to +150 Unit V mA V mA V mA mA C Conditions VI = -0.5 V VO = -0.5 V VO = VCC +0.5 V Output "H" or "L" Output "Z" or VCC:OFF
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.4.00 Jul. 23, 2004 page 2 of 6
HD74LVC125A
Recommended Operating Conditions
Item Supply voltage Input / output voltage Symbol VCC VI VO Ta IOH IOL Input rise / fall time *1 tr, tf Ratings 1.5 to 5.5 2.0 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 -40 to 85 -12 -24*2 12 24*2 10 Unit V V V C mA mA ns/V Conditions Data hold At operation C, A Output "H" or "L" Output "Z" or VCC:OFF VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V
Operating temperature Output current
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle 50%
Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 2.7 to 5.5 0 2.7 to 3.6 2.7 to 5.5 3.0 to 3.6 Min 2.0 VCCx0.7 -- -- VCC -0.2 2.2 2.4 2.2 3.8 -- -- -- -- -- -- -- -- -- -- Max -- -- 0.8 VCCx0.3 -- -- -- -- -- 0.2 0.4 0.55 0.55 5.0 5.0 20 10 10 500 Unit V V V IOH = -100 A IOH = -12 mA IOH = -24 mA V IOL = 100 A IOL = 12 mA IOL = 24 mA VIN = 5.5 VCC GND VIN = VCC, GND, VOUT = 5.5 V or GND VIN / VOUT = 5.5 V VIN / VOUT = 3.6 to 5.5 V VIN = VCC or GND VIN = one input at (VCC -0.6) V, other inputs at VCC or GND Test Conditions
VOL
Input current Off state output current Output leak current Quiescent supply current
IIN IIOZ IOFF ICC ICC
A A A A A
Rev.4.00 Jul. 23, 2004 page 3 of 6
HD74LVC125A
Switching Characteristics
Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL tZH tZL tHZ tLZ VCC (V) 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 2.7 Min -- 1.5 -- -- 1.5 -- -- 1.5 -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- 3.0 15.0 Max 6.5 6.0 5.0 8.0 7.0 6.0 6.5 5.5 4.5 -- 1.0 1.0 -- -- Unit ns From (Input) A To (Output) Y
Output enable time
ns
C
Y
Output disable time
ns
C
Y
Between output pins skew *1 tOSLH tOSHL Input capacitance Output capacitance Note: CIN CO
ns
pF pF
1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn|
Test Circuit
VCC VCC
See Function Table
Input
Output 500 S1 CL = 50 pF 450 50 Scope
Pulse Generator Zout = 50
*1
OPEN See under table GND
Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ
S1
Vcc=2.7V, 3.30.3V Vcc=5.00.5V
OPEN GND 6V
OPEN GND 2xVcc
Note:
1. CL includes probe and jig capacitance.
Rev.4.00 Jul. 23, 2004 page 4 of 6
HD74LVC125A Waveforms - 1
tr 90 % Input A Vref 10 % t PLH Vref 90 % Vref 10 % t PHL VOH Output Y Vref VOL tf VIH GND
Notes:
1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform : PRR = 10 MHz, duty cycle 50%
Waveforms - 2
tf Input C 90 % Vref 10 % t ZL Waveform - A t ZH Waveform - B Vref Vref t HZ VOH - 0.3 V tr 90 % Vref 10 % t LZ VIH GND V OH1 VOL + 0.3 V VOL VOH V OL1 TEST VIH Vref VOH1 VOL1
Vcc=2.7V, 3.30.3V Vcc=5.00.5V
2.7 V 1.5 V 3V GND
Vcc 50%Vcc Vcc GND
Notes:
1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform : PRR = 10 MHz, duty cycle 50% 3. Waveform - A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform - B shows input conditions such that the output is "H" level when enable by the output control.
Rev.4.00 Jul. 23, 2004 page 5 of 6
HD74LVC125A
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
1
7
5.5
*0.20 0.05
2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
5.00 5.30 Max 14 8
1
7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max 0 - 8 0.50 0.10
*0.20 0.05
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-14DV -- -- 0.05 g
Rev.4.00 Jul. 23, 2004 page 6 of 6
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