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POWER MANAGEMENT Description
Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator
Features
VIN Range: 2.3 - 5.5V 4A Continuous Output Current Adjustable Output Voltage 0.5V to Vin Low RDS(ON) integrated FETs: 75m and 47m Up to 95% Efficiency Synchronizable and Programmable Frequency: 200kHz - 2MHz Power Good Monitor <1A of Shutdown Current Programmable Soft Start Programmable Current Limit Over Temperature protection -40 to +85 C Ambient Temperature Range 4X4mm MLPQ-20 packages- WEEE and RoHS compliant
SC4624A
The SC4624A is a highly integrated synchronous stepdown DC/DC regulator designed for low input voltage range of 2.3V to 5.5 Volts. It can deliver 4A continuous output current with the output voltage as low as 0.5 Volts. The internal low RDS(ON) synchronous power switches eliminate the need for external Schottky diode while delivering overall converter efficiency up to 95%. A power good pin is available to monitor the output voltage status. Operating frequency is adjustable from 200 kHz to 2MHz with a single resistor and it can be synchronized to an external clock. The SC4624A offers adjustable current limit, soft start and over temperature protection to safeguard the device under extreme operating conditions. The soft start provides a controlled output voltage ramp up at startup. When a logic low is applied to the Enable pin, the SC4624A enters the shutdown mode and it consumes less than 1A of current. The SC4624A is available in 4x4 MLPQ-20 and it is rated over -40C to +85C ambient temperature range.
Applications
Low Voltage Distributed DC-DC Converters Telecommunication Power Supplies Portable Equipment xDSL
Typical Application Circuit
5 4 3 2 1
R4
D
C11 L1
Vin
PVIN R5 C9 R6 R2 C3 SYNC/EN PGOOD VCC FB PH
D
Vout
R7 R8 C8 C4
C
C
SC4624A
SS ISET FS
R1 C2
R9 C1
B
B
COMP
AGND
C7
C5
R3 R11
A
PGND
A
5
4
3
2
1
Revision: July 10, 2008
1
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SC4624A
POWER MANAGEMENT Pin Configuration
5 4 D 3 2 1
Ordering Information
D
Top View
Device
Top Mark SC 4624A
Package MLPQ-20
PH
NC NC
PH
PH
SC4624AMLTRT (1) (2) SC4624AEVB-MLPQ
PVIN
C
20 1
PVIN ISET
16 15
Evaluation Board
PGND
SS FS
T
5 6 11 10
PGND
FB
AGND VCC
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices for MLPQ-20 C package. (2) Available in lead-free package only. Device is WEEE and RoHS compliant.
B
B
A
20Pin MLPQ
JA= 29C/W; JC= 2.5C/W.
5 4 3 2 1
SYNC/EN
PGOOD
COMP
VCC
NC
A
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SC4624A
POWER MANAGEMENT Absolute Maximum Ratings
Parameter Supply Voltage PVIN to VCC FB, COMP, ISET, SYNC/EN, FS, SS, PGOOD to AGND PGND to AGND PHASE Voltage to PGND PHASE Pulse Voltage to PGND Tpulse < 50ns Storage Temperature Range Junction Temperature IR Reflow Temperature ESD Protection Level(1)
Note: 1) Tested in accordance to JEDEC standard JESD22-A114B.
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Symbol PVIN, VCC
Maximum -0.3 to 6 +/- 0.3 -0.3 to VCC+ 0.3 +/- 0.3
Units V V V V V V C C C kV
VPHASE VPHASE TSTG TJ TP
VESD
-0.3 to PVIN+ 0.3 -3 to PVIN+ 2 -40 to 150 150 260 2
Recommended Operating Conditions
The Performance is not guarantied if exceeding the specifications below.
Parameter Power Supply Input Voltage Operating Range Ambient Temperature Range Junction Temperature Max. Output Current
Symbol
Conditions
Min
Typ
Max
Units
VIN TA TJ IOUTMAX
2.3 -40 -40 0
5.5 85 125 4
V C C A
Electrical Characteristics
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1K, RISET=27.4K, TA = -40C to 85C
Parameter Power Supply Start Threshold Voltage, UVLO Hysteresis Voltage, UVLO Supply Current, Shutdown Supply Current, Operating
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Symbol
Conditions
Min
Typ
Max
Units
VIUV VIUVHY ISD IQswitching IQL
VIN Rising
2 120
2.25
V mV
VSYNC = 0V FB = COMP, No Load FB = 0.6V, No Load
3
0.2 7 3.5
1 10 7
A mA mA
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SC4624A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1K, RISET=27.4K, TA = -40C to 85C.
Parameter Thermal Shutdown Thermal Shutdown Trip Point Thermal Shutdown Hysteresis Synchronization, Enable Input SYNC/EN Threshold Frequency Range, SYNC Oscillator Osciilator Frequency Range Osciilator Frequency Accuracy Ramp Peak to Valley(1) Ramp Peak Voltage(1) Ramp Valley Voltage(1) Soft Start, Current Limit Soft-Start Charge Current ISET Bias Voltage Over Current Trip Output UVLO Hiccup period(1) Error Amplifier Error Amplifier Open Loop Voltage Gain (1) Error Amplifier Unity Gain Bandwidth(1) Output Voltage Slew Rate, COMP(1) Source Output Current, COMP Sink Output Current, COMP Output Voltage High, COMP
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Symbol
Conditions
Min
Typ
Max
Units
TOTP TOTP_HYS
Temperature Rising
160 10
C C
VENL VENH FSYNC
Logic Low Logic High 20% Higher than FOSC 2.0 200
0.8
V V
2000
kHz
FOSC ROSC= 51.1K ROSC=51.1K, TA=TJ=25C VPV VP VV
200 415 435 500 500 1.0 1.25 0.25
2000 585 565
kHz kHz kHz V V V
ISS VISET IIST VOUV TOCHP RISET = 27.4K RISIT = 57.6K VFB drop 0.45 1.9
4 0.55 2.55 0.3 131072 0.61 3.1
A V A V clks
100 10 4 FB = 0.4V FB = 0.6V FB = 0.4V, ICOMP = -1mA
4
dB MHz V/s mA mA V
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20 25 2.5
SC4624A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VIN= VCC=SYNC/EN=3.3V, ROSC=51.1K, RISET=27.4K, TA = -40C to 85C.
Parameter Error Amplifier (Cont.) Output Voltage Low, COMP Feedback Voltage Input Bias Current(1) Power Switches High-Side P-MOSFET Low Side N-MOSFET Power Good PGood Voltage Low PGood Leakage Current PGood Delay Time(1) PGood High Window
Note: (1) Guaranteed by design.
Symbol
Conditions
Min
Typ
Max
Units
FB = 0.6V, ICOMP = 1mA VFB IFB 0.4925 Vcc = 2.3V to 5.5V FB=VREF -2
0.1 0.5 +1
0.25 0.5075 +2 300
V V % nA
RDSH(on) RDSL(on)
VIN=VCC=5V, ISOURCE = 1A, TA=TJ=25 C VIN=VCC=5V, ISINK = 1A, TA=TJ=25 C
74 47
100 85
m m
VPGL IPGOOD TD
IPGOOD = 1mA PGOOD = 5V Vout rising or Vout falling With respect to nominal output, TA=TJ=25 C +8
0.2 1 1024 +10 +15
V A clks %
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SC4624A
POWER MANAGEMENT Start up by Vin Operation Typical Performance Characteristics
Circuit condition: Application circuit#1, 5VIN, 1VOUT
VIN Vin 5V/DIV 5V/DIV VOUT Vout SS SS 5V/DIV 5V/DIV VOUT Vout
Test condition: 5Vin, 1Vo, Io=0A
Start up by Vin
Test condition: 5Vin, 1Vo, Io=0A
VIN Vin SS SS
0.5V/DIV 5V/DIV 10ms/DIV
PGOOD PGOOD
0.5V/DIV 5V/DIV 10ms/DIV
PGOOD PGOOD
Figure 1. Start Up by VIN@0A Shutdown by Vin
Test condition: 5Vin, 1Vo, Io=0A
FigureShutdownUp by VIN@4A 2. Start by Vin
Test condition: 5Vin, 1Vo, Io=4A
5V/DIV 5V/DIV VIN Vin SS SS 0.5V/DIV VVout OUT 5V/DIV
PGOOD PGOOD
5V/DIV 5V/DIV VIN Vin
SS SS
0.5V/DIV VOUT 5V/DIV
Vout PGOOD PGOOD
5ms/DIV
1ms/DIV
Figure Transient responseIN@0A 3. Shutdown by V
Test condition: 5Vin, 1Vo, Io=0 to 4A R=F=2.5A/us,T1=T2=0.1ms
Figure 4. ShutdownRipple @4A Stability and by VIN
Test condition: 5Vin, 1Vo, Io=4A, (Operating stably)
Vout
20mV/DIV 50mV/DIV
Io
Vout V
OUT
VOUT Vout
2A/DIV 20us/DIV
lOUT IOUT
2.0V/DIV 1us/DIV
Vphase V
PHASE
Figure 5. Transient Response@ 0 to 4A
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Figure 6. Ripple and Stability@4A
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SC4624A
POWER MANAGEMENT Over current protection Operation Typical Performance Characteristics (Cont.)
Test condition: circuit#1, 5V , 1V Circuit condition: Application5Vin, 1Vout IN OUT
Thermal protection
Test condition: 5Vin, 1Vout
0.6V/DIV
0.6V/DIV
Vout OUT
VVout OUT
V
5.0V/DIV
SS SS
5.0V/DIV
SS SS
3.0V/DIV 100ms/DIV
Vphase PHASE
V
3V/DIV 1s/DIV
Vphase VPHASE
Figure 7. Over Load Hiccup
SYNC
External clock singal=650kHz, duty=50%
Sync Signal Efficiency(%)
Figure 8. Thermal Shutdown Protection@0A
Efficiency
5Vin
2.0V/DIV
SYNC
2.5Vin 3.3Vin
2.0V/DIV 1us/DIV
VPHASE Vphase
Output Current(A)
Figure 9. Synchronization
Internal PMOS RDSON @ Room Temperature
Figure 10. Efficiency(VIN)
Internal NMOS RDSON @ Room Temperature
130
80
120
75
2.5VIN
110
RDSON (m)
100
RDSON (m)
2.5VIN
70
3.3VIN
65
90
3.3VIN
60
80
5VIN
55
5VIN
70 1 2
IOUT (A)
3
4
50 1 2
IOUT (A)
3
4
Figure 11. High-Side P-MOSFET
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Figure 12. Low-Side N-MOSFET
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SC4624A
POWER MANAGEMENT Operation Typical Performance Characteristics (Cont.)
Regulation During Switching to Linear Mode
2.54 2.52 2.50 2.48
VOUT
OCP Trip
3.3Vin
5Vin
VOUT (V)
IOUT (A)
2.46 2.44 2.42 2.40 2.38 2.36 0.0 0.2 0.4 0.6 0.8
2.5Vin
IOUT (A)
1.0
1.2
1.4
1.6
1.8
2.0
RISET (K)
Figure 13. Loading Regulation
Figure 14. Over Current Setting versus RISET
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SC4624A
POWER MANAGEMENT Pin Descriptions
Pin Pin Name MLPQ-20 1,2 3 4 5 6 7,12 8,19,20 9 PVIN ISET SS FS PGOOD VCC NC Pin Functions Power supply voltage for high side MOSFETs. Current limit setting pin. A resistor connected between ISET and AGND sets the over current protection threshold. A ceramic decoupling between ISET pin to AGND have to be reserved to prevent from noise influence. Soft start time setting pin. A cap connected from this pin to GND sets the soft start up time. Oscillator frequency setting pin. An external resistor connected from this pin to GND sets the oscillator frequency. Power good indicator. It is an open drain output. Low when the output is below the power good threshold level. Power supply voltage for the analog section of the controller. No connection.
The oscillator frequency of the SC4624A is set by FS when SYNC/EN is pulled and held above SYNC/EN 2V. Its synchronous mode is activated as SYNC/EN is driven by an external clock. Its shutdown mode is invoked if SYNC/EN is pulled and held below 0.8V. COMP FB AGND PGND PH This is the output of the error amplifier. The voltage at this point is connected to the inverting input of the PWM comparator. A compensation network is required in order to optimize the dynamic performance of the voltage mode control loop. The inverting input of the error amplifier. It serves as the output voltage feedback point for the buck controller. It senses the output voltage through an external divider. Analog signal ground. Power ground. Switching nodes
10 11 13 14,15 16,17,18
THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not electrically PAD connected internally.
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SC4624A
POWER MANAGEMENT Block Diagram
VCC
ASYNCHRONOUS START UP THERMAL SHUTDOWN
0.5V
BANDGAP
UVLO
+ TOP GATE
PVIN1 PVIN2
BANDGAP HIGH SIDE DRIVER AND LOGIC AGND VREF
CONTROL AND HICCUP
ISET
I = F(R_ISET) PH1
OVER CURRENT PROTECT
SS FB COMP SYNC/EN FB FS
SD OSC CLOCK
PWM BLOCK PWM LOGIC
SHOOTTHRU PROTECTION
LOW SIDE DRIVER AND LOGIC
0.9VREF
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DELAY
1.1VREF
10
+
BOTTOM GATE
SOFT START
ERROR OPAMP
PH2
PH3
PGND1 PGND2
PGOOD
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SC4624A
POWER MANAGEMENT Application Information
Overview The SC4624A is a programmable high switching frequency, integrated 4A MOSFET, synchronous step down regulator. This reduces external component count and makes it effective for applications which are low in cost and sized small. A non-overlap protection is provided for the gate drive signals to prevent shoot through of the internal MOSFET pair. The SC4624A is capable of producing an output voltage as low as 0.5V and Its operation frequency is programmable up to 2MHz by an external resistor. It features lossless current sensing of the voltage drop across the internal drain to source resistance of the high side MOSFET during its conduction period. The quiescent supply current in shutdown mode is typically lower than 1A. An external soft start is provided to prevent output voltage overshoot during start-up. Over Temperature Protection, Power Good Indicator, External Clock Synchronization are some of the internal added features. Enable The SC4624A is enabled by applying a voltage greater than 2V (typical) to the VCC and SYNC/EN pin. The voltage on the VCC pin determines the operation of the SC4624A. As VCC increases during start up, the UVLO block senses VCC and keeps the high side and low side MOSFETs off and the internal soft start voltage low until VCC reaches 2V. If no faults are present, the SC4624A will initiate a soft start when VCC exceeds 2V. A typical 120mV hysteresis in the UVLO comparator provides noise immunity during its start up. (refer to Figures 1 & 2). Shutdown The SC4624A is disabled when VCC falls below 1.88V (typical) or shutdown mode operation is invoked by clamping the SYNC/EN pin to a voltage below 0.8V. During the shutdown mode, A typical 0.2A current draw through the VCC pin, the internal soft start voltage is held low and the internal MOSFETs are turned off. (refer to Figures 3 & 4). Soft Start The soft start function is required for step down controllers to prevent excess in-rush current through the DC bus during start up. An external capacitor is necessary for the soft start function and is connected from SS pin to AGND.
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During start up or restart, A typical 4A sourcing current charges the capacitor and then the voltage of capacitor ramp up the error amp reference slowly. The closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. The duration of the soft start in the SC4624A is controlled by an external capacitor. The SC4624A starts up in asynchronous mode before SS voltage reaches to 0.5V, and the bottom FET diode is used for circulating current during the top FET off time. Ths SS voltage level is clamped at VCC finally. Oscillator The FS pin is used to set the PWM oscillator frequency through an external resistor that is connected from the FS pin to the AGND. The internal ramp is a triangle at the PWM frequency with a peak voltage of 1.25V and a valley voltage of 0.25V. The approximate operating frequency is determined by the value of an external resistor as shown in Figure 15.
Switching Frequency Setting
145 135 125 115 105 95 85 75 65 55 45 35 25 15 5 200 400
RFS (K)
5VIN
2.5VIN
600
800
1000
1200
1400
1600
1800
2000
Fosc (kHz)
Figure 15. Switching Frequency vs. RFS
The operation frequency can be programmed up to 2MHz, but there is a minimum on-time limitation which is around 110ns. Users should take care of minimum limitation on the operating duty cycle under high frequency application.
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SC4624A
POWER MANAGEMENT Operation Information (Cont.) Application
Synchronization Frequency Synchronization operation mode is invoked by using an external clock signal and is activated when the SYNC/EN is pulled and held above 2V and held below 0.8V. The range of synchronization frequency is from 200kHz to 2MHz. A jitter happens when sync pulse clock edge is less than 120ns before the phase switches. It is caused by the ground bounce of synchronization pulse coupled to PWM comparator. Users try to avoid this application. (refer to Figure 9). Power Good Indicator The PGOOD pin is an open-drain and incorporated window comparators output. It's is necessary that a pull-up resistor from the PGOOD pin to the input supply for setting the logic high level of the PGOOD signal. When FB voltage is within +10% setting output voltages typical, the output of power good comparator becomes high impedance after delay time. The PGOOD signal delay time is around 1024/ FOSC. In shutdown mode the power good output is actively pulled low. For example, 1MHz switching frequency applications, the PGOOD delay time is around 1ms. Thermal Shutdown When the junction temperature rises up around 160C, the internal soft start voltage is held low, the internal high side and low side MOSFETs are turned off and the output voltage will fall to zero. Once the junction temperature goes below hysteresis temperature around 10C, the regulator will restart. (refer to Figure 8). Linear Mode Operation (100% duty) The SC4624A can allows 100% duty cycle operation. The Vout is, where IL : Output inductor current. RDSH(ON) : High side P-MOSFET conduction resistance. After the high side PMOS turn on around 30ns, the OCP comparator will compare between V2 and V1. When the converter detects an over current condition (V2 > V1) as shown in Figure 16, the SC4624A proceeds into the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases and the output voltage is monitored. If the over current and low output voltage (set at 60% of nominal output voltage) occur at the same time, the SS pin is pull low by an internal switch and the comp pin is pulled low Test condition: 3.3Vin, 1.2Vo, Io=0 start and the devices stops switching. Assume to 3A from FB = R=F=2.5A/us,T1=T2=0.3ms 0.5V. Once 0V, FB and SS voltage rise forward SS voltage exceeds 0.4V, the hiccup comparator becomes enabled. The hiccup period is around 217/FOSC. (Point C to Point D). attention is internal high side PMOS has minimum off time limitation and is related to duty cycle rate. This condition makes the working duty cycle perform at randon with the output ripple increasing and a poor transient response. Above phenomenon can be improved by larger output capacitor and smaller output inductor. Users need to verify whether above application condition has opposite influence on entire circuit. Over Current Protection A over current setting is programmed by an external resistor (RISET). It goes through internal sense resistor and generates a voltage.
where I : The current is generated by RISET , and it is amplified by internal current amplifier. RONSENSE : Internal sense resistor. Output inductor current goes through internal high side P-MOSFET and generate a voltage.
Transient response
where RL : Output inductor DC resistance. RDSH : Internal high side P-MOSFET resistance. (refer to Figure11). As Vin drops gradually and close to Vout, the buck regulator will go into 100% duty cycle ratio. A matter needing
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For example, with a switching frequency application of
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SC4624A
POWER MANAGEMENT Application information (Cont.)
550kHz, the hiccup period is around 238ms. (refer to Figure 7). A poor layout will make OCP trip point shift and is not easily to calculate by RISET. This is because it is affected by ground bounce, spiker voltage between Vin pin and PH pin, and internal parameter tolerance. Users can refer to Figure 14, it shows how to set maximum output current by RISET. After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation and is given as follows:
Vout
A
B
The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce any copper loss of the inductor, (the core loss can be found in the manufacturer's datasheet).
C
0
0.6 * Vout Vo
The inductor's copper loss can be estimated as follows:
D
Iout
0
Imax
where ILRMS is the RMS current in the inductor. This current can be calculated as follows:
Figure 16. Over Current Protection Characteristic Inductor Selection For a typical SC4624A application, the inductor selection is mainly based on its value, saturation current and DC resistance. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. The inductor value can be determined according to its operating point and the switching frequency as follows:
Output Capacitor Selection Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4624A regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the
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where fs = switching frequency. DI = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is:
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SC4624A
POWER MANAGEMENT Operation Information (Cont.) Application
switching actions. For the continuous conduction mode, the RMS value of the input capacitor can be calculated from:
5 4 3 2 1
D
IN
C1 R1 C2
SC4624A
COMP FB
This current gives the capacitor's power loss as follows:
C
Vout
C8
L1 PH
This capacitor's RMS loss can be a significant part of the total loss in the converter and reduces the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor's ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by:
R
B
C4
R8
R7
R9
A
5
Figure 17. Compensation Network Provides 3 Poles and 2 Zeros
4 3
2
1
For voltage mode step down applications as shown in Figure 17, the power stage transfer function is:
where D = VO/VI , duty ratio. DVI = the given input voltage ripple. Loop Compensation Design For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The SC4624A has an internal error amplifier and requires the compensation network to connect among the COMP pin and FB pin, GND, and the output as shown in Figure 17. The compensation network includes C1, C2, R1, R7, R8 and C8. R9 is used to program the output voltage according to:
where R = load resistance RC = C4's ESR. The compensation network will have these characteristics:
w GCOMP (s) = I s
1+
s s 1+ wZ1 wZ 2 s s 1+ 1+ wP1 wP 2
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SC4624A
POWER MANAGEMENT Operation Information (Cont.) Application
where
I = 1 R 7 (C1 + C 2 )
The design guidelines for the SC4624A applications are as follows: 1. Set the loop gain crossover corner frequency wC for given switching corner frequency wS = 2pfs, 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select wZ1 and wZ2 such that they are placed near wO to damp the peaking and the loop gain has a -20dB/ dec rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel the zero from C4's ESR by a compensator pole wP1 (wP1 = wESR = 1/(RCC4)). 5. Place a high frequency compensator pole wP2 (wP2 = pfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at wC. The compensated loop gain will be as given as show in Figure 18.
Z1 =
1 R1 C2
Z2 =
1 ( R 7 + R 8 ) C8
C1 + C 2 R 1 C1 C 2
P1 =
P 2 =
1 R 8 C9 8
s 1+ 1 1 s s wI VI 1 + 1+ RC C4 VM wZ1 wZ 2 T(s) = GPWM GCOMP (s) G VD (s) = s s L s 1+ 1+ 1 + s 1 + s2L1C wP1 wP 2 R s 1+ 1 1 s s wI VI 1 + 1+ RC C4 VM wZ1 wZ 2 s) P ( s) G VD (= = s s L s 1+ 1+ 1 + s 1 + s2L1C wP1 wP 2 R
After the compensation, the converter will have the following loop gain:
where GPWM = PWM gain. VM = 1.0V, ramp peak to valley voltage of SC4624A.
Figure 18. Asymptotic Diagrams of Power Stage and Loop Gain
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SC4624A
POWER MANAGEMENT Operation Information (Cont.) Application
Layout Guidelines In order to achieve optimal thermal and noise immunity for high frequency converters, special attention must be paid to the PCB layout. The goal of layout optimization is to minimize the high di/dt loops and reduce ground bounce. Output voltage setting, line regulation, stability , switching frequency and OCP trip point shifted are affected by a poor layout. The following guidelines should be used to ensure proper functions of the converters. 1. Both Power ground (PGND) and signal ground (AGND) are separated. 2. A ground plane is recommended to minimize noise and copper losses, and maximize heat dissipation. 3. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. 4. Minimize all high di/dt loops. These loops pass high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. Ground bounce happen to magnetic flux changed and it is proportional to a magnetic filed which goes through high di/dt loops. 5. The input ceramic capacitor (CIN) should be close to PVIN pins and PGND pins. 6. Both input ceramic capacitor gnd and output ceramic capacitor gnd are at same port. 7. A RC snubber circuit between PVIN and PH pins is helpful for stability operation. Be careful with power derating of snubber circuit. 8. The VCC bypass capacitor should be placed next to the VCC and AGND pins. 9. The OCP setting resistor (RISET) and filter capacitor (CISET) should be placed next to the ISET and AGND pins. 10. Feedback divider connects to output connector by Kelvin connection and far away from the noise sources such as switching node and switching components. 11. A multilayer chip beads between AGND and PGND will reduce the ground bounce injected to the "quiet" circuit. It's helpful for stability operation. 12. A large copper area underneath the SC4624 IC is necessary for heat sinking purpose. And multiple layers of large copper area connected through vias can be used for better thermal performance. The size of the vias as the connection between multiple layers should not be too large or solder may seep through
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the big vias to the bottom layer during the re-flow process.
SC4624A
POWER MANAGEMENT Operation Information (Cont.) Application 5 4
5Vin
D
R5 10k R6 10k R2 10R
5VIN, 1VOUT, 4A, all ceramic capacitors ( application circuit #1 )
3
2
1
C6 1nF
C3 1uF 7 6 9
U1
VCC PGOOD SYNC/EN NC COMP FB PH PH PH VCC AGND FS SS NC ISET PVIN PVIN PGND 12 13 5 4 20 3 1 2 15 14 C9 22uF R11 C7 47.5k 47nF R10 0R
C
C1 R1 20k
2.2pF C2 390pF
8 10 11
C5 R3 30k
opt
1Vout@4A
C8 270pF R8 2.32k R7 28.7k
L1
1.8uH
16 17 18 19
C4
R9
PAD
C11
B
22uF
NC
PGND
(2)
R12
28.7k
SC4624A
MLB-160808-0600R-S2
R4
A
opt VIN=5V; Vout=1V/4A opt Switching Frequency=550kHz Note: (1,2) Option for stability L1: TOKO D104C(919AS-1R8N) R12: Multilayer chip inductors; MLB-160808-0600R-S2 Input(C9)/Output Capacitors(C4): Panasonic ECJ33YBOJ226M(22uF/6.3V)
5
4
3
2
1
2008 Semtech Corp.
17
www.semtech.com
SC4624A
POWER MANAGEMENT Operation PCB Layout
Component Side (TOP)
(TOP layer)
(Bottom layer)
(IN1 layer)
(IN2 layer)
2008 Semtech Corp.
18
www.semtech.com
SC4624A
POWER MANAGEMENT
Outline Drawing - MLPQ - 20
A D B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
SEATING PLANE A1 D1 LxN E/2 E1 2 1 C
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.031 .035 .039 .000 .001 .002 - (.008) .007 .010 .012 .154 .157 .161 .100 .106 .110 .154 .157 .161 .100 .106 .110 .020 BSC .012 .016 .020 20 .004 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 20 0.10 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C
N e D/2
bxN bbb CAB
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ - 20
K
DIMENSIONS DIM C G H K P X Y Z INCHES (.156) .122 .106 .106 .020 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80
(C)
H
G
Z
Y X P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
2008 Semtech Corp.
www.semtech.com
19 www.semtech.com

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