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| STA333W 2-channel high-efficiency digital audio system Features ! ! Wide supply voltage range (4.5 V - 18 V) 2 power output configurations - 2 channels of binary PWM (stereo mode) - 2 channels of ternary PWM Power SSO-36 slug down package 2 channels of 24-bit DDX(R) 100 dB SNR and dynamic range Selectable 32 kHz to 192 kHz input sample rates I2C control with selectable device address Digital gain/attenuation +48 dB to -80 dB steps Software volume update Individual channel and master gain/attenuation Individual channel and master software and hardware mute Independent channel volume bypass Automatic zero-detect mute Automatic invalid input detect mute 2-channel I2S input data Interface Selectable clock input ratio Input channel mapping Variable max power correction for lower fullpower 96 kHz internal processing sample rate, 24-bit precision Advanced AM interference frequency switching and noise suppression modes Thermal overload and short-circuit protection embedded PowerSSO36 slug (or exposed pad) down ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Applications ! ! ! ! ! LCD DVD Cradle Digital speaker Wireless speaker cradle Description The STA333W is an integrated solution of digital audio processing, digital amplifier control, and DDX(R)-power output stage, thereby creating a high-power single-chip DDX(R) solution comprising of high-quality, high-efficiency, all digital amplification. The STA333W power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2 channels can be provided by two full-bridges, providing up to 2 x 20 W of power. Also provided in the STA333W are new advanced AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. The STA333W is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker offering cost effectiveness, low power dissipation and sound enrichment. Packing Tube Tape and reel Video application: 576 x fs input mode support Table 1. Device summary Part number STA333W Package PowerSSO36 (slug down) PowerSSO36 (slug down) STA333W13TR May 2007 Rev 1 1/42 www.st.com 42 Contents STA333W Contents 1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 3.3 3.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 6 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Characterization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 6.1.2 6.1.3 6.1.4 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 6.3 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.1 6.3.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Configuration registers (0x00 - 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 Configuration register A (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . 20 Configuration register B (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration register C (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . 25 Configuration register D (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . 26 Configuration register E (address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration register F(address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/42 STA333W Contents 7.2 Volume control registers (addresses 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . 30 7.2.1 7.2.2 7.2.3 7.2.4 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3 7.4 Auto mode registers (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3.1 Auto mode register 2 (address 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Channel configuration registers (addresses 0x0E-0x0F) . . . . . . . . . . . . . 33 7.4.1 7.4.2 0x0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 0x0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5 Variable max power correction registers (addresses 0x27-0x29) . . . . . . . 33 7.5.1 7.5.2 Variable max power correction registers (bits [15:8]) . . . . . . . . . . . . . . . 33 Variable max power correction registers (bits [7:0]) . . . . . . . . . . . . . . . . 33 7.6 Variable distortion compensation registers (addresses 0x29 -0x2A) . . . . 34 7.6.1 7.6.2 Variable distortion compensation register (bits [15:8]) . . . . . . . . . . . . . . 34 Variable distortion compensation register (bits [7:0]) . . . . . . . . . . . . . . . 34 7.7 Fault detect recovery constant registers (addresses 0x2B -0x2C) . . . . . . 34 7.7.1 7.7.2 Fault detect recovery constant register (bits [15:8]) . . . . . . . . . . . . . . . . 34 Fault detect recovery constant register (bits [7:0]) . . . . . . . . . . . . . . . . . 34 7.8 7.9 Device status register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.8.1 Device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reserved registers (address 0x2E - 0x31) . . . . . . . . . . . . . . . . . . . . . . . 35 7.9.1 7.9.2 7.9.3 7.9.4 Reserved register (0x2E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reserved register (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reserved register (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reserved register (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.10 Post scale registers (address 0x32 - 0x33) . . . . . . . . . . . . . . . . . . . . . . . 35 7.10.1 7.10.2 Channel 1 post scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel 2 post scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.11 Output limit register (address 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.11.1 Thermal and over-current warning output limit register . . . . . . . . . . . . . 36 8 9 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3/42 Contents STA333W 10 11 12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 STA333W Block diagram 1 Figure 1. Block diagram Block diagram I2C ctrl I2S interface Power control Logic DDX Volume control Regulators PLL Bias Digital signal processing Power stage Channel 2B Channel 2A Channel 1B Channel 1A Protection current/thermal 5/42 Pin description STA333W 2 Pin description Figure 2. Pin connection (Top view) GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD_REG CONFIG N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD_DIG GND_DIG SCL SDA INT_LINE RESET SDI LRCKI BICKI XTI GND_PLL FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG N.C. N.C. D05AU1638 Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin description Type Gnd I I I/O I/O O Gnd Power O O Power Gnd O Name GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A Substrate ground I2C select address This pin must be connected to GROUND Internal reference at Vcc - 3.3 V Internal Vcc reference Output half bridge 2B Power negative supply Power positive supply Output half bridge 2A Output half bridge 1B Power positive supply Power negative supply Output half bridge 1A Description 6/42 STA333W Table 2. Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin description Pin description (continued) Type Gnd Power I Power Gnd I Power I Gnd I I I I I O I/O I Gnd Power Name GND_REG VDD_REG CONFIG N.C. N.C. N.C. N.C. VDD_DIG GND_DIG PWRDN VDD_PLL FILTER_PLL GND_PLL XTI BICKI LRCKI SDI RESET INT_LINE SDA SCL GND_DIG VDD_DIG Description Internal ground reference Internal 3.3 V reference voltage Paralleled mode command Not connected Not connected Not connected Not connected Positive supply digital Digital ground Power down 0: low-power mode 1: normal operating mode Positive supply for PLL Connection to PLL filter Negative supply for PLL PLL input clock, 256 Fs, or 384 Fs I2S serial clock I2S left/right clock I2S serial data channel Reset Fault interrupt I2C serial data I2C serial clock Digital ground Digital supply 7/42 Electrical specification STA333W 3 3.1 Electrical specification Thermal data Table 3. Symbol Thermal data Parameter Min. Typ. 1.5 150 130 20 Max. 2.0 Unit C/W C C C RTh(j-case) Thermal resistance junction to case (thermal pad) Tsd Tw Thsd Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 3.2 Absolute maximum ratings Table 4. Symbol VCC VDD IL Top Tstg Absolute maximum ratings Parameter Analog supply voltage (pins VCCxA, VCCxB) Digital supply voltage (pins VDD_DIG) Logic input interface Operating junction temperature Storage temperature -0.3 0 -40 Min. Typ. Max. 20 3.6 4 150 150 Unit V V V C C 3.3 Recommended operating condition Table 5. Min. VCC VDD IL Tamb Recommended operating condition Parameter Analog supply voltage (VCCxA,VCCxB) Digital supply voltage (VDD_DIG) Logic input interface Ambient temperature Min. 4.5 2.7 2.7 0 3.3 3.3 Typ. Max. 18.0 3.6 3.6 70 Unit V V V C 8/42 STA333W Electrical specification 3.4 Electrical characteristics Table 6. Electrical characteristics (VCC = 18 V, VDD = 3.3 V, fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified) Parameter Output power BTL THD = 10% Po Output power SE Power Pchannel/Nchannel MOSFET (Total bridge) Power Pchannel/Nchannel leakage Power Pchannel RdsON matching Power Nchannel RdsON matching Low current dead time (static) High current dead time (dynamic) Rise time Fall time Supply voltage operating voltage Supply current from Vcc in PWRDN = 0 power down Ivcc PCM input signal = -60 dBFS Supply current from Vcc in Switching frequency = 384 KHz operation No LC filters Supply current for DDX Internal clock = 49.152 MHz processing (reference only) Supply current in standby ILIM ISC UVL tmin THD+N Over-current limit Short-circuit protection Under-voltage protection threshold Output minimum pulse width Total harmonic distortion and noise No load DXX stereo mode, Po = 1 W, f = 1 kHz 20 Non-linear output Hi-Z output (2) (1) Symbol Conditions THD = 1% Min. Typ. 16 20 Max. Unit RL = 4 , f = 1 kHz, THD = 1% RL = 4 , f = 1 kHz, THD = 10% ld = 1 A Vcc = 18 V ld = 1 A ld = 1 A Resistive load, refer to Figure 3 Refer to Figure 4 Resistive load, refer to Figure 3 Resistive load, refer to Figure 3 4.5 0.03 95 95 W 7 9 180 250 10 m A % % 5 10 8 8 10 20 10 10 18 0.06 0.2 ns ns ns ns V mA RdsON ldss gP gN ILDT IHDT tr tf VCC 30 mA 10 8 2.2 2.7 30 11 3.5 3.8 3.5 30 0.05 50 25 4.3 5.0 4.3 60 0.2 mA mA A A V ns % Ivdd-dig 9/42 Electrical specification Table 6. STA333W Electrical characteristics (continued) (VCC = 18 V, VDD = 3.3 V, fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified) Parameter Conditions A weighted A weighted DXX stereo mode, < 5 kHz, Vripple = 1 V RMS audio input = dither only DXX stereo mode, < 5 kHz, One channel driven at 1 W the other channel measured Po = 2 x 20 W into 8 Min. Typ. 100 dB 90 Max. Unit Symbol Signal to noise ratio in ternary mode SNR Signal to noise ratio in binary mode PSRR Power supply rejection ratio 80 dB XTALK Crosstalk Peak efficiency in DXX mode 80 dB 90 % 1. The ILIM data is for 1 channel of BTL configuration, thus, 2 x ILIM drives the 2-channel BTL configuration. The current limit is active when OCRB = 0 (see Table 24: Over current warning detect adjustment bypass on page 26. When OCRB = 1 then ISC applies. 2. The ISC current limit data is for 1 channel of BTL configuration, thus, 2 x ISC drives the 2-channel BTL configuration. The short-circuit current is applicable when OCRB = 1 (see Table 24: Over current warning detect adjustment bypass on page 26. 10/42 STA333W Testing 4 Testing Figure 3. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50% M58 DTr OUTxY M57 DTf INxY R 8 + - V67 = vdc = Vcc/2 D03AU1458 gnd Figure 4. Current dead time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64 Duty cycle=B DTin(A) INA M57 DTin(B) INB M63 Iout=4A Lout = 1.5 A Q3 Iout=4A Lout = 1.5 A Q4 C71 470nF Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure D03AU1517 11/42 Characterization data STA333W 5 Characterization data Figure 5. Output power 1% THD 30 25 4 ohm 6 ohm output power W 20 15 8 ohm 10 5 0 5 7 9 11 13 15 16 ohm 17 19 supply voltage V Figure 6. FFT 0 dBfs 1 kHz, Vcc = 12 V, RL = 8 +10 +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz 12/42 STA333W Figure 7. FFT -60 dBfs 1 kHz, Vcc = 12 V, RL = 8 Characterization data +10 +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 8. THD vs. Freq, Vcc = 12 V, Po = 1 W 1 0.5 4ohm 0.2 6ohm % 0.1 0.05 0.02 8ohm 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Hz 13/42 Characterization data Figure 9. FFT 0 dBfs 1 kHz, Vcc = 18 V, RL = 8 STA333W +10 +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 10. FFT -60 dBfs 1 kHz, Vcc = 18 V, RL = 8 +10 +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz 14/42 STA333W Figure 11. THD vs. Freq, Vcc = 18 V, Po = 1 W Characterization data 1 0.5 6ohm 0.2 4ohm 0.1 % 0.05 0.02 8ohm 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Hz 15/42 I2C bus specification STA333W 6 I2C bus specification The STA333W supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333W is always a slave device in all of its communications. It supports up to 400 kB/sec rate (fast-mode bit rate). 6.1 6.1.1 Communication protocol Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 6.1.2 Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 6.1.3 Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA333W and the bus master. 6.1.4 Data input During the data input the STA333W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 6.2 Device addressing To start communication between the master and the STA333W, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA333W the I2C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA333W identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 16/42 STA333W I2C bus specification 6.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA333W again responds with an acknowledgement. 6.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the STA333W. The master then terminates the transfer by generating a STOP condition. 6.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 12. Write mode sequence ACK BYTE WRITE START DEV-ADDR RW ACK MULTIBYTE WRITE START DEV-ADDR RW SUB-ADDR ACK DATA IN ACK DATA IN STOP SUB-ADDR ACK DATA IN STOP ACK ACK Figure 13. Read mode sequence ACK CURRENT ADDRESS READ START NO ACK DEV-ADDR RW ACK RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START ACK SEQUENTIAL RANDOM READ START DEV-ADDR RW SUB-ADDR START ACK DEV-ADDR RW ACK DATA ACK DATA DEV-ADDR SUB-ADDR ACK DEV-ADDR DATA STOP ACK DATA NO ACK RW RW= ACK HIGH DEV-ADDR DATA START ACK DATA RW ACK DATA NO ACK STOP STOP ACK DATA STOP NO ACK 17/42 Register description STA333W 7 Table 7. Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Addr 0x1A 0x1B 0x1C 0x1D 0x1E Register description Register summary(1) Name ConfA ConfB ConfC ConfD ConfE ConfF Mute Mvol C1Vol C2Vol Unused Unused Auto Unused C1Cfg C2Cfg Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Name Unused Unused Unused Unused Unused D7 FDRB C2IM OCRB SVE EAPD MV7 C1V7 C2V7 RFU D7 D6 TWAB C1IM ZDE ZCE PWDN MV6 C1V6 C2V6 RFU D6 D5 TWRB CSZ3 DCCV ECLE MV5 C1V5 C2V5 RFU D5 D4 IR1 SAIFB CSZ2 PWMS LDTE MV4 C1V4 C2V4 RFU D4 D3 IR0 SAI3 CSZ1 PSL AME BCLE MV3 C1V3 C2V3 AMAM2 D3 D2 MCS2 SAI2 CSZ0 NSBW IDE C2M MV2 C1V2 C2V2 AMAM1 C1VBP C2VBP D2 D1 MCS1 SAI1 OM1 MPC C1M MV1 C1V1 C2V1 AMAM0 D1 D0 MCS0 SAI0 OM0 MPCV MMute MV0 C1V0 C2V0 AMAME D0 - 18/42 STA333W Table 7. Addr 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 Register description Register summary(1) (continued) Name Unused Unused Unused Unused Unused Unused Unused Unused MPCC1 MPCC2 DCC1 DCC2 FDRC1 FDRC2 Status BIST1 BIST2 BIST3 TSTCTL C1PS C2PS OLIM D7 MPCC15 MPCC7 DCC15 DCC7 FDRC15 FDRC7 PLLUL RFU RFU RFU RFU C1PS7 C2PS7 OLIM7 D6 MPCC14 MPCC6 DCC14 DCC6 FDRC14 FDRC6 FAULT RFU RFU RFU RFU C1PS6 C2PS6 OLIM6 D5 MPCC13 MPCC5 DCC13 DCC5 FDRC13 FDRC5 UVFAULT RO1BACT R01BEND RFU RFU C1PS5 C2PS5 OLIM5 D4 MPCC12 MPCC4 DCC12 DCC4 FDRC12 FDRC4 D3 MPCC11 MPCC3 DCC11 DCC3 FDRC11 FDRC3 D2 MPCC10 MPCC2 DCC10 DCC2 FDRC10 FDRC2 D1 MPCC9 MPCC1 DCC9 DCC1 FDRC9 FDRC1 TFAULT D0 MPCC8 MPCC0 DCC8 DCC0 FDRC8 FDRC0 TWARN OVFAULT OCFAULT OCWARN R5BACT R5BEND R5BBAD RFU C1PS4 C2PS4 OLIM4 R4BACT R4BEND R4BBAD RFU C1PS3 C2PS3 OLIM3 R3BACT R3BEND R3BBAD RFU C1PS2 C2PS2 OLIM2 R2BACT R1BACT R2BEND R1BEND R1BBAD R1BBAD RFU C1PS1 C2PS1 OLIM1 RFU C1PS0 C2PS0 OLIM0 1. RFU: reserved for future use. 19/42 Register description STA333W 7.1 7.1.1 Configuration registers (0x00 - 0x05) Configuration register A (address 0x00) D7 FDRB 0 D6 TWAB 1 D5 TWRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1 Master clock select Table 8. Bit 0 1 2 Master clock select R/W R/W R/W R/W 1 1 0 RST MCS0 MCS1 MCS2 Master clock select: Selects the ratio between the input I2S sample frequency and the input clock. Name Description The STA333W will support sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock will be: " " " 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 9. MCS bits MCS(2..0) IR 101 00 01 1X 576 fs NA NA 100 128 fs 64 fs 32 fs 011 256 fs 128 fs 64 fs 010 384 fs 192 fs 96 fs 001 512 fs 256 fs 128 fs 000 768 fs 384 fs 192 fs Input sample rate fs (kHz) 32, 44.1, 48 88.2, 96 176.4, 192 20/42 STA333W Register description Interpolation ratio select Table 10. Bit 4:3 Interpolation ratio select R/W RST 00 Name IR [1:0] Description Interpolation ratio select: Selects internal interpolation ratio based on input I2S sample frequency. R/W The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 11. IR bit settings as a function of input sample rate IR 00 00 00 01 01 10 10 1st stage interpolation ratio 2 times oversampling 2 times oversampling 2-times oversampling Pass-through Pass-through 2-times downsampling 2-times downsampling Input sample rate Fs (kHz) 32 44.1 48 88.2 96 176.2 192 Thermal warning recovery bypass Table 12. Bit Thermal warning recovery R/W RST Name Description Thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled 5 R/W 1 TWRB If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset. 21/42 Register description STA333W Thermal warning adjustment bypass Table 13. Bit Thermal warning adjustment R/W RST Name Description Thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled 6 R/W 1 TWAB The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3dB output limit (determined by TWOCL in coeff RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0. Fault detect recovery bypass Table 14. Bit Fault detect recovery R/W RST Name Description Fault detect recovery bypass: 0: fault detect recovery enabled 1: fault detect recovery disabled 7 R/W 0 FDRB The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), hold it at 0 for period of time in the range of .1ms to 1 second as defined by the fault detect recovery constant register (FDRC registers 0x292A), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 7.1.2 Configuration register B (address 0x01) D7 C2IM 1 D6 C1IM 0 D5 RES 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0 Serial audio input interface format Table 15. Bit 0 1 2 3 Serial audio input interface format R/W RST 0 0 0 0 SAI0 SAI1 SAI2 SAI3 The serial audio input interface format determines the interface format of the input serial digital audio interface. Name Description R/W R/W R/W R/W 22/42 STA333W Register description 7.1.3 Serial data interface The STA333W audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA333W always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12. The SAI register (configuration register B - 0x01, bits D3-D0) and the SAIFB register (configuration register B - 0x01, bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB first. Available formats are shown in the tables and figure that follow. Serial data first bit Table 16. SAIFB 0 1 Format MSB-first LSB-first Notes Default value Default value Table 17. Support serial audio input formats for MSB first (SAIFB = 0) SAI [3:0] 0000 SAIFB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S 15-bit data Left/right justified 16-bit data I2S 16 - 23-bit data Left justified 16 - 24-bit data Right justified 24-bit data Right justified 20-bit data Right justified 18-bit data Right justified 16-bit data I2S 16 - 24-bit data Left justified 16 - 24-bit data Right justified 24-bit data Right justified 20-bit data Right justified 18-bit data Right justified 16-bit data Interface format BICKI 32fs 0001 0000 0001 48fs 0010 0110 1010 1110 0000 0001 64fs 0010 0110 1010 1110 23/42 Register description Table 18. Supported serial audio input formats for LSB-First (SAIFB = 1) SAI[3:0] 1100 32fs 1110 0100 0100 1000 1100 48fs 0001 0101 1001 1101 0010 0110 48fs 1010 1110 0000 0100 1000 1100 0001 64fs 0101 1001 1101 0010 0110 1010 1110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SAIFB 1 I2S 15-bit data Left/right justified 16-bit data I2S 23-bit data I2S 20-bit data I2S 18-bit data LSB first I2S 16-bit data Left justified 24-bit data Left justified 20-bit data Left justified 18-bit data Left justified 16-bit data Right justified 24-bit data Right justified 20-bit data Right justified 18-bit data Right justified 16-bit data I2S 24-bit data I2S 20-bit data I2S 18-bit data LSB First I2S 16-bit data Left justified 24-bit data Left justified 20-bit data Left justified 18-bit data Left justified 16-bit data Right justified 24-bit data Right justified 20-bit data Right justified 18-bit data Right justified 16-bit data Interface format STA333W BICKI 24/42 STA333W Register description Channel input mapping Table 19. Bit 6 Channel input mapping R/W RST 0 C1IM Name Description 0: processing channel 1 receives left I2S input 1 : processing channel 1 receives right I2S input 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input R/W 7 R/W 0 C2IM Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 7.1.4 Configuration register C (address 0x02) D7 OCRB 1 D6 D5 CSZ3 0 D4 CSZ2 1 D3 CSZ1 0 D2 CSZ0 1 D1 OM1 1 D0 OM0 1 DDX power output mode Table 20. Bit 0 1 DDX power output mode R/W RST 1 1 Name OM0 OM1 Description The DDX power output mode selects configuration of DDX output. R/W R/W The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. The STA50x or STA51x recommended use is OM = 10. Table 21. Output modes Output stage - mode STA50x: drop compensation Discrete output stage: tapered compensation STA50x: full power mode Variable drop compensation (CSZx bits) OM[1:0] 00 01 10 11 25/42 Register description STA333W DDX compensation pulse size register Table 22. Bit 2 3 4 5 DDX compensating pulse size R/W RST 1 0 1 0 Name CSZ0 CSZ1 CSZ2 CSZ3 When OM[1:0]: 11, this register determines the size of the DDX compensating pulse from 0 to 15 clock periods. Description R/W R/W R/W R/W Table 23. Compensating pulse size Compensating pulse size 0 ns (0 ticks) compensating pulse size 20 ns (1 tick) clock period compensating pulse size ... 300 ns (15 ticks) clock period compensating pulse size CSZ(3..0) 0000 0001 ... 1111 Over-current warning detect adjustment bypass Table 24. Bit 7 Over current warning detect adjustment bypass R/W RST 1 Name OCRB Description 0: over current warning adjustment enabled 1: over current warning adjustment disabled R/W The OCWARN input is used to indicate an over current warning condition. When OCWARN is asserted (set to 0), the power control block will force an adjustment to the modulation limit (default -3dB) in an attempt to eliminate the over-current warning condition. Once the over-current warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient RAM. 7.1.5 Configuration register D (address 0x03) D7 MME X D6 ZDE 1 X X X X X X D5 D4 D3 D2 D1 D0 Zero-detect mute enable Table 25. Bit 6 Zero detect mute enable R/W RST 1 Name ZDE Description Setting of 1 enables the automatic zero-detect mute R/W Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) 26/42 STA333W Register description filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 7.1.6 D7 SVE 1 Configuration register E (address 0x04) D6 ZCE 1 D5 DCCV 0 D4 PWMS 0 D3 AME 0 D2 NSBW 0 D1 MPC 1 D0 MPCV 0 Max power correction variable Table 26. Bit 0 Max power correction variable R/W RST 1 Name MPCV Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient R/W Max power correction Table 27. Bit 1 Max power correction R/W RST 1 Name MPC Description Setting of 1 enables STA50x correction for THD reduction near maximum power output. R/W Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1:0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-out channels. Noise-shaper bandwidth selection Table 28. Bit 2 Noise shaper bandwidth selection R/W RST 0 Name NSBW 1: 3rd order NS 0: 4th order NS Description R/W AM mode enable Table 29. Bit 3 AM mode enable R/W RST 0 Name AME Description 0: normal DDX operation 1: AM reduction mode DDX operation R/W The STA333W features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio. 27/42 Register description STA333W PWM speed mode Table 30. Bit 4 PWM speed mode R/W RST 0 Name PWMS Description 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels R/W Distortion compensation variable enable Table 31. Bit 5 Distortion compensation variable enable R/W RST 0 Name DCCV Description 0: uses preset DC coefficient. 1: uses DCC coefficient. R/W Zero-crossing volume enable Table 32. Bit 6 Zero-crossing volume enable R/W RST 1 Name ZCE Description 1: volume adjustments will only occur at digital zero-crossings 0: volume adjustments will occur immediately R/W The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Soft volume update enable Table 33. Bit 7 Zero-crossing volume enable R/W RST 1 SVE Name Description 1: volume adjustments ramp according to SVR settings 0 : volume adjustments will occur immediately R/W 7.1.7 Configuration register F(address 0x05) D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 LDTE 1 D3 BCLE 1 D2 IDE 1 X X D1 D0 Invalid Input detect mute enable Table 34. Bit 2 Invalid input detect mute enable R/W RST 1 IDE Name Description 1: enables the automatic invalid input detect mute R/W Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. 28/42 STA333W Register description Binary output mode clock loss detection Table 35. Bit 3 Binary output mode clock loss detection R/W RST 1 Name BCLE Description Binary output mode clock loss detection enable R/W Detects loss of input MCLK in binary mode and outputs 50% of the duty cycle. LRCK double trigger protection Table 36. Bit 4 LRCK double trigger protection R/W RST 1 Name LDTE Description LRCLK double trigger protection enable R/W Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 37. Bit 5 Auto EAPD on clock loss R/W RST 0 Name ECLE Description Auto EAPD on clock loss R/W When active will issue a power device power down signal (EAPD) on clock loss detection. IC power down Table 38. Bit 6 Power down R/W RST 1 Name PWDN Description 0: IC power down low-power condition 1: IC normal operation R/W The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block will be gated. This places the IC in a very low power consumption state. External amplifier power down Table 39. Bit 7 External amplifier power down R/W RST 1 Name EAPD Description 0: external power stage power down active 1: normal operation R/W The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). 29/42 Register description STA333W 7.2 7.2.1 Volume control registers (addresses 0x06 - 0x0A) Mute/line output configuration register D7 D6 D5 D4 D3 D2 C2M 0 D1 C1M 0 D0 MMUTE 0 Master mute Table 40. Bit 0 Master mute R/W RST 0 Name MMUTE Description 0: normal operation 1: all channels are in mute condition R/W Channel mute Table 41. Bit Channel mute R/W RST Name Description Channel 1 mute: 0: no mute condition. It is possible to set the channel volume 1: Channel 1 in hardware mute Channel 2 mute: 0: no Mute condition. It is possible to set the channel volume 1: Channel 2 in hardware mute 1 R/W 0 C1M 2 R/W 0 C2M 7.2.2 Master volume register D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1 7.2.3 Channel 1 volume D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0 30/42 STA333W Register description 7.2.4 Channel 2 volume D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0 The volume structure of the STA333W consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to - 80 dB. As an example if C3V = 0x00 or + 48 dB and MV = 0x18 or - 12 dB, then the total gain for channel 3 = + 36 dB. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes(CxM) will mute only that channel. Both the master mute and the channel Mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate(~96 kHz). A "hard mute" can be obtained by commanding a value of all 1's (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than - 80 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates will occur immediately. Table 42. Master volume offset as a function of MV[7:0] MV(7..0) 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01001100 (0x4C) ... 11111110 (0xFE) 11111111 (0xFF) Volume offset from channel value 0 dB -0.5 dB -1 dB ... -38 dB ... -127.5 dB Hard master mute Table 43. Channel volume as a function of CxV[7:0] CxV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) Volume +48 dB +47.5 dB +47 dB ... +0.5 dB 0 dB -0.5 dB 31/42 Register description Table 43. Channel volume as a function of CxV[7:0] (continued) ... 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) ... 11101100 (0xEC) 11101101 (0xED) ... 11111111 (0xFF) ... -59.5 dB -60 dB -61 dB -62 dB ... -80 dB Hard channel mute ... Hard channel mute STA333W 7.3 7.3.1 Auto mode registers (0x0C) Auto mode register 2 (address 0x0C) D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0 AM interference frequency switching Table 44. Bit 0 AM interference frequency switching R/W RST 0 Name AMAME Description 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM setting R/W AMAM bits Table 45. AutoMode AM switching frequency selection 48 kHz / 96 kHz input Fs 0.535 MHz - 0.720 MHz 0.721 MHz - 0.900 MHz 0.901 MHz - 1.100 MHz 1.101 MHz - 1.300 MHz 1.301 MHz - 1.480 MHz 1.481 MHz - 1.600 MHz 1.601 MHz - 1.700 MHz 44.1 kHz / 88.2 kHz input Fs 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz AMAM[2:0] 000 001 010 011 100 101 110 32/42 STA333W Register description 7.4 7.4.1 Channel configuration registers (addresses 0x0E-0x0F) 0x0E D7 D6 D5 D4 D3 D2 C1VPB 0 D1 D0 7.4.2 0x0F D7 D6 D5 D4 D3 D2 C2VPB 0 D1 D0 Volume bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. 7.5 Variable max power correction registers (addresses 0x270x29) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 7.5.1 Variable max power correction registers (bits [15:8]) D7 MPCC15 0 D6 MPCC14 0 D5 MPCC13 0 D4 MPCC12 1 D3 MPCC11 1 D2 MPCC10 0 D1 MPCC9 1 D0 MPCC8 0 7.5.2 Variable max power correction registers (bits [7:0]) D7 MPCC7 1 D6 MPCC6 1 D5 MPCC5 0 D4 MPCC4 0 D3 MPCC3 0 D2 MPCC2 0 D1 MPCC1 0 D0 MPCC0 0 33/42 Register description STA333W 7.6 Variable distortion compensation registers (addresses 0x29 0x2A) DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. 7.6.1 Variable distortion compensation register (bits [15:8]) D7 DCC15 1 D6 DCC14 1 D5 DCC13 1 D4 DCC12 1 D3 DCC11 0 D2 DCC10 0 D1 DCC9 1 D0 DCC8 1 7.6.2 Variable distortion compensation register (bits [7:0]) D7 DCC7 0 D6 DCC6 0 D5 DCC5 1 D4 DCC4 1 D3 DCC3 0 D2 DCC2 0 D1 DCC1 1 D0 DCC0 1 7.7 Fault detect recovery constant registers (addresses 0x2B 0x2C) FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 0.1 ms. 7.7.1 Fault detect recovery constant register (bits [15:8]) D7 FDRC15 0 D6 FDRC14 0 D5 FDRC13 0 D4 FDRC12 0 D3 FDRC11 0 D2 FDRC10 0 D1 FDRC9 0 D0 FDRC8 0 7.7.2 Fault detect recovery constant register (bits [7:0]) D7 FDRC7 0 D6 FDRC6 0 D5 FDRC5 0 D4 FDRC4 0 D3 FDRC3 1 D2 FDRC2 1 D1 FDRC1 0 D0 FDRC0 0 34/42 STA333W Register description 7.8 7.8.1 Device status register (address 0x2D) Device status register D7 PLLUL D6 FAULT D5 UVFAULT D4 OVFAULT D3 OCFAULT D2 OCWARN D1 TFAULT D0 TWARN This read-only register provides fault and thermal-warning status information from the power control block. 7.9 7.9.1 Reserved registers (address 0x2E - 0x31) Reserved register (0x2E) D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES 7.9.2 Reserved register (0x2F) D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES 7.9.3 Reserved register (0x30) D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES 7.9.4 Reserved register (0x31) D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES 7.10 7.10.1 Post scale registers (address 0x32 - 0x33) Channel 1 post scale D7 C1PS7 0 D6 C1PS6 1 D5 C1PS5 1 D4 C1PS4 1 D3 C1PS3 1 D2 C1PS2 1 D1 C1PS1 1 D0 C1PS0 1 35/42 Register description STA333W 7.10.2 Channel 2 post scale D7 C2PS7 0 D6 C2PS6 1 D5 C2PS5 1 D4 C2PS4 1 D3 C2PS3 1 D2 C2PS2 1 D1 C2PS1 1 D0 C2PS0 1 The STA333W provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel, which can be used to limit the maximum modulation index and therefore the peak current through the power device. The register values represent an 8-bit signed fractional number. This number is extended to a 24-bit number by adding zeros to the right and then directly multiplied by the data on that channel. An independent post-scale is provided for each channel but all channels can use the channel 1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7F (pass-through). 7.11 7.11.1 Output limit register (address 0x34) Thermal and over-current warning output limit register D7 OLIM7 0 D6 OLIM6 1 D5 OLIM5 0 D4 OLIM4 1 D3 OLIM3 1 D2 OLIM2 0 D1 OLIM1 1 D0 OLIM0 0 The STA333W provides a simple mechanism for reacting to a thermal or over-current warning in the power-device. When the TWARN or OCWARN input is asserted, the OLIM setting is used to limit the output to that value. The default setting of 0x5A provides -3dB limit. The limit in this situation can be adjusted by modifying the thermal warning/overcurrent output limit value. If the cause of the limiting was a thermal warning, the output limiting is removed when the thermal warning situation disappears. If the cause of the limiting was an over-current warning, the output limiting remains in effect until the device is reset. 36/42 STA333W Application 8 Application Figure 14. Application diagram 22H 19 20 100nF 2.7 21 VDD_DIG 22 GND_DIG 3.9K 100nF 1.2nF 220pF 100pF 23 POWRDN 24 PLL_VDD 25 PLL_FILTER 26 PLL_GND 27 XTI 28 BICKI 29 LRCKI 30 SDI 31 RESET 32 INT_LINE 33 SDA 34 SCL 100nF 35 GND_DIG 36 VDD_DIG 2.7 18 17 CONFIG 16 VDD_REG 15 GND_REG 14 OUT1A 13 GND1 12 VCC1 11 OUT1B 10 OUT2A VCC2 GND2 OUT2B VCC_REG VSS_REG TESTMODE SA GND_SUB 100nF 330pF 6.2 100nF 22 100nF 1F 6.2 100nF 100nF 8 100nF 470nF 22H 22H 9 8 7 6 5 4 3 2 1 100nF 22 100nF 1F 100nF 100nF 6.2 6.2 100nF 100nF 470nF 8 330pF VDD STA333W 1000F 22H VCC 37/42 Package thermal characteristics STA333W 9 Package thermal characteristics A thermal resistance of 25 C/W can be achieved using a ground copper area of 3 x 3 cm, and using 16 vias, on the PCB (see Figure 15). The amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA333W is 3 W. This gives, with the suggested board copper area, a maximum Tj of 75 C. This gives a safety margin before the thermal protection intervention is invoked (Tj = 150 C) in consumer environments where a 50 C is the maximum ambient temperature. Figure 15. Thermal characteristics 38/42 STA333W Package information 10 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK specifications are available at: www.st.com. Figure 16. PowerSSO36 slug down package information DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h k L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.5 8.5 2.3 0.10 0.06 10.50 0.40 5 0.55 4.3 10 1.2 0.8 2.9 3.65 1.0 4.1 6.5 4.7 7.3 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.287 0.90 0.022 0.169 10 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.019 0.335 0.090 0.004 0.002 0.413 0.016 5 0.035 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299 Outline and mechanical data 10.10 0.398 PowerSSO-36 Exposed pad (or slug) down (1) "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006") A2 A hx45u G LEAD COPLANARITY A D e stand-off a1 T Y M Gauge plane 0.25 L O E H F U B 0.1 M A B b e3 S BOTTOM VIEW X 7587131 A k c Q 39/42 Trademarks and other acknowledgements STA333W 11 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics. 40/42 STA333W Revision history 12 Revision history Table 46. Date 25-May-2007 Document revision history Revision 1 Initial release. Changes 41/42 STA333W Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 42/42 |
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