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STB5701
350 to 400 MHz FSK/ASK receiver (ST-RECORD01 family)
Preliminary Data
Features

Multiband receiver: 350MHz to 400MHz FSK/ASK modulation selection Programmable multichannel High dynamic range with On-Chip AGC PLL and fully VCO integrated Image Rejection Mixer integrated Start Code Detector block (SCD) I2C serial interface (standard mode/fast mode) BiCMOS SiGe technology VQFN package 5 x 5 mm
Description
This device is a single chip FSK/ASK receiver optimized for licence-free ISM band operations from 350MHz to 400 MHz. It can easily be configured to provide the optimal solution for the user's application like Set Top Box and 350/400 MHz ISM Band Systems.
Applications

350 to 400 MHz ISM Band System Set Top Box
Table 1.
Device summary
Order codes Package Tray QFN32L STB5701 Tape & Reel STB5701TR
October 2007
Rev 1
1/35
www.st.com 35
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STB5701
Contents
1 2 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Programmable Phase Locked Loop synthesizer (PLL) . . . . . . . . . . . . . . 18
4.2.1 4.2.2 4.2.3 4.2.4 Divider (a-counter, m-counter and prescaler) . . . . . . . . . . . . . . . . . . . . 18 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
Receiver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Image Rejection Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ASK/FSK demodulator and data filter . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Min /Max peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4
Digital control and source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 4.4.2 4.4.3 State pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MODE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 4.6 4.7 4.8
Start code detection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Detailed display description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 5.2 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 QFN32L (5mm x 5mm) information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/35
STB5701
Contents
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3/35
List of tables
STB5701
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings (Tamb = 25oC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C reserved addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C address breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C mapped top level registers - summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C mapped SCD registers - summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DIG_config register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RF_Config register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PLL_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PLL_M register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PLL_R register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCD_config register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCD_status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SCD_code register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SCD_code_lenth register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SCD_symbol_min_time register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SCD_symbol_max_time register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SCD_symbol_nom_time register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SCD_prescaler register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt_enable register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt_clear register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timeout register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 QFN32L (5mm x 5mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/35
STB5701
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LNA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mixer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ASK/FSK demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Digital section block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 START code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 QFN32L (5mm x 5mm) dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/35
1
6/35
Figure 1.
10.7 MHz Ceramic Filter
32 GND_LNA
FSK_Discr Pin 21
Block diagram and pin configuration
Block diagram
(31) Vcc_MIX
(30 Vcc_IF
(29) IF 1
(28) TEST_EN
(27) IF 2
(26) RSSI_OUT
(25) SAD
sI
(1) IN_LNA
RFAmp
FSK Demodulator Chan_Filter1 (24)
(2) VCC_LNA
Image Rejection Mixer
RSSI
sQ
I2C (LNA_GAIN)
(3) VCC_Div
Threshold
Delay
ASK
I2C (ASK_NOTFSK)
FSK
Chan_Filter2 (23)
Clk
(4) VCC_XTAL
I2C (PLL_A, PLL_M)
Chan_Filter3 (22)
(5) XTAL2
Pierce Crystal Oscillator
1N
PF D CP
PLL S ynthetizer
VCO
Clk
Test_EN Pin 28
:2
SAD Pin 25
FSK_Discr (21)
Data Slicer
(6) XTAL1
I2C (PLL_R)
1 R
Digital S ection
10.7 MHz Discriminator
Mean Peak Detector Min
Block diagram and pin configuration
(20) PK1
V cc V cc
SCD
Max
CK_OUT (7)
Clk
I2C (CLKOUT_ENABLE)
TANK
I2C Interface
PK2 (19)
notReset 18 DOUT (17)
(8) LF
VCC_VCO (9)
EN_Xtal 10
NC (11)
SCL (12)
SDA (13)
STATE (14)
IR_IN (15)
Vcc_Dig (16)
STB5701
STB5701 Table 2.
Pin
Block diagram and pin configuration Pin description
Name I/O type I/O schematic Description
Vcc
32
GND_LNA
GND
IN_LNA
Vcc
Low Noise Amplifier ground
GND_LNA
1 2 3 4
IN_LNA Vcc_LNA Vcc_Div Vcc_XTAL
I Vcc Vcc Vcc
Vcc Vcc
Low Noise Amplifier input Low Noise Amplifier supply voltage Divider supply voltage Crystal supply voltage
5
XTAL2
O
XTAL2
2nd Crystal input
Vcc Vcc Vcc
6
XTAL1
I
XTAL1
1st Crystal input
Vcc
7
CK_OUT
O
CK_OUT
Clock output
Vcc
Vcc
LPF
8
LPF
I/O
Loop filter
9
Vcc_VCO
Vcc
Vcc
VCO supply voltage
10
EN_XTAL
I
EN_Xtal
Crystal oscillator enable
11
NC
Not connected
7/35
Block diagram and pin configuration Table 2.
Pin
STB5701
Pin description (continued)
Name I/O type I/O schematic
Vcc Vcc
Description
12
SCL
I
SCL
I2C clock
Vcc
13
SDA
I
SDA
Vcc
I2C data In/Out
Vcc
14
STATE
O
STATE
High when selecting UHF
Vcc Vcc
15
IR_IN
I
IR_IN
From external IR source
16
Vcc_Dig
Vcc
Vcc
Digital section supply voltage
17
DOUT
O
DOUT
Digital serial output
Vcc Vcc
18
NotReset
I
notReset
Global reset, active low
8/35
STB5701 Table 2.
Pin
Block diagram and pin configuration Pin description (continued)
Name I/O type I/O schematic
Vcc
Description
PK2
Vcc
19
PK2
I/O
Max. peak detector
Vcc Vcc
20
PK1
I/O
PK1
Min. peak detector
21 FSK_Discrim
I/O
FSK discriminator
FSK_Discr
Vcc Vcc
22
Chan_Filter3
I/O
Chan_Filter3
Channel filter
Vcc
Vcc
23
Chan_Filter2
I/O
Chan_Filter2
Channel filter
Vcc
24
Chan_Filter1
I/O
Chan_Filter1
Channel filter
Vcc Vcc
25
SAD
I
SAD
I2C address selection
9/35
Block diagram and pin configuration Table 2.
Pin
STB5701
Pin description (continued)
Name I/O type I/O schematic
Vcc
Description
26
RSSI_OUT
O
RSSI_OUT
Radio strength signal indicator output
Vcc
27
IF2
I
IF2
External IF filter input
Vcc Vcc
28
Test_EN
I
TEST_EN
Test mode enable
Vcc
Vcc
29
IF1
O
IF1
External IF filter output
30 31 EP
Vcc_IF Vcc_MIX GND
Vcc Vcc GND
IF supply voltage Mixer supply voltage Ground
10/35
STB5701 Figure 2. Test circuit
Block diagram and pin configuration
GND
1
2
EN_XTAL
NC
SCL
SDA
11/35
Block diagram and pin configuration Table 3.
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R2 R3 R4 R5 R6 R7 L1 X1 F1 F2
STB5701
Bill of material
Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 CS10 Manufacturer MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA NEOHM NEOHM NEOHM NEOHM NEOHM NEOHM NEOHM MURATA CITIZEN Toko Toko Part number Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series GRM39 Series CRG0603 Series CRG0603 Series CRG0603 Series CRG0603 Series CRG0603 Series CRG0603 Series CRG0603 LQP18M CS1027.000MABJTR SK107M2N-A0-20X CDF107F-AO-022 Description LNA Input matching Crystal load capacitor Crystal load capacitor Loop filter capacitor Loop filter capacitor Peak detector capacitor Peak detector capacitor FSK Discriminator Tuning Channel filter capacitor Channel filter capacitor RSSI output low path capacitor IF Filter DC Block IF Filter DC Block Resistor load capacitor Loop filter resistor Peak detector resistor Peak detector resistor RSSI output resistor IF Filter Matching IF Filter Matching LNA input matching Crystal Ceramic filter Ceramic resonator
12/35
STB5701
Electrical specifications
2
2.1
Electrical specifications
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 4.
Symbol VCC Tj Tstg Supply voltage Junction temperature Storage temperature
Absolute maximum ratings (Tamb = 25oC)
Parameter Value 4.5 -40 to 150 -55 to + 150 Unit V
oC oC
2.2
Thermal data
Table 5.
Symbol Ta th
Thermal data
Parameter Operating temperature Thermal resistance junction to ambient Value 0 + 70 40 Unit
oC oC/W
13/35
Electrical characteristics
STB5701
3
Electrical characteristics
(VCC = 3.3 V, Zs = 50 , Ta = 25 oC, unless otherwise specified). Table 6.
Symbol Vcc frx f
Electrical characteristics
Parameters Supply voltage Receive frequency range FSK frequency deviation FSK receive current consumption High gain LNA En_Xtal (PIN 10) high / floating En_Xtal (PIN 10) low FSK data rate (Manchester encoding) Test conditions Min. 2.7 350 25 37.5 Typ. 3.3 Max. 3.6 400 50 Unit V MHz kHz
Irx_FSK
25
mA
5
mA
Standby current Icc_standby consumption
RF Enable bit=0
20 2 10 0 10
A kbps dB dBm
RLin
Input return loss Max RF power input RF1 =369.5MHz RF2 = 371.1MHz RF3 = 375.3MHz RF4 = 376.9MHz RF5 = 388.3MHz RF6 = 391.5MHz RF7 = 394.3MHz RF8 = 395.9MHz RFX +/-30KHz Channel blocking (1) Image Rejection +/-1MHz +/-6MHz
Pmin
Input sensitivity
2 kbps manchester encoding BER 10-3 BW = 300KHz FSK 37.5 KHz deviation
-109
dBm
-103 50 50 35
dBm dBc dBc dB
I2C I/O pins VIH VIL Input logic voltage high Input logic voltage low 0.7 Vcc -0.5 3.6 0.3Vcc V V
14/35
STB5701 Table 6.
Symbol VOL
Electrical characteristics Electrical characteristics (continued)
Parameters Output logic voltage low Hysteresis of schmitt trigger for inputs Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Input current each I/O pin with an input voltage between 0.1Vcc and 0.9Vcc Capacitance for each I/O pin Capacitive load for each bus line 0.05 Vcc Test conditions Min. Typ. Max. 0.4 Unit V
VHYST
V
tof
20+ 0.1Cb
250
ns
Ii
-10
10
A
Ci Cb
10 400
pF pF
I2C Standard mode fSCL tSU_STA tHD_STA tHIGH tLOW SCL clock frequency Setup time for START condition Hold time for START condition SCL high time SCL low time 0 4.7 4 4 4.7 250 0 3.45 1000 300 4 100 kHz s s s s ns s ns ns s
tSU_DAT DATA setup time tHD_DAT tR tF tSU_STO DATA hold time SDA, SCL rise time SDA, SCL fall time Setup time for STOP condition Bus free time between STOP and START condition
tBUF
4.7
s
15/35
Electrical characteristics Table 6.
Symbol
STB5701
Electrical characteristics (continued)
Parameters Test conditions Min. Typ. Max. Unit
I2C Fast mode fSCL tSU_STA tHD_STA tHIGH tLOW SCL clock frequency Setup time for START condition Hold time for START condition SCL high time SCL low time 0 0.6 0.6 0.6 1.3 100 0 0.9 300 300 0.6 400 kHz s s s s ns s ns ns s
tSU_DAT DATA setup time tHD_DAT tR tF tSU_STO DATA hold time SDA, SCL rise time SDA, SCL fall time Setup time for STOP condition Bus free time between STOP and START condition
tBUF
1.3
s
1.
Desired signal 10dB above the input sensitivity level, CW interferer power level increased until BER -3 10
16/35
STB5701
Functional description
4
4.1
Functional description
General description
The STB5701 FSK/ASK receiver is a heterodyne configuration (10.7 MHz IF Frequency) and it is designed for applications in the 350MHz to 400MHz frequency range and includes ASK and FSK detectors. The synthesizer has a typical channel spacing of better than 100 kHz and uses a integrated fully VCO. With the STB5701 receiver chip, various circuit configurations can be arranged in order to meet a number of different customer requirement. The STB5701 is housed in a VQF package 5mm x 5mm 32 leads. The STB5701 receiver IC consists of the following building blocks:

Phase Locked Loop Synthesizer (PLL): M-Counter, A-Counter, Prescaler, PhaseFrequency Detector (PFD), Charge Pump (CP), Voltage Controlled Oscillator (VCO). Programmable reference divider for crystal and channel step selection. Low Noise Amplifier (LNA) with AGC function for high sensitivity and dynamic range RF signal reception. Image Rejection Mixer for down conversion of the RF signal to the IF (without external saw image filter). IF amplifier to amplify and limit the IF signal and for RSSI generation. Phase coincidence demodulator to demodulate the IF signal. Operation amplifier for data slicing, filtering and ASK detection. Min/max peak detector to create a DC output voltage equal to the mean of the min and max peak value of the data signal. I2C bus to exchange data between the STB5701 and the micro. Start code detector (SCD) to recognize a valid data signal to prevent continuos toggling of data in the absence of an RF Signal due to the noise. Bias circuitry for band gap biasing and circuit shutdown.
17/35
Functional description
STB5701
4.2
Programmable Phase Locked Loop synthesizer (PLL)
Figure 3. PLL block diagram
Image Rejection Mixer
(3) VCC_Div
f VCO
(4) VCC_XTAL
Pierce Crystal Oscillator f XTAL
I2C (PLL_A, PLL_M)
:2
(5) XTAL2
1N
1R
I2C (PLL_R)
fN
PLL Synthetizer
2 f VCO
PFD CP
fR
(6) XTAL1
VCO
CK_OUT (7)
Clk
I2C (CLKOUT_ENABLE)
TANK
(8) LF
VCC_VCO (9)
EN_Xtal 10
NC (11)
The synthesized programmable local oscillator is a Phase Locked Loop (PLL) using a 'parallel-resonant' quartz crystal as frequency reference. The PLL block contains a phase detector, charge pump, VCO, Programmable N and R Divider and a Crystal Oscillator. The synthesized frequency (fVCO) is set by programming the 'N' Divider through the I2C interface (PINs 12, 13).
fR = fXTAL / R fVCO = N fN = N . fR = (N / R) . fXTAL
.
4.2.1
Divider (a-counter, m-counter and prescaler)
The main divider (N) of the PLL contains a 3-bit A-counter, a 10-bit M-counter and an 8/9 prescaler. The divider ratio of the prescaler is controlled by the program counter and the swallow counter. During one cycle, the prescaler divides by 9 until the swallow A-counter reaches its terminal count. Afterwards the prescaler divider by 8 until the program counter reaches its terminal count. Therefore the overall feedback divider ratio can be expressed as: N = 9 . A + 8 . (M - A)
18/35
STB5701
Functional description The A-counter configuration represents the lower bits in the feedback divider register and the upper bits the M-counter configuration respectively. According to that, the following counter ranges are implemented:
0 A 7 7 M 1023
and therefore the range of the overall feedback divider ratio results in:
56 N 8191
The user does not need to care about the A- and M-counter settings. It is only necessary to know the overall feedback divider ratio N to program the register settings.
4.2.2
Reference divider
The reference divider reduces the frequency of the external crystal (FXTAL) to an internal reference frequency (FR) used for the phase-locked loop. This value, corresponding to the channel step, it is set by programming a 10-bit counter through the I2C interface (PINs 12, 13). Therefore the range of the Reference divider ratio is:
0 R 1023
4.2.3
Phase Frequency Detector
The phase detector (PFD) is a device that compares two input (fN and fR) phases, generating an output that is a measure of their phase difference. The gain of the phase detector can be expressed as:
KPD = ICP / 2 where ICP is the charge pump current. If fR doesn't equal fN, the phase-error signal, after being filtered and amplified, causes the VCO frequency to deviate in the direction of fR.
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Functional description
STB5701
4.2.4
Loop filter
An external PLL loop filter is connected to pin LF (PIN 8). The loop filter controls the dynamic behavior of the PLL, primarily lock time and reference spur levels. Generally, the PLL lock time is a small fraction of the overall receiver start-up time. The crystal oscillator is the largest contributor to start-up time.
4.3
Receiver section
The integrated receiver is intended to be used as a single-conversion FSK/ASK receiver. It consists of a low noise amplifier, mixer, IF filter, limiter, FSK demodulator, a LPF amplifier, and a data slicer. The received strength signal indicator (RSSI) can be used for fast carrier sense detection or as amplitude shift keying, (ASK) demodulator.
4.3.1
Low Noise Amplifier (LNA)
Figure 4. LNA block diagram
32 GND_LNA
(1) IN_LNA
Image Rejection Mixer
(2) VCC_LNA
I2C (LNA_GAIN)
RSSI
Delay Clk
Threshold
The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The LNA output is directly connected to the mixer removing the external output matching. It has 2 step gain managed by an internal AGC. This AGC circuit monitors the RSSI output. The AGC has a hysteresis of ~10dB.
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STB5701
Functional description
4.3.2
Image Rejection Mixer
Figure 5. Mixer block diagram
(31) Vcc_MIX
sI
LNA IF Filter
RFAmp
sQ
Image Rejection Mixer
I2C (SC_FILTER)
VCO
An excellent feature of the STB5701 is the integrated image rejection mixer. This device was designed to eliminate the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost.The mixer cell is a pair of double-balanced mixers that perform an IQ down conversion of the 350-400MHz RF input to the IF (10.7MHz) with low-side injection (i.e., fRF = fLO - fIF). The Image Rejection circuit combines these signals to achieve ~35dB of Image Rejection over the full temperature range. Low-side injection is required due to the on-chip Image Rejection architecture.
4.3.3
ASK/FSK demodulator and data filter
The received signal strength indicator (RSSI) voltage is proportional to the log of the downconverted RF signal at the IF limiting amplifier input. It also used as demodulator for amplitude-shift \ keying (ASK) modulation. The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The ASK or FSK modulation selection is set by I2C interface. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 80 dB higher compared to the RF input signal at full sensitivity. In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier but at FSK receive mode the RSSI output provides a field strength indication. Coming from the RSSI the FSK signal is fed to the input of the FSK demodulator. After buffering the signal is fed to a phase discriminator. The phase shift is generated by an external 10.7MHz Ceramic discriminator connected to FSK_Discr. (PIN 21). The FSK demodulator is intended to be used for an FSK deviation of 37.5 kHz. Lower values may be used but the sensitivity of the receiver is reduced in that condition. After demodulation a 2nd order Sallen and Key filter is provided in order to suppress unwanted frequency components.
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Functional description Figure 6. ASK/FSK demodulator block diagram
STB5701
FSK_Discr Pin 21
RSSI
FSK Demodulator Chan_Filter1 (24)
RSSI
ASK
I2C (ASK_NOTFSK)
FSK
Chan_Filter2 (23)
Chan_Filter3 (22)
FSK_Discr (21)
Data Slicer
10.7 MHz Discriminator
Mean Peak Detector Min Max
SCD
(20) PK1
V cc V cc
PK2 (19)
notReset
18
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STB5701
Functional description
4.3.4
Min /Max peak detector
The peak detector embedded in the STB5701, in conjunction with an external RC filter (PINs 22, 23, 24), generates a DC output voltage equal to the mean of the min and max peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data filter output voltage.
4.3.5
Data slicer
The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data filter output. The other path is fed to the min/max Peak detector to derive the average value (DC component) as an adaptive slice reference which is presented to the positive comparator input. The adaptive reference allows detecting the received data over a large range of noise floor levels.
4.4
Digital control and source selection
Figure 7. Digital section block diagram
Clk
Test_EN Pin 28
SAD Pin 25
Digital Section
Data Slicer
I2C Interface
SCD
notReset
18
DOUT (17)
SCL (12)
SDA (13)
STATE (14)
IR_IN (15)
Vcc_Dig (16)
The STB5701 digital section is responsible for the following functions:

Configuration of the RF front end through software programmable config bits. Configuration of the PLL through software programmable registers (PLLA,M,R). Detection of a pre-programmed start code sequence (one of two possibilities). Arbitration between UHF and IR sources.
The serial data emerges from the DATA output pin (PIN 17) and the system state emerges from the STATE output pin (PIN 14).
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Functional description
STB5701
4.4.1
State pin
The STATE output pin may be configured in one of two ways:

To reflect the state of the start code detection block officiated = detected, 0 = searching or off), the state can be cleared by a programmable time out or a software reset. To operate as a true interrupt with associate status bit and a software clearing mechanism.
The state output may be optionally inverted.
4.4.2
Data pin
The DATA output pin is driven by one of two sources:

The IR_IN pin. The UHF input from the RF front end.
4.4.3
MODE register
The DATA source selected at any time is governed by the MODE register, the options are as follows:

IR_IN only, direct connection. UHF only, direct connection. IR triggered, the output is zero and switched to UHf on detection of a valid start code. IR/UHF arbitrated, the output comes by default from IR_IN, however on detection of a valid start code the output is switched to select the UHF source. The switch back to IR is accomplished in one of two ways.
A software reset is programmed. The time-out counter has been set and has timed out.
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STB5701
Functional description
4.5
Start code detection example
This section explains the operation of the start code detector with reference to the start code sequence illustrated in the following figure: Figure 8. START code
12 11 10
9
8
7
654
32
1
0
1 ms 500 s
2 ms
1 ms
2 ms
Firstly we assume the nominal symbol duration is 500 s, in this example there are then 13 symbol (denoted as 12 to 0 in the figure above). If the device is operating from a 27 Mhz external clock then we program the prescaler to 27. The internal sampling clock will be 1Mhz and the sampling resolution will be 1us. To add some error tolerance we also program an upper and lower bound on the symbol duration as well as the nominal value. In this case 400 (corresponding to 400us) in SCD_symbol_min_time register, 500 (corresponding to 500us) in SCD_symbol_nom_time and 600 (corresponding to 600us) in SCD_symbol_max_time. Now we program 0b1001111001111 into the SCD_code register and 13 (0x0d) corresponding to 13 symbols to be detected into the SCD_code_length register. The start code detection is started by setting the enable and research bits in SCD_config register to `1'. The start code detector checks for the minimum symbol time of each symbol and the sequence in which symbols are received. If the symbol time is not respected by the input (incase of noise) the start code detection is re-initialized. The detector is capable of simultaneously searching for two different start codes, the alternative code is written into the upper 16 bits of SCD_code register.
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Functional description
STB5701
4.6
Registers list
Two unique I2C addresses have been reserved for the STB5701 device, the appropriate one is selected using the SAD input pin. Table 7.
SAD 0 1 (spare) 0110010x Unique to this device. 0110011x
I2C reserved addresses
Address
4.7
Register summary
The I2C mapped address space of the STB5701 is given below: Table 8. I2C address breakdown
Group Top Level SCD Block Description See table 9 below See table 10 below
Base address 0x00 0x80
Table 9.
Address 0x00 0x04 0x08 0x0C 0x10
I2C mapped top level registers - summary
Name DIG_config RF_config PLL_A PLL_M PLL_R Reset value 0x00000000 Digital configuration 0x00000000 Configure RF front end 0x00000000 PLL post divider 0x00000000 PLL feedback divider 0x00000000 PLL reference divider Function
Table 10.
Address 0x80 0x84 0x88 0x8C 0x90 0x94 0x98
I2C mapped SCD registers - summary
Name Scd_config Scd_status Scd_code Scd_code_length Scd_symbol_min_time Reset value Function
0x00000000 SCD configuration register. 0x00000000 SCD status can be read from this register. 0x00000000 Expected Start code is stored in this register. 0x00000000 0x00000000 Length of the start code is stored in this register. Minimum time of the symbol is stored in this register. Maximum time of the symbol is stored in this register.
Scd_symbol_max_time 0x00000000
Scd_symbol_nom_time 0x00000000 Nominal symbol time is stored in this register.
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STB5701 Table 10.
Address 0x9C 0xA0 0xA4 0xA8
Functional description I2C mapped SCD registers - summary (continued)
Name Scd_prescaler Interrupt_enable Interrupt_clear Timeout Reset value Function
0x00000001 Value of prescaler for sampling is stored. 0x00000000 0x00000000 Interrupt enable register value is stored in this register. Interrupt clear register value is stored in this register.
0x00000000 Timeout for SCS based on prescaler tick.
4.8
Detailed display description
Table 11. DIG_config register format
0x00 Reset state Function 00: UHF direct 01: IR direct 10: UHF triggered (DOUT = 0 when no trigger) 11: IR or UHF triggered 1: STATE is driven by the SCD interrupt output 0: STATE is driven by the SCD detect state 1: Invert the STATE output 0: Open drain 1: Push pull 1: Enable clock output buffer 0x00 R/W
DIG_Config Bit Bit field
1:0
MODE
00
2 3 4 5 31:6
STATE_SEL STATE_INV STATE_DRIVE CLKOUT_ENABLE Reserved
0 0 0 0 0x00
Table 12.
RF_Config register format
0x04 Reset state 0 0 0 0 0x00 0x00 1: Enable front end 0: Disable front end 1: ASK detection 0: FSK detection 1: Enable AGC 0: Disable AGC (high gain) Function R/W
RF_Config Bit Bit field
0 1 2 3 31:4
RF_ENABLE ASK_NOTFSK LNA_GAIN Not used Reserved
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Functional description Table 13. PLL_A register
0x08 Reset state SAD = 0: 0x1 SAD= 1: 0x7 0x00 Function
STB5701
PLL_A Bit Bit field
R/W
2:0
PLL_A
PLL post divider value. Reset value determined by level on SAD input. 0x00
31:3
Reserved
Table 14.
PLL_M register format
0x0C Reset state SAD = 0: 0x1D5 SAD= 1: 0x1CD 0x00 Function PLL feedback divider value. Reset value determined by level on SAD input. 0x00 R/W
PLL_M Bit Bit field
9:0
PLL_M
31:10
Reserved
Table 15.
PLL_R register format
0x10 Reset state 000 0x00 Function PLL reference divider value 0x00 R/W
PLL_R Bit 9:0 31:10 Bit field PLL_R Reserved
Table 16.
SCD_config register format
0x80 Reset state 0 0 0 0 0x00 Function 1: Enables the start code detection circuit 0: By passes SCD, UHF in fed to UHF out 1: Start a fresh research. Reset automatically to `0' on re-search start 1: Resets all the counters and shift register 1: Reset only shift register. Status register is not affected. 0x00 R/W
SCD_config Bit 0 1 2 3 31:4 Bit field Enable Re-search Soft_rst Reset_shift_reg Reserved
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STB5701 Table 17. SCD_status register format
0x84 Reset state 0 0 0 0x00
Functional description
SCD_status Bit 0 1:2 3 31:4 Bit field Detect Reserved Alternative Reserved
R Function
1: Start code detected, UHF in fed to UHF out 00 1: The alternative code was detected 0x00
Table 18.
SCD_code register format
0x88 Reset state 0x00 0x00 Function Start code to be detected Alternative start code to be detected R/W
SCD_code Bit 15:0 31:16 Bit field Code Alt_code
Note:
This register holds each start code to be detected. Table 19. SCD_code_lenth register format
0x8C Reset state 0 0x00 0 0x00 Length of the start code 0x00 Length of the alternative start code 0x00 Function R/W
SCD_code_lenth Bit 4:0 15:5 20:16 31:21 Bit field Code_length Reserved Alt_code_length Reserved
Note:
The length of the start code is stored in this register. If the start code length is 10 symbol then 10 has to be written into this register. Writing 0x00 disables the SCD. Table 20. SCD_symbol_min_time register format
0x90 Reset state 0x00 0x00 Minimum symbol time 0x00 Function R/W
SCD_symbol_min_time Bit 15:0 31:16 Bit field Min_time Reserved
Note:
The minimum time of the symbol in terms of pre-scaler ticks is stored in this register. If any symbol violates the minimum symbol time, the SCD process is re-initialized. If a value 0x10 is written into this register, the symbol min. time is 16 pre-scaler clock periods.
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Functional description Table 21. SCD_symbol_max_time register format
0x94 Reset state 0x00 0x00 Maximum symbol time 0x00 Function
STB5701
SCD_symbol_max_time Bit 15:0 31:16 Bit field Max_time Reserved
R/W
Note:
The maximum time of the symbol is stored in this register. Any changes in the input data are allowed only between symbol minimum time and symbol maximum time. The symbol time counting is done by a clock (enable pulse) which ia output of pre-scaler. If a value 0x10 is written into this register, the symbol max time is 16 pre-scaler clock periods. Table 22. SCD_symbol_nom_time register format
0x98 Reset state 0x00 0x00 Nominal symbol time 0x00 Function R/W
SCD_symbol_nom_time Bit 15:0 31:16 Bit field Nom_time Reserved
Note:
The nominal time of the symbol in terms of pre-scaler ticks is stored in this register. This value is used to register a new symbol when consecutive symbols with same logical value are received. If a value 0x10 is written into this register, the symbol nominal time is 16 prescaler clock periods. Table 23. SCD_prescaler register format
0x9C Reset state 0x01 0x00 Function Pre scaler division value is stored in this register 0x00 R/W
SCD_prescaler Bit 15:0 31:16 Bit field prescaler Reserved
Note:
The nominal time of the symbol is stored in this register. Table 24. Interrupt_enable register format
0xA0 Reset state 0 0x00 1 Enable interrupt 0 Disable interrupt 0x00 Function R/W
Interrupt_enable Bit 0 31:1 Bit field scd_detected Reserved
Note:
The interrupt enable register value is stored in this register.
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STB5701 Table 25. Interrupt_clear register format
0xA4 Reset state 0 0x00
Functional description
Interrupt_clear Bit 0 31:1 Bit field scd_clear_int Reserved
R/W Function
1 Clear interrupt 0 No change on interrupt 0x00
Note:
The interrupt clear register value is stored in this register. Table 26. Timeout register format
0xA8 Reset state 0x00 0x00 Function Timeout value, duration is based on prescaler tick. 0x00 R/W
Bitcount Bit 23:0 31:24 Bit field Timeout Reserved
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Package information
STB5701
5
5.1
Package information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
QFN32L (5mm x 5mm) information
Figure 9. QFN32L (5mm x 5mm) dimensions
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STB5701 Table 27. QFN32L (5mm x 5mm) mechanical data
mm Min. A A1 A3 b D D2 E E2 e L ddd 0.30 0.18 4.85 3.50 4.85 3.50 0.80 0.00 Typ. 0.90 0.02 0.20 0.25 5.00 3.60 5.00 3.60 0.50 0.40
Package information
Max. 1.00 0.05
0.30 5.15 3.70 5.15 3.70
0.50 0.05
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Revision history
STB5701
6
Revision history
Table 28.
Date 01-Oct-2007
Document revision history
Revision 1 Initial release. Changes
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STB5701
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