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XC9515 Series
2 channel Synchronous Step-Down DC/DC Converter with Manual Reset
ETR0706-008
GENERAL DESCRIPTION
The XC9515 series consists of 2 channel synchronous step-down DC/DC converters and a voltage detector with delay circuit built-in. The DC/DC converter block incorporates a P-channel 0.35 (TYP.) driver transistor and a synchronous N-channel 0.35 (TYP.) switching transistor. By minimizing ON resistance of the built-in transistors, the XC9515 series can deliver highly efficient and a stable output current up to 800mA. With high switching frequencies of 1MHz, a choice of small inductor is possible. The series has a built-in UVLO (under-voltage lock-out) function, therefore, the internal P-channel driver transistor is forced OFF when input voltage becomes 1.8V or lower (for XC9515A, 2.7V or lower). The voltage detector block can be set delay time freely by connecting an external capacitor. With the manual reset function, the series can output a reset signal at any time.
APPLICATIONS
DVDs Blu-ray Disk LCD TVs, LCD modules Multifunctional printers Photo printers Set top boxes
FEATURES
DC/DC Block Input Voltage Range Output Voltage : 2.5V 5.5V : VOUT1=1.2V 4.0V VOUT2=1.2V 4.0V (Accuracy 2%) Oscillation Frequency : 1MHz (Accuracy 15%) High Efficiency : 95% (VIN=5V, VOUT=3.3V) Output Current : 800mA Control : PWM control Protection Circuits : Thermal Shutdown : Integral Latch Over Current Limit : Short Protection Circuit Ceramic Capacitor Compatible Voltage Detector (VD) Block Detect Voltage Range : 2.0 5.5V Accuracy 2% Delay Time : 173 ms (When Cd=0.1 F is connected) Output Configuration : N-channel open drain Package : QFN-20
TYPICAL APPLICATION CIRCUIT
L1 VOUT1 EN1 VIN EN2
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs. Output Current
VIN=5V, fOSC=1MHz, L=4.7 H (CDRH4D28C) L=4.7uH(CDRH4D28C),CIN=10uF(ceramic),CL=10uF(ceramic)
VIN=5V,FOSC=1MHz
100 90 80
CIN=10
F (ceramic), CL=10 F (ceramic)
VOUT=3.3V
LX1
EN1
PVDD 1
EN2
NC
CIN1
NC
CL1
VOUT 1 MR AVSS Cd
Efficiency[%]
PVSS 1 NC PVSS 2 VDOUT NC PVDD 2 LX2 NC NC
MR
70 60 50 40 30 20 10 0 1
VOUT=1.5V
VOUT 2
Cd RUP
VOUT=1.8V 10 100 Output Current : IOUT [mA] 1000
CIN2
CL2 VDOUT
L2
VOUT2
1/21
XC9515 Series
20 PVDD1 16 EN2 17 EN1
PIN CONFIGURATION
18 LX1
Vout1 15 MR 14 AVSS 13 CD 12 Vout2 11
1
19 NC
1 NC 2 PVSS1 3 NC 4 PVSS2 5 NC
QFN-20 (BOTTOM VIEW)
VDOUT 10
NC 9
LX2 8
NC 7
PIN ASSIGNMENT
QFN-20
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 *1 PIN NAME NC P_VSS1 NC P_VSS2 NC P_VDD2 NC LX2 NC VDOUT FUNCTION No Connection Power Ground 1 No Connection Power Ground 2 No Connection Power Supply 2 No Connection Switching Output 2 No Connection Voltage Detector output PIN NUMBER 11 12 13 14 15 16 17 18 19 20 PIN NAME VOUT2 Cd A_VSS MR VOUT1 EN2 EN1 LX1 NC P_VDD1 FUNCTION Output Voltage Sense 2 Delay Capacitor Connection Analog Ground Manual Reset Output Voltage Sense1 CH2 ON/OFF Control CH1 ON/OFF Control Switching Output 1 No Connection Power Supply 1
Back metal pad voltage VSS level The back metal pad should be soldered to enhance mounting strength and heat release. If the pad needs to be connected to
other circuit, care should be taken for the pad voltage level.
2/21
PVDD2 6
XC9515
Series
FUNCTION CHART
EN1, EN2 and MR pins are internally pulled up. * PIN EN1 EN2 MR LEVEL High , Open Low High , Open Low High , Open Low
2)
OPERATIONAL STATUS DC/DC_CH1 Operation DC/DC_CH1 Stop DC/DC_CH2 Operation DC/DC_CH2 Stop VD_OUT Detect RESET Signal Output VD_OUT Force RESET Signal Output
EN1, EN2 and MR pins are internally pulled up so that the levels of High and Open are same function.
EN1, EN2 and MR pins are left open internally. * PIN EN1 EN2 MR LEVEL High Low High Low High Low
2)
OPERATIONAL STATUS DC/DC_CH1 Operation DC/DC_CH1 Stop DC/DC_CH2 Operation DC/DC_CH2 Stop VD_OUT Detect RESET Signal Output VD_OUT Force RESET Signal Output
EN1, EN2 and MR pins are floated inside so that these pins shall not be left open outside. * Please refer to the PRODUCTION CLASSIFICATION to see the combination of pull-up status regarding the EN1, EN2, and MR pins.
2)
PRODUCT CLASSIFICATION
Ordering Information (Standard products)
XC9515
DESIGNATOR DESCRIPTION Input Voltage & UVLO SYMBOL A B A B EN & MR logic control conditions C D Set Voltage Combinations Package Device Orientation 01 Z R L DESCRIPTION Input Voltage Range 5V Input Voltage Range 2.5V 10%, UVLO Voltage 2.7V (TYP.) 5.5V, UVLO Voltage 1.8V (TYP.)
EN1, EN2, MR pins are not pulled up internally EN1, EN2 pins have built-in pull-up resistors, MR pin has a built-in pull-up resistor EN1, EN2 Pins are not pulled up internally, MR pin has a built-in pull-up resistor EN1, EN2 pins have built-in pull-up resistors, MR pin are not pulled up internally Based on Torex Standard Product Number QFN-20 Embossed tape, Standard feed Embossed tape, Reverse feed
3/21
XC9515 Series
BLOCK DIAGRAM
VOUT1
ErrorAmp
Current Feedback
PVDD
Current Limit
VOUT1
ErrorAmp
PVDD
Current Limit
Current Feedback
PVDD1
LX1 EN1 EN2
Soft Start PWM Comparator Ramp Wave Thermal Shutdown
Logic Buffer Drive
LX1 EN1
Soft Start PWM Comparator Ramp Wave Thermal Shutdown
Logic Buffer Drive
ON/ OFF Control
PVSS1
EN2
ON/ OFF Control
PVSS1
Vre
OSC
Vre
OSC
VOUT2
PVDD2
Soft Start Ramp Wave
Current Limit
VOUT2
Soft Start
PVDD2
Ramp Wave
Current Limit
Current Feedback
Current Feedback
ErrorAmp PVDD1
LX2
PWM Comparator
Logic Buffer Drive
ErrorAmp PVDD1
LX2
PWM Comparator
Logic Buffer Drive
PVSS2 MR VDOUT
Rdelay Rdelay
PVSS2 MR VDOUT
Vre
Vre
AVSS
Cd
AVSS
Cd
ABSOLUTE MAXIMUM RATINGS
Ta=25
PARAMETER P_VDD1P_VDD2 Pin Voltage VOUT1VOUT2 Pin Voltage Cd Pin Voltage VDOUT Pin Voltage VDOUT Pin Current EN1EN2MR Pin Voltage LX1LX2 Pin Voltage LX1LX2 Pin Current Power Dissipation QFN-20 SYMBOL P_VDD1, P_VDD2 VOUT1, VOUT2 VCd VDOUT IDOUT VEN1, VEN2, VMR VLx1, VLx2 ILx1, ILx2 Pd (Free air) Pd (Wiring on PCB) Topr Tstg RATINGS -0.36.5 -0.36.5 -0.3P_VDD12 + 0.3 -0.36.5 10 -0.36.5 -0.3P_VDD12+0.3 1500 300 1000 -40 +85 -55 +125 UNITS V V V V mA V V mA mW
o o
Operating Temperature Range Storage Temperature Range * P_VDD1
2
C C
stands for P_VDD1=P_VDD2
A_VSS=P_VSS1=P_VSS2=0V
4/21
XC9515
Series
ELECTRICAL CHARACTERISTICS
XC9515AB04xx DC/DC CH1, CH2 (VOUT1=1.5V, VOUT2=3.3V, fOSC =1MHz, EN1 2 Pull-up inside)
PARAMETER Input Voltage Output Voltage 1 Output Voltage 2 Maximum Output Current 12 Current Limit 12 Oscillation Frequency Maximum Duty Cycle Minimum Duty Cycle Efficiency 1
(*2) (*1)
Ta =25 oC
MIN. 4.5 TYP. 5.0 MAX. UNITS CIRCUIT 5.5 V V V mA mA MHz % % %
SYMBOL VIN VOUT1 VOUT2 IOUTMAX1 IOUTMAX2 I LIM1 I LIM 2 fOSC MINDTY EFFI1
CONDITIONS
Connected to the external components, P_VDD12=VEN1=VEN2=0V, IOUT1=30mA Connected to the external components, P_VDD12=VEN2=VEN1=0V, IOUT2=30mA
1.470 1.500 1.530 3.234 3.300 3.366 800 1000 1.00 89 1.15 0
Connected to the external components, IOUT=10mA VOUT1=VOUT2=VIN Connected to the external components, P_VDD12=VEN1=5.0V, VEN2=0V, VOUT1=1.5V, IOUT1=200mA Connected to the external components,
0.85 100
MAXDTY VOUT1=VOUT2=0V
Efficiency 2
(*2)
EFFI2
P_VDD12=VEN2=5.0V, VEN1=0V, VOUT2=3.3V, IOUT2=200mA
94
%
LX12 "H" ON Resistance LX12 "L" ON Resistance Integral Latch Time 12
RLX1HRLX2H VOUT1=VOUT2=0V, ILx1=ILx2=100mA RLX1LRLX2L
(*3)

0.35 0.35 6
(*4)

ms

(*4)
LX1 and LX2 are pulled down by a resistor of 200 tLAT1 tLAT2 VOUT1=Setting Voltagex0.9, VOUT2= Setting Voltage x0.9 Soft-Start Time 12 EN12 "H" Level Voltage EN12 "L" Level Voltage EN12 "H" Level Current EN12 "L" Level Current LX12 "H" Leakage Current
(*7) (*5)
tSS1 tSS2 VEN1H VEN2H VEN1L VEN2L
Time until EN1, EN2 or both pins changes from 0V to VIN and voltage becomes VOUT12x0.95, IOUT12=10mA VOUT1=VOUT2=0V Voltage which LX1 or LX2 becomes "H" VOUT1=VOUT2=0V Voltage which LX1 or LX2 becomes "L"
(*6) (*6)
1.2 AVSS -3.0
(*9)
1.3
5 0.4 0.1
(*8)
ms V V A A A A

IEN1HIEN2H P_VDD12=VEN1=VEN2=5.5V IEN1LIEN2L P_VDD12=5.5V, VEN1=VEN2=0V ILEAK1H ILEAK2H ILEAK1L ILEAK2L P_VDD12=VLX1=VLX2=5.5V, VEN1=VEN2=0V P_VDD12=5.5V, VLX1=VLX2=VEN1=VEN2=0V
-6
(*8)
1.0
(*9)

LX12 "L" Leakage Current
Test Conditions * P_VDD1 2 stands for P_VDD1=P_VDD2 **Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 2 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 When the difference between the input and the output is small, some cycles may be skipped completely before current maximizes. If current is further pulled from this state, output voltage will decrease because of P-ch driver ON resistance. *2 EFFI = { ( output voltage x output current ) / ( input voltage x input current) } x 100 *3 On resistance ( )= (VIN - Lx pin measurement voltage) / 100mA *4 Designed value. *5 Time until it short-circuits LX1 (LX2 in the side of 2CH) with GND via 1 of resistor from an operational state and is set to Lx=0V from current limit pulse generating. *6 "H" is judged as "H">VIN-0.1V, "L" is judged as "L"<0.1V. *7 When temperature is high, a current of approximately 20 A (maximum) may leak. *8 Current which EN1 and EN2 are measured separately. *9 Lead current which LX1 and LX2 are measured separately.
5/21
XC9515 Series
ELECTRICAL CHARACTERISTICS (Continued)
XC9515AB04xx
Voltage Detector (VD) (MR pin Pull-up Inside) Block
PARAMETER Detect Voltage Hysteresis Width VD Output Current Delay Resistance MR "H" Level Voltage MR "L" Level Voltage MR "H" Level Current MR "L" Level Current Test Conditions * P_VDD1
2
Ta=25oC
CONDITIONS MIN. VDF(T) x0.98 TYP. VDF(T) 5.0 6.6 2.5 -6.0
(*2)
SYMBOL VDF(E)
(*1)
MAX. VDF(T) x1.02 8.0 5.5 0.4 0.1
UNITS CIRCUIT V % mA M V V A A
VHYS IDOUT RDLY VMRH VMRL IMRH IMRL
VHYS=(VDR(E)
(*3)
- VDF(E) ) / VDF(E) x100
5.0 1.2 AVSS
P_VDD12=VDF-0.01V, Apply 0.5V to VDOUT VDOUT="H" Level Voltage VDOUT="L" Level Voltage P_VDD12=VMR=5.5V P_VDD12=5.5V, VMR=0V
(*3) (*3)
stands for P_VDD1=P_VDD2
2
**Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 VDF(E)=Detect Voltage *2 VDR(E)=Release Voltage *3 "H" is judged as "H">VIN-0.1V, "L" is judged as "L"<0.1V
XC9515AB04xx
Whole Circuit (VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz, EN1
PARAMETER Supply Current 1 Supply Current 2 Stand-by Current UVLO Detect Voltage UVLO Release Voltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis Width Test Conditions * P_VDD1
2
2 Pull-up Inside)
MIN.
(*1) (*1)
Ta=25oC
TYP. 950 75 18 1.8 150 20 MAX. UNITS CIRCUIT 1500 145 33 3.0 3.5 A A A V V
o
SYMBOL IDD1 IDD2 ISTB VUVLOF VUVLOR TTSD THYS
CONDITIONS VOUT1=VOUT2=Setting Voltage x 0.9 VOUT1=VOUT2=Setting Voltage x 1.1 Oscillation stops VEN1=VEN2=0V VIN voltage which VOUT1=0V and LX pin becomes "L" VIN voltage which VOUT1=0V and LX pin becomes "H"

2.4
C C
o
stands for P_VDD1=P_VDD2
2
**Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 "H" is judged "H">VIN-0.1V, "L" is judged "L"<0.1V
6/21
XC9515
Series
ELECTRICAL CHARACTERISTICS (Continued)
XC9515BA06xx DC/DC CH1, CH2 (VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz, EN1 and EN2 pins are internally floating)
PARAMETER Input Voltage Output Voltage1 SYMBOL VIN Connected to the external components, VOUT1 PVDD12=EN1, EN2=0V IOUT1=30mA Connected to the external components, Output Voltage2 VOUT2 IOUTMAX1 IOUTMAX2 ILIM1 ILIM 2 fOSC MAXDTY MINDTY EFFI1 Connected to the external components, IOUT=10mA VOUT1=VOUT2=0V VOUT1=VOUT2=VIN Connected to the external components, Efficiency 1
(*2)
Ta=25 oC
MAX. UNITS CIRCUIT 5.5 V V
CONDITIONS
MIN. 2.5
TYP.
1.470 1.500 1.530
PVDD12=EN2, EN1=0V IOUT2=30mA
3.234 3.300 3.366
V
Maximum Output Current 12 Current Limit 12 Oscillation Frequency Maximum Duty Cycle Minimum Duty Cycle
(*1)
800 1000 0.85 100 0 89 1.00 1.15
mA mA MHz % % %

PVDD12=EN1=5.0V, EN2=0V VOUT1=1.5V, IOUT1=200mA Connected to the external components,
Efficiency 2
(*2)
EFFI2
PVDD12=EN2=5.0V, EN1=0V VOUT2=3.3V, IOUT2=200mA
(*3)
94 0.35 0.35
(*4) (*4)
% ms ms 5 0.4 0.1
(*8)

LX12 "H" ON Resistance LX12 "L" ON Resistance Integral Latch Time 12 Soft-Start Time 12 EN12 "H" Voltage EN12 "L" Voltage EN12 "H" Current EN12 "L" Current LX12 "H" Leak Current
(*7)
RLX1HRLX2H VOUT1=VOUT2=0V, ILx1=ILx2=100mA RLX1LRLX2L tLAT1tLAT2 tSS1tSS2 VENHVEN2H VEN1LVEN2L IEN1HIEN2H IEN1LIEN2L Ileak1HIleak2H Ileak1LIleak2L
LX1 and LX2 are pulled down by a resistor of 200 VOUT1= Setting Voltagex0.9, VOUT2= Setting Voltagex0.9 and voltage becomes VOUT12x0.95, IOUT12=10mA VOUT1=VOUT2=0V Voltage which LX1 or LX2 becomes "H" VOUT1=VOUT2=0V Voltage which LX1 or LX2 becomes "L" PVDD12=EN1=EN2=5.5V PVDD12=5.5V, EN1=EN2=0V PVDD12=LX1=LX2=5.5V, EN1=EN2=0V PVDD12=5.5V, LX1=LX2=EN1=EN2=0V -3.0
(*9) (*6) (*6) (*5)
6 1.3 1.2 AVSS
Time until EN1, EN2 or both pins changes from 0V to VIN
V V A A A A
-0.1
(*8)
1.0
(*9)
LX12 "L" Leak Current
Test Conditions * P_VDD1 2 stands for P_VDD1=P_VDD2 **Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 2 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 When the difference between the input and the output is small, some cycles may be skipped completely before current maximizes. If current is further pulled from this state, output voltage will decrease because of P-ch driver ON resistance. *2 EFFI = { ( output voltage x output current ) / ( input voltage x input current) } x 100 *3 On resistance ( )= (VIN - Lx pin measurement voltage) / 100mA *4 Designed value. *5 Time until it short-circuits LX1 (LX2 in the side of 2CH) with GND via 1 of resistor from an operational state and is set to Lx=0V from current limit pulse generating. *6 "H" is judged as "H">VIN-0.1V, "L" is judged as "L"<0.1V. *7 When temperature is high, a current of approximately 20 A (maximum) may leak. *8 Current which EN1 and EN2 are measured separately. *9 Lead current which LX1 and LX2 are measured separately.
7/21
XC9515 Series
ELECTRICAL CHARACTERISTICS (Continued)
XC9515BA06xx VD (MR pin is internally floating)
PARAMETER Detect Voltage Hysteresis Width VD Output Current Delay Resistance MR "H" Level Voltage MR "L" Level Voltage MR "H" Level Current MR "L" Level Current Test Conditions * P_VDD1
2
Ta=25 oC
CONDITIONS VHYS={VDR(E)
(*2)
SYMBOL VDF(E)
(*1)
MIN. 2.94
TYP. 3.00 5.0 6.6 2.5
MAX. UNITS CIRCUIT 3.06 8.0 5.5 0.4 0.1 V % mA M V V A A
VHYS IDOUT RDLY VMR VMR IMR IMR
-VDF(E) }/ VDF(E)x100 5.0 1.2 AVSS -0.1
(* )
P_VDD12=VDF-0.01V, Apply 0.5V to VDOUT VDOUT="H" Level Voltage VDOUT="L" Level Voltage PVDD12=MR=5.5V PVDD12=5.5V,MR=0V
(*3) (*3)
stands for P_VDD1=P_VDD2
2
**Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 VDF(E)=Detect Voltage *2 VDR(E)=Release Voltage *3 "H" is judged as "H">VIN-0.1V, "L" is judged as "L"<0.1V
XC9515BA01xx Whole Circuit (VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz, EN1 and EN2 pins are internally floating)
PARAMETER Supply Current 1 Supply Current 2 Stand-by Current UVLO Detect Voltage UVLO Release Voltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis Width Test Conditions * P_VDD1
2
Ta=25 oC
TYP. 950 75 5.5 MAX. UNITS CIRCUIT 1500 145 11 2.1 2.3 150 20 A A A V V
o
SYMBOL IDD1 IDD2 ISTB VUVLOF VUVLOR TTSD THYS
CONDITIONS VOUT1=VOUT2= Setting Voltagex0.9 VOUT1=VOUT2= Setting Voltagex1.1 (Oscillation stops) EN1=EN2=0V VIN voltage which VOUT1=0V and LX pin becomes "L" VIN voltage which VOUT1=0V and LX pin becomes "H"
(*1) (*1)
MIN.
-
1.5
1.8
C C
o
stands for P_VDD1=P_VDD2
2
**Unless otherwise stated, P_VDD1 2=5V, VEN1=VEN2= P_VDD1 *** A_VSS=P_VSS1=P_VSS2=0V NOTE : *1 "H" is judged "H">VIN-0.1V, "L" is judged "L"<0.1V
8/21
XC9515
Series
TYPICAL APPRICATION CIRCUIT
L1
VOUT1 EN1
VIN
EN2
NC
PVDD 1
LX1
EN1
EN2
CIN1
NC
CL1
VOUT 1 MR AVSS Cd
PVSS 1 NC PVSS 2 VDOUT NC PVDD 2 LX2 NC NC
MR
VOUT 2
Cd RUP
CIN2
CL2 VDOUT
L2
VOUT2
Example of the External Components L1 L2 CIN1 CIN2 CL1 CL2 RUP 4.7 4.7 10 10 10 10 H H CDRH4D28C, SUMIDA CDRH4D28C, SUMIDA
F ceramic F ceramic F ceramic F ceramic
100k
9/21
XC9515 Series
OPERATIONAL EXPLANATION
XC9515 series consists of a reference voltage source, ramp wave circuit, error amplifier, PWM comparator, phase compensation circuit, output voltage adjustment resistors, P-channel driver transistor, N-channel synchronous switching transistor, current limit circuit, UVLO circuit and others. The series ICs compare, using the error amplifier, the voltage of the internal voltage reference source with the feedback voltage from VOUT pin through split resistors, RFB1 and RFB2. Phase compensation is performed on the resulting error amplifier output, to input a signal to the PWM comparator to determine the turn-on time during PWM operation. The PWM comparator compares, in terms of voltage level, the signal from the error amplifier with the ramp wave from the ramp wave circuit, and delivers the resulting output to the buffer driver circuit to cause the Lx pin to output a switching duty cycle. This process is continuously performed to ensure stable output voltage. The current feedback circuit monitors the P-channel driver transistor current for each switching operation, and modulates the error amplifier output signal to provide multiple feedback signals. This enables a stable feedback loop even when a low ESR capacitor, such as a ceramic capacitor, is used, ensuring stable output voltage. The reference voltage source provides the reference voltage to ensure stable output voltage of the DC/DC converter. The ramp wave circuit determines switching frequency. The frequency is fixed internally at 1MHz. Clock pulses generated in this circuit are used to produce ramp waveforms needed for PWM operation, and to synchronize all the internal circuits. The error amplifier is designed to monitor output voltage. The amplifier compares the reference voltage with the feedback voltage divided by the internal split resistor, RFB1 and RFB2. When a voltage lower than the reference is fed back, the output voltage of the error amplifier increases. The gain and frequency characteristics of the error amplifier output are fixed internally to deliver an optimized signal to the mixer. The current limiter circuit of the XC9515 series monitors the current flowing through the P-channel MOS driver transistor connected to the Lx pin, and features a combination of the current limit mode and the latch mode. When the driver current is greater than a specific level (peak value of coil current), the current limit function operates to off the pulses from the Lx pin at any giving timing. When the driver transistor is turned off, the limiter circuit is then released from the current limit detection state. At the next pulse, the driver transistor is turned on. However, the transistor is immediately turned off in the case of an over current state. When the over current is eliminated, the IC resumes its normal operation. The IC waits for the over current state to end by repeating the steps to . If an over current state continues for a few ms and the above three steps are repeatedly performed, the IC performs the function of latching the OFF state of the driver transistor. Both two DC/DC blocks stop operations when either CH1 or CH2 of protection circuit is activated. At this time, both Lx1 and Lx2 become high impedance. Once the IC is in latch mode, operations can be resumed by either turning the IC off after letting EN1 and EN2 pins down to low level, or by restoring power. For restoring power, the IC should be turned off after P_VDD1 and P_VDD2 voltages drop below the low level of EN1 and EN2 pin. The latch operation can be released from the current limit detection state because of the circuit's noise. Also, depending on the state of the PC Board, latch time may become longer and latch operation may not work. In order to avoid the effect of noise, the board should be laid out so that capacitors are placed as close to the chip as possible.
Limit < # ms Limit < # ms
10/21
XC9515
Series
OPERATIONAL EXPLANATION (Continued)
For protecting the IC from heat damage, the thermal shutdown circuit monitors the chip temperature. When the chip temperature reaches 150 , the thermal shutdown circuit operates and the driver transistor will be set to OFF. As the chip temperature drops to 130 by stopping current flow, the soft-start function operates to turn the output on. The short-circuit protection circuit monitors the FB voltage. If the output is shorted incorrectly with the ground, the short-circuit protection circuit operates and turns the driver transistor off to latch when the FB voltage becomes less than half of the setting voltage. Both two DC/DC blocks stop operations when either CH1 or CH2 of protection circuit is activated. At this time, both Lx1 and Lx2 become high impedance. Once the IC is in latch mode, operations can be resumed by either turning the IC off after letting both ends of EN1 and EN2 pins down to low level, or by restoring power. (The P_VDD1 and P_VDD2 voltages should be less than the low level of the EN1 and EN2 pins when restoring power.) The soft-start circuit protects against inrush current, when the power is switched on, and also to protect against voltage overshoot. It should be noted, however, that this circuit does not protect the load capacitor (CL) from inrush current. With the Vref voltage limited and depending upon the input to the error amps, the operation maintains a balance between the two inputs of the error amps and controls the EXT1 pin's ON time so that it doesn't increase more than is necessary. When the VIN pin voltage becomes1.8V (TYP.) or lower (for XC9515A, 2.7V or lower), the P-channel output driver transistor is forced OFF to prevent false pulse output caused by unstable operation of the internal circuitry. When the VIN pin voltage becomes 1.9V (TYP.) or higher (for XC9515A, 3.0V or lower), switching operation takes place. By releasing the UVLO function, the IC performs the soft-start function to initiate output startup operation. The series' detector function monitors the voltage divided by resistors connected to the P_VDD1 pin, as well as monitoring the voltage of the internal reference voltage source via the comparator. Because of hysteresis at the detector function, output at the VDOUT pin will invert when the sense pin voltage of the detector block (P_VDD1) increases above the release voltage (105% of the detect voltage). The output configuration of the VDOUT pin is N-channel open drain, therefore, a pull-up resistor is required. The voltage detector block has a manual reset (MR) pin. By setting the MR pin at low level, the VDOUT pin is forced to be at low level.
By connecting a capacitor (Cd) to the Cd pin, the XC9515 series can set a delay time to VDOUT pin's output signal when releasing voltage. The delay time can be calculated from the internal resistance, Rdelay (2.5M fixed TYP.) and the value of Cd as per the following equation. As selecting the capacitor (Cd), the delay time can be set freely. tDR (Delay time) Release Delay Delay Capacity Cd [ F] 0.01 0.022 0.047 0.1 0.22 0.47 1 Cd x Rdelay x 0.69 Ta=25 oC MAX.) [ms]
Release Delay tDR (TYP.) [ms] 17 38 81 173 380 811 1725
Release Delay tDR (MIN. 10 24 23 53 49 113 103 242 228 532 487 1135 1035 2415
11/21
XC9515 Series
NOTES ON USE
1. 2. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded. Please apply the same electrical potential to the P_VDD1 and P_VDD2 pins. Even where either CH1 or CH2 is used, both P_VDD1 and P_VDD2 pins should have the same electrical potential. Applying the electrical potential to only one side causes malfunction. Also the same electrical potential should be applied to the P_VSS1, P_VSS2 and A_VSS pins. The XC9515 series is designed for use with ceramic output capacitors. If, however, the potential difference between dropout voltage or output current is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and the output could be unstable. If the input-output potential difference is large, use a larger output capacitor to compensate for insufficient capacitance. When the peak current, which exceeds limit current flows within the specified time, the built-in driver transistor is turned off (the integral latch circuit). During the time until it detects limit current and before the built-in transistor can be turned off, the current for limit current flows; therefore, care must be taken when selecting the rating for the coil. When the input voltage is low, limit current may not be reached because of voltage falls caused by ON resistance or serial resistance of the coil. Since the potential difference for input voltage has occurred to the both ends of a coil, the time changing rate of the coil current is large when the P-channel driver transistor is ON. On the other hand, since the VOUT pin short-circuits to the GND when the N-channel transistor is ON and there is almost no potential difference of the coil both ends, the time changing rate of the coil current becomes very small. This operation is repeated and the delay time of the circuit also influences, therefore, the coil current is converged on the current value beyond the amount of current which should be restricted essentially. The short-circuit protection does not operate during the soft-start time. As soon as the soft-start time finishes, the short-circuit protection starts to operate and the circuit becomes disable. The delay time of the circuit also influences when step-down ratio is large, as the result, a current more than over current limit may flow. Please do not exceed the absolute maximum ratings of the coil. A current flows to the driver transistor up to the current limit (ILIM). For the delay time of the circuit, a current more than the ILIM flows after the ILIM decide until the P channel driver transistor turns off. Time changing rate of the coil current becomes very small because there is no potential difference between both ends of the coil. The Lx pin oscillates a narrow pulse during the soft-start time because of the current limit. The circuit is latched since the short-circuit protection operates and the P-channel driver transistor is turned off.
3.
4.
5. 6.
# ms
12/21
XC9515
Series
NOTES ON USE (Continued)
7. 8. Driving current below the minimum operating voltage may lead malfunction to the UVLO circuit because of the noise. Depending on the PC board condition, the latch function may be released from limit current detection state and the latch time may extend or fail to reach the latch operation. Please locate the input capacitance as close to the IC as possible. Spike noise and ripple voltage arise in a switching regulator as with a DC/DC converter. These are greatly influenced by external component selection, such as the coil inductance, capacitance values, and board layout of external components. Once the design has been completed, verification with actual components should be done.
9.
10. With the DC/DC converter block of the IC, the peak current of the coil is controlled by the current limit circuit. Since the peak current increases when dropout voltage or load current is high, current limit starts operating, and this can lead to instability. When peak current becomes high, please adjust the coil inductance value and fully check the circuit operation. In addition, please calculate the peak current according to the following formula: Peak current: Ipk = (VIN - VOUT) x OnDuty / (2 x L x fosc) + IOUT L: Coil Inductance Value, fOSC: Oscillation Frequency 11. When the load current is light in PWM control, very narrow pulses will be outputted, and there is the possibility that some cycles may be skipped completely. 12. When the difference between VIN and VOUT is small, and the load current is heavy, very wide pulses will be outputted and there is the possibility that some cycles may be skipped completely. 13. If the power input pin voltage is assumed to decrease rapidly (ex. from 6.0V to 0V) at the release of the operation although delay capacitance (Cd) pin is connected, please connect an Shottky barrier diode between the power input (P_VDD1) pin and the delay capacitance (Cd) pin. 14. Please connect a pull-up resistor with 100 to 200k to the output pin of the voltage detector block (VDOUT). 15. The delay time of the voltage detector block in heavy load may extend because of the noise of the DC/DC block. Precipitous and large voltage fluctuation at the power input pin may cause malfunction of the IC. 16. Use of the IC at voltages below the minimum operating voltage may lead the output voltage drop before achieving over current limit. 17. When P_VDD1 and P_VDD2 power supply pins and EN1 and EN2 enable pins are in undefined states, the latch protection circuit may not be reset so that the IC operation does not start correctly. Power supply and enable pins EN1,EN2 should be grounded before starting the IC operation. Undefined state conditions for each pin P_VDD1=P_VDD2=0.1V ~ 1.2V VEN1=VNE2= 0.4V ~ 1.2V 18. UVLO function works even if when VIN input voltage falls below the UVLO voltage in very short time period like a few ten nanoseconds.
Instruction on Pattern Layout
1. In order to stabilize VIN's voltage level, we recommend that a by-pass capacitor (CIN1 and CIN2) be connected as close as possible to the P_VDD1 P_VDD2 pins and P_VSS1 P_VSS2 pins. 2. Please mount each external component as close to the IC as possible. 3. Wire external components as close to the IC as possible and use thick, short connecting traces to reduce the circuit impedance. 4. Make sure that the VSS traces are as thick as possible, as variations in the VSS potential caused by high VSS currents at the time of switching may result in instability of the DC/DC converter.
13/21
XC9515 Series
TEST CIRCUITS
< Test Circuit No.1 >
Wave Form Measurement Point
Wave Form Measurement Point
A
L
LX1
CL CIN
EN1 EN2 VOUT1 MR AVSS CD VOUT2 VDOUT A V
PVDD1 PVSS1 PVSS2
CIN
CL L
PVDD2 LX2
V
Wave Form MeasurementPoint Wave Form Measurement Point
External Components L : 4.7H(CDRH4D28C : SUMIDA) CIN : 10F (ceramic) CL : 10F (ceramic)
< Test Circuit No.2 >
A
Wave Form Measurement Point
Wave Form Measurement Point
LX1 PVDD1
EN1 EN2 VOUT1 MR AVSS CD VOUT2 VDOUT
A
1F
PVSS1 PVSS2 V A V PVDD2 LX2
V
Wave Wave Form Measurement Point Form Measurement Point
< Test Circuit No.3 >
100A
A V
LX1 PVDD1 PVSS1 PVSS2
EN1 EN2 VOUT1 MR AVSS CD VOUT2 VDOUT
1F 100A
V
PVDD2 LX2
A
14/21
XC9515
Series
TEST CIRCUITS (Continued)
Wave Form Measurement Point
Wave Form Measurement Point
15/21
XC9515 Series
TYPICAL PERFORMANCE CHARACTERISTICS
(1) Efficiency vs. Output Current
VIN=5V,FOSC=1MHz L=4.7uH(CDRH4D28C),CIN=10uF(ceramic),CL=10uF(ceramic)
100 90 80 VOUT=3.3V
Efficiency: EFFI (%) Efficiency[%]
70 60 50 40 30 20 10 0 1
VOUT=1.5V
VOUT=1.8V 10 100 Output Current : IOUT (mA) Output Current: IOUT [mA] 1000
(2) Output Voltage vs. Output Current
VOUT=1.5V VIN=5.0V L:4.7uH(CDRH4D28C),CIN=10uF(ceramic),CL=10uF(ceramic)
1.60 Output Voltage : VOUT[V] Output Voltage: VOUT (V) Output Voltage : VOUT[V] 1.90
VOUT=1.8V VIN=5. 0V L:4.7uH(CDRH4D28C),CIN=10uF(ceramic),CL=10uF(ceramic)
1.55
1.85
1.50
1.80
1.45
1.75
1.40 1 10 100 Output Current : IOUT[mA] Output Current: IOUT (mA) 1000
1.70 1 10 100 Output Current : IOUT[mA] Output Current: IOUT (mA) 1000
VOUT=3.3V VIN=5.0V L:4.7uH(CDRH4D28C),CIN=10uF(ceramic),CL=10uF(ceramic)
3.40
Output Voltage: VOUT (V) Output Voltage : VOUT[V]
3.35
3.30
3.25
3.20 1 10 100 Output Current : IOUT[mA] Output Current: IOUT (mA) 1000
16/21
XC9515
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(3) Output Voltage vs. Ambient Temperature VVout=1.2V OUT=1.2V
1.30 Output Voltage:Vout1[v] Output Voltage:Vout1[v] 1.25 1.20 1.15 1.10 1.05 1.00 -50 -25 0 25 50 75 100 Ambient Temperature:Ta[ ] VIN=2.5V,3.0V,4.0V,5.0V,5.5V
V IN=2.5V,3.0V,4.0V,5.0V,5.5 V L:4.7uH(CDRH 4D28C),CIN =10uF(c eram ic ),CL=10uF(ce ramic)
VOUT=1.5V Vout=1.5V V IN=2.5V,3.0V,4.0V,5.0 V,5.5V L:4.7 uH(CDRH 4D28C),CIN =10uF(ce ramic),CL=10uF(ceramic)
1.60 1.55 1.50 1.45 1.40 1.35 1.30 -50 -25 0 25 50 75 100 Ambient T emperature:Ta[ ] VIN=2.5V,3.0V,4.0V,5.0V,5.5V
VVout=1.8V OUT=1.8V V IN=2.5V,3.0V,4.0V,5.0V,5.5 V L:4.7uH(CDRH 4D28C),CIN =10uF(c eram ic ),CL=10uF(ce ramic)
1.90 OutputVoltage:Vout1[v] Output Voltage:Vout2[v] 1.85 1.80 1.75 1.70 1.65 1.60 -50 -25 0 25 50 75 100 Ambient Temperature:Ta[ ] VIN=2.5V,3.0V,4.0V,5.0V,5.5V 3.40 3.35 3.30 3.25 3.20 3.15 3.10 -50 -25
VOUT=3.3V Vout=3.3V VIN =4.0V,5.0 V,5.5V L:4.7 uH(CDRH 4D28C),CIN =10uF(ce ramic),CL=10uF(ceramic)
VIN=4.0V,5.0V,5.5V
0
25
50
75
100
Ambient Temperature:Ta[ ]
(4) Oscillation Frequency vs. Ambient Temperature fOSC=1MHz FOSC=1MHz
Oscillation Frequency Oscillation Frequency: fOSC (MHz) :FOSC[MHz] 1.2 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 Ambient Temperature:Ta[ ] VIN=2.5V,3.0V,4.0V,5.0V,5.5V
VIN=2.5V,3.0V,4.0V,5.0V,5.5V L:4.7uH(CD RH4D28C),CIN =10uF(ceramic),CL=10uF(ceramic)
17/21
XC9515 Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Load Transient Response VIN=5V, VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz VIN=5V,VOUT1=1.5V,VOUT2=3.3V,FOSC=1MHz,
VOUT1=200mV/div VOUT1=200mV/div
VOUT2=200mV/div
VOUT2=200mV/div
IOUT1=200mA
IOUT1=200mA
IOUT1=1mA
IOUT1=1mA
50 50s/div s/div VIN=5V, VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz VIN=5V,VOUT1=1.5V,VOUT2=3.3V,FOSC=1MHz,
VOUT1=200mV/div VOUT1=200mV/div
200s/div 200 s/div
VOUT2=200mV/div
VOUT2=200mV/div
IOUT1=800mA
IOUT1=800mA
IOUT1=200mA
IOUT1=200mA
50 50s/div s/div VIN=5V, VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz VIN=5V,VOUT1=1.5V,VOUT2=3.3V,FOSC=1MHz,
VOUT1=200mV/div VOUT1=200mV/div
200s/div 200 s/div
VOUT2=200mV/div
VOUT2=200mV/div
IOUT2=200mA
IOUT2=200mA
IOUT2=1mA
IOUT2=1mA
50 50s/div s/div VIN=5V, VOUT1=1.5V, VOUT2=3.3V, fOSC=1MHz VIN=5V,VOUT1=1.5V,VOUT2=3.3V,FOSC=1MHz,
VOUT1=200mV/div VOUT1=200mV/div
200s/div 200 s/div
VOUT2=200mV/div
VOUT2=200mV/div
IOUT2=800mA
IOUT2=800mA
IOUT2=200mA
IOUT2=200mA
50 50s/div s/div
200s/div 200 s/div
18/21
XC9515
Series
PACKAGING INFORMATION
QFN-20 Unit: mm
*The solder filet may not be formed because of no plating at side.
QFN-20 Reference Pattern Layout
QFN-20 Reference Metal Mask Design
Thickness of solder paste
120
m (reference)
19/21
XC9515 Series
MARKING RULE
QFN-20
Standard Product
1pin
Represent product series MARK PRODUCT SERIES 5 1 5 XC9515******
Represents integer number of setting voltage MARK PRODUCT SERIES 0 QFN-20 (TOP VIEW) 0 0 1 XC95150001**
Represents production lot number Order of 01, ...09, 10, 11, ...99, 0A, ...0Z, 1A, ...9Z, A0, ...Z9, AA, ...ZZ. (G, I, J, O, Q, W excepted) *No character inversion used.
20/21
XC9515
Series
1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this datasheet may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD.
21/21

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