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ISL59311
Data Sheet April 25, 2007 FN6372.3
Differential Video Amplifier with Common Mode Sync Encoder and Serial Digital Interface
The ISL59311 is a high bandwidth triple differential amplifier with integrated encoding of video sync signals. The inputs are suitable for handling high speed video or other communications signals in either single-ended or differential form, and the common-mode input range extends all the way to the negative rail enabling ground-referenced signaling in single supply applications. The high bandwidth enables differential signaling onto standard twisted-pair or coax with very low harmonic distortion, while internal feedback ensures balanced gain and phase at the outputs reducing radiated EMI and harmonics. Embedded logic encodes standard video horizontal and vertical sync signals onto the common mode of the twisted pair(s), transmitting this additional information without the requirement for additional buffers or transmission lines. The ISL59311 enables significant system cost savings when compared with discrete line driver alternatives. The digital block of the chip is a data transceiver which is intended to drive one twisted pair line. The maximum baudrate for this block is 50Mbps. The ISL59311 is available in a 32 Ld QFN package and is specified for operation over the -40C to +85C temperature range.
Features
* Fully differential inputs, outputs, and feedback * 650MHz -3dB bandwidth * 1500V/s slew rate * -70dB distortion at 20MHz * Single 5V operation * 50mA minimum output current * Low power: 57mA total supply current * Pb-free plus anneal available (RoHS compliant)
Block Diagram
VCCA VCCD
VCCA domain VINA+ VINADisable + VOUTA+ VOUTA-
VINB+ VINBCMA HSYNC Sync to CMB Common Mode Translation CMC
+ -
VOUTB+ VOUTB-
VSYNC
VINC+
+ -
VOUTC+ VOUTC-
Applications
* Twisted-pair drivers * Differential line drivers * VGA over twisted-pair * Transmission of analog signals in a noisy environment
VINC-
VCCS domain VCCS
VCCD domain
Transmit SOUT+ TXDATA SOUT-
Ordering Information
PART NUMBER (Note) ISL59311IRZ PART TAPE & PACKAGE MARKING REEL (Pb-Free) 59311 IRZ 13" 32 Ld QFN 32 Ld QFN PKG. DWG. # L32.5x6A L32.5x6A
SDATA
RXDATA
+ -
SIN+ SIN-
ISL59311IRZ-T13 59311 IRZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
GNDA
GNDD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL59311 Pinout
ISL59311 (32 LD QFN)
29 VOUTA+
30 Disable
28 VOUTA-
31 VIINA+
26 GNDA 25 VOUTC24 VOUTB+ 23 VOUTB22 VOUTC+ 21 GNDA 20 GNDD 19 VCCD 18 NC 17 SOUT+ SIN+ 16
VSYNC 1 HSYNC 2 VINB+ 3 VINB- 4 VINC+ 5 VINC- 6 GNDA 7 VCCS 8 VCCS 9 GNDD 10 THERMAL PAD
Transmit 12
SOUT- 13
NC 14
Pin Descriptions
PIN NAME VINA, VINB, VINC Differential video inputs DESCRIPTIONS EQUIVALENT CIRCUIT
VOUTA, VOUTB, VOUTC Differential video outputs to transmission line HSYNC, VSYNC Horizontal and Vertical Sync inputs to be encoded
H,V GNDA
Disable
Disable video amplifiers signal. Logic low enables the video amplifiers. Logic high disables the video amplifiers, reducing VCCA power consumption. The Serial Digital Interface is always enabled regardless of the state of the Disable pin. Transmit/receive logic input. Logic high: Transmits data from the SDATA pin data down the transmission line. Logic low: Data received from the transmission line is output on the SDATA pin. Differential serial data outputs to transmission line Differential serial data inputs from transmission line
SDATA 11
SIN- 15
27 VCCA
32 VINA-
ENV
GNDA
Transmit
TR GNDA
SOUT SIN
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FN6372.3 April 25, 2007
ISL59311 Pin Descriptions (Continued)
PIN NAME SDATA DESCRIPTIONS Digital data input/output. When Transmit is high, this is an input, receiving the serial data to be transmitted over the SOUT pins. When Transmit is low, this is an output, representing the data received on the SIN pins.
TXRX
EQUIVALENT CIRCUIT
DIFF DATA
VCCS VCCD GNDD VCCA GNDA NC
Power supply for SDATA I/O pin - sets input thresholds and output swing. Typically set to 3.3V or 5V. VCC for line interface section (5V) Digital ground for the Serial Digital Interface VCC for the video amplifiers (5V) Analog ground for the video amplifiers No Connection. Do not connect these pins to anything. Leave these pins floating!
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FN6372.3 April 25, 2007
ISL59311
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VCCA, VCCD) . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . 70mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Input/Output Voltages All signal (non-supply) pins . . . . . . . . . . . . -0.6V to VCCA + 0.6V ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
DESCRIPTION
VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25C, VIN = 0V, RL = 200, unless otherwise specified. CONDITION MIN TYP MAX UNIT
Video Amplifier Electrical Characteristics Output Voltage Range Output Impedance, Disabled AC PERFORMANCE Bandwidth, -3dB AV = 2, VOUT = 200mV VOUT = 2V Differential Slew Rate, Settling Time (0.1%, 2VP-P) Gain Bandwidth Product 2nd Harmonic Distortion 3rd Harmonic Distortion Hostile Crosstalk Differential Phase @100MHz Differential Gain @100MHz INPUT CHARACTERISTICS Input Referred Offset Voltage Input Bias Current Differential Input Impedance Differential Input Range Common Mode Input Voltage Range Input Referred Noise CMRR OUTPUT CHARACTERISTICS Output Peak Current Output Voltage Range DC PERFORMANCE Voltage Gain 1.90 1.95 2.00 V/V 40 1 60 VCC - 1 mA V VCM = 0V to 2V 60 -0.3 15 75 -10 2 1 6 10 0.75 VCCA - 2.6 10 12 mV A M V V nV/Hz dB 20MHz, RL = 200 20MHz, RL = 200 VOUT = 2VP-P 650 600 1500 20 1300 -70 -70 75 0.01 0.01 MHz MHz V/s ns MHz dBc dBc dB % 1 10 VCC - 1 V M
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FN6372.3 April 25, 2007
ISL59311
Electrical Specifications
DESCRIPTION PSRR VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25C, VIN = 0V, RL = 200, unless otherwise specified. (Continued) CONDITION Rejection of VCCA MIN 60 TYP 75 MAX UNIT dB
Digital Transceiver Block Electrical Characteristics TRANSMITTER DC CHARACTERSTICS SOUT Differential Output Voltage No load RL = 100 (Figure 1A) Change in Magnitude of Driver Differential SOUT for Complementary Output States SOUT Common-Mode Voltage (deviation from VCCD/2) SOUT Short Circuit Current RL = 100 (Figure 1A) |(SOUT+) - (SOUT-)| RL = 100 (Figure 1A) Driving high, output tied to GND Driving low, output tied to VCCD SOUT Leakage Current SOUT (Transmit = GND) -0.1 3.0 VCCD 3.3 .08 0.06 95 95 2 0.2 +0.1 110 110 100 V V V V mA mA nA
TRANSMITTER SWITCHING CHARACTERISTICS Maximum Data Rate Differential Propagation Delay RL = 100, (Figure 1A) tPLH (Figure 2, RDIFF = 100) tPHL (Figure 2, RDIFF = 100) Differential Output Skew Output Enable Time |tPLH - tPHL| (Figure 2, RDIFF = 100) tPZH: Driver Enable to Output High (Figure 3, ISINK = 1mA, ISOURCE = off) tPZL: Driver Enable to Output Low (Figure 3, ISINK = off, ISOURCE = 1mA) Output Disable Time tPHZ: Output High to Output Disabled (Figure 3, ISINK = 25mA, ISOURCE = off) tPLZ: Output Low to Output Disabled (Figure 3, ISINK = off, ISOURCE = 25mA) Disabled Output Leakage RECEIVER DC CHARACTERISTICS SIN Input Hysteresis SIN Input Range SIN Input Resistance; Each Input to GND RECEIVER SWITCHING CHARACTERISTICS Maximum Data Rate Receiver Input to Output Propagation Delay Driven with 100mV differential signal (Figure 4, Note 4) TPLH (Figure 4) TPHL (Figure 4) Receiver Skew tRISE/tFALL Receiver Enable to Output High Receiver Enable to Output Low Receiver High to Hi-Z |tPLH - tPHL| (Figure 4) 100k II10pF load 50 4.7 5.5 0.8 2 15 35 15 20 42 25 8 8 2 Mbps ns ns ns ns ns ns ns VCM = 2.5V 2 GND - 0.5 2.5 3.0 30 50 VCC + 0.5 3.5 mV V k 50 6 6 2 4 6 28 28 2 10 10 4 20 20 35 35 100 Mbps ns ns ns ns ns ns ns nA
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FN6372.3 April 25, 2007
ISL59311
Electrical Specifications
DESCRIPTION Receiver Low to Hi-Z System Logic Inputs DC Characteristics VSYNC, HSYNC, TRANSMIT, AND DISABLE INPUT CHARACTERISTICS Input High Voltage Input Low Voltage VSYNC, HSYNC, Transmit Input Current Disable Pin Pull-down Resistance to GNDA VIH VIL IIN RDisable 1 500 2 0.8 5 V V A k VCCA = VCCD = VCCS = +5V, GNDA = GNDD = 0V, TA = +25C, VIN = 0V, RL = 200, unless otherwise specified. (Continued) CONDITION MIN TYP 10 MAX 20 UNIT ns
SDATA INPUT CHARACTERISTICS (Transmit = VCCD) Input High Voltage Input Low Voltage Input Current VIH VIL IIN 0.001 0.7 VCCS 0.3 VCCS 1 V V A
SDATA OUTPUT CHARACTERISTICS (Transmit = GND) High Output Level Low Output Level Short Circuit Output Current Sourcing 4mA to GND Sinking 4mA from VCCS Driving high, output tied to GND Driving low, output tied to VCCS Power Supply Characteristics VCCA Operating Range VCCA Supply Current (all 3 channels) Operating (Disable = GND) Disabled (Disable = VCCA) VCCD Operating Range VCCD Supply Current VCCS Input Impedance NOTES: 1. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 2. VCCS current is equal to the VCCS voltage applied divided by the VCCS Input Impedance. Some additional current is consumed when SDATA is driving high into the external load. 3. Applies to peak current. See "Typical Performance Curves" for more information. 4. Guaranteed by characterization but not tested. VCCS = 5V (Note 2) 4 4.5 7 5 4.5 50 2.3 5.5 60 3 5.5 12 6 V mA mA V mA k 4.5 4.7 0.3 20 40 0.4 V V mA mA
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FN6372.3 April 25, 2007
ISL59311 Test Circuits and Waveforms
50 SDATA SOUTD SOUT+ 50 VOC VOD SDATA SOUTD SOUT+ VOD
50 VCM 0V to 5V 50
FIGURE 1A. VOD AND VOC
FIGURE 1B. VOD WITH COMMON MODE LOAD FIGURE 1. DC DRIVER TEST CIRCUITS
5V DI 2.5V 2.5V 0V CL = 50pF tPLH SOUTtPHL VOH VOL
SDATA D
SOUT100 SOUT+ CL = 50pF
SOUT+
SIGNAL GENERATOR DIFF OUT (SOUT+ - SOUT-) 90% 10% tR SKEW = |tPLH - tPHL| 90% 10% tF
+VOD -VOD
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
TRANSMIT SDATA D SIGNAL GENERATOR SOUT SOUT 50pF ISOURCE SOUT tPZL tPZH
2.5V
2.5V tPHZ 90%
3.5V
ISINK
tPLZ 1.5V 10%
FIGURE 3A. TEST CIRCUIT FIGURE 3. DRIVER DATA RATE
FIGURE 3B. MEASUREMENT POINTS
4.0V 2.5V SINSIN+ R SIN+ SDATA 50pF tPLH SIGNAL GENERATOR 1.5V tPHL VCCS = 5V SDATA 1.5V 0V 2.5V 2.5V 1.0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY AND DATA RATE
7
FN6372.3 April 25, 2007
ISL59311 Typical Performance Curves
BLUE CM OUT (CH C) GREEN CM OUT (CH B) RED CM OUT (CH A) VSYNC HSYNC TIME (0.5ms/DIV) RL = 100 RL = 50 VCCA = 5V CL = 0pF CHAN A RL = 500 RL = 200
VOLTAGE (2.5V/DIV)
VOLTAGE (0.5V/DIV)
FIGURE 5. COMMON MODE OUTPUT
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF (CHANNEL A)
VCCA = 5V CL = 0pF CHAN B
RL = 500 RL = 200
VCCA = 5V CL = 0pF CHAN C
RL = 500 RL = 200
RL = 100 RL = 50
RL = 100 RL = 50
FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF (CHANNEL B)
FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF (CHANNEL C)
VCCA = 5V RL = 200 CHAN A
CL = 12pF CL = 8.2pF
VCCA = 5V RL = 200 CHAN B
CL = 12pF CL = 8.2pF
CL = 4.7pF CL = 2.2pF
CL = 4.7pF CL = 2.2pF
FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF (CHANNEL A)
FIGURE 10. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF (CHANNEL B)
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FN6372.3 April 25, 2007
ISL59311 Typical Performance Curves
VCCA = 5V RL = 200 CHAN C CL = 12pF CL = 8.2pF
(Continued)
VCCA = 5V RL = 200 THD OUTPUT C
CL = 4.7pF OUTPUT B CL = 2.2pF
OUTPUT A
FIGURE 11. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF (CHANNEL C)
FIGURE 12. TOTAL HARMONIC DISTORTION
VCCA = 5V RL = 200 2ND HARMONIC OUTPUT B OUTPUT A
VCCA = 5V RL = 200 3RD HARMONIC OUTPUT C
OUTPUT A OUTPUT C OUTPUT B
FIGURE 13. 2ND HARMONIC DISTORTION
FIGURE 14. 3RD HARMONIC DISTORTION
RL = 200 DIFF CL = 0pF VOLTAGE (235mV/DIV) VOLTAGE (120mV/DIV)
RL = 200 DIFF CL = 0pF
RISE t = 1.2ns
FALL t = 1.1ns
RISE t = 1.4ns
FALL t = 1.3ns
TIME (20ns/DIV)
TIME (20ns/DIV)
FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 16. DIFFERENTIAL SMALL SIGNAL TRANSIENT RESPONSE
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FN6372.3 April 25, 2007
ISL59311 Typical Performance Curves
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 POWER DISSIPATION (W) POWER DISSIPATION (W) 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 2.857W
Q J 3 2 /W FN C 5 =3
A
0.8
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD
0.7 758mW 0.6
J
A
Q
3 2 /W F N 5 C 2 =1
0.5 0.4 0.3 0.2 0.1 0 0 25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Operational Description and Application Information
Introduction
The ISL59311 is designed to differentially drive composite RGB video signals onto twisted pair lines, while simultaneously encoding horizontal and vertical sync signals as common mode output. The entire video signal plus sync can therefore be transmitted on 3 twisted pairs of wire. When utilizing CAT5 cable, the 4th available twisted pair can be used for transmission of audio, data or control information. The distribution of composite video over standard CAT5 cable enables enormous cost and labor savings compared with traditional coaxial cable, when considering both the relative low price and ease of pulling CAT5 cable. The digital block of the chip is a data transceiver which is intended to drive one twisted pair line. The maximum baudrate for this block is 50Mbps.
consists of three fully differential video signals, with sync encoded on the common mode of each of the three RGB differential signals. HSYNC and VSYNC can easily be separated from the differential output signals, decoded and transmitted along with the RGB video signals to the video monitor.
Sync Transmission
The ISL59311 encodes HSYNC and VSYNC signals on the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Table 1 shows the common mode levels for the different SYNC input combinations. Note that the sum of the common mode voltages results in a fixed average DC level with no AC content. This dramatically reduces EMI radiation into any common mode signal along the twisted pairs of CAT5 cable.
Extract Common Mode Sync and Decode HSYNC and VSYNC
HSYNC and VSYNC can be regenerated from the Common Mode sync output voltages. The relationships between HSYNC, VSYNC and the 3 common mode levels are given by Table 1. The common mode levels are easily separated from the differential outputs of the ISL59311 using this simple resistor network at the cable receiver input of each differential channel; see Figure 20.
TABLE 1. SYNC SIGNAL ENCODING COMMON MODE A (RED) 3.0 2.5 2.0 2.5 COMMON MODE B (GREEN) 2.0 3.0 3.0 2.0 COMMON MODE C (BLUE) 2.5 2.0 2.5 3.0
Functional Description
The ISL59311 provides three fully differential high-speed amplifiers, suitable for driving high-resolution composite video signals onto twisted pair or standard coaxial cable. The input common-mode range extends to the negative rail, allowing simple ground-referenced input termination to be used with a single supply. The amplifiers provide a fixed gain of +2 to compensate for standard video cable termination schemes. Horizontal and Vertical sync signals (HSYNC and VSYNC) are passed to an internal Logic Encoding Block to encode the sync information as three discrete signals of different voltage levels. Generally, in differential amplifiers an external VREF pin is used to control the common mode level of the differential output; in the case of the ISL59311 the VREF of each of the three internal amplifier channels receives a signal from the Logic Encoding Block with encoded HSYNC and VSYNC information. The final output
HSYNC Low Low High High
VSYNC High Low Low High
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FN6372.3 April 25, 2007
ISL59311
Long Distance Video Transmission
+ VINA DISABLE + + VOUTA VREF DISABLE + + VOUTB VREF DISABLE + + VOUTC VREF
VSYNC HSYNC DISABLE LOGIC DECODING
CMA CMB CMC
+ VINB -
+ VINC -
FIGURE 19. VIDEO DRIVER BLOCK DIAGRAM
Twisted Pair Termination
The schematic in Figure 20 illustrates a termination scheme for 50 series termination and a 100 twisted pair cable. Note RCM is the common mode termination to allow measurement of VCM and should not be too small since it loads the ISL59311; a little over a 100 is recommended for RCM.
50 + 50 VREF TWISTED PAIR ZO =100 + 50 VCM 50 120 (RCM: SHOULD BE >100) (FOR LOADING CONSIDERATIONS)
The SXGA Video Transmission System makes it possible to transmit Red, Green and Blue (RGB) video plus sync up to 1000ft through CAT5 cable. The input to the SXGA Video Transmission System is the output of a video source transmitting RGB video signals plus sync. The signals are received initially by the ISL59311; which converts the single ended input RGB signals to three fully differential waveforms with sync encoded on the discrete common modes of each color channel and then drives the signals through a length of CAT5 cable. The signal is received by the EL9111, which can provide 6-pole equalization for both high and low frequency signal transmission line losses. Then the EL9111 converts the differential RGB video signals back into single ended format while extracting the common mode component for decoding. The single ended RGB signal is taken directly from the output of the EL9111 and is ready for the output device. The EL9111 Common Mode Decoder Circuit receives the common mode signals and decodes them and transmits HSYNC and VSYNC to the output device.
DISABLE
Disabling the Amplifiers with the Disable Pin
The Disable pin must be a logic low for normal operation of the video amplifiers. When Disable is taken high, the amplifiers are disabled, reducing supply VCCA supply current. (The Disable pin has no effect on the Serial Digital Transceiver - it is always enabled as long as power is applied to VCCD.)
Serial Digital Transceiver Operation
The digital transceiver is a half-duplex design, either receiving data on the SIN pins and sending it out on the SDATA pin, or transmitting data from the SDATA pin out on some the 2 SOUT pins. The digital transceiver operates in a high speed (up to 50MBaud) differential mode. The SDATA pin is the half-duplex logic-level transmit and receive data pin. SDATA is an output when Transmit = low (receive mode) and an input when Transmit = high (transmit mode). This can be made to work with existing designs that use independent transmit and receive pins by connecting SDATA directly to the transmit pin and through a resistor to the receive pin. Figure 21 shows an example of how to interface the ISL59311 with an RS485 transceiver. VCCD is the power source for the digital line interface drivers and receivers.
FIGURE 20. TWISTED PAIR TERMINATION
Video Transmission
The ISL59311 is a twisted pair differential line driver directed at the transmission of Video Signals through cables up to 100 feet; however, as signal losses increase with transmission line length the ISL59311 will need additional support to equalize video signals along longer twisted pair transmission lines. A full solution to accomplish this is the SXGA Video Transmission System presented in the ISL59311 Data Sheet. Note the inclusion of the EL9111 for signal equalization of up to 1000ft of CAT5 cable and common mode extraction; see Data Sheet for additional information on the EL9111.
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FN6372.3 April 25, 2007
ISL59311
+5V + 19 VCCS 11 SDATA R SIN+ SINSOUT+ 12 TRANSMIT SOUTD GND ISL59311 7 GND 5 ISL83088 15 16 17 13 RT RT 7 6 B/Z A/Y 0.1F 0.1F + 8 VCC D DI 4 DE 3 RE 2 R RO 1 +5V
FIGURE 21. RS-485 SERIAL INTERFACE CONNECTION DIAGRAM
Digital Transceiver Block Diagram
TXEN SOUT+ R1 TWISTED PAIR LINE
Proper Layout Technique
A critical concern with any PCB layout is the establishment of a "healthy" ground plane. It is imperative to provide ground planes terminated close to inputs to minimize input capacitance. Additionally, the ground plane can be selectively removed from inputs to prevent load and supply currents from flowing near the input nodes. In general the following guidelines apply to all PCB layout: * Keep all traces as short as possible. * Keep power supply bypass components as close to the chip as possible - extremely close. * Create a healthy ground with low impedance and continuous ground pathways available to all grounded components board-wide. * In high frequency applications on multi-level boards try to keep one level of board with continuous ground plane and minimum via cutouts - providing it is affordable.
TXDATA (SDATA) TRANSMIT
ENCODING
SOUT-
R3
RDATA (SDATA)
SIN+ SIN-
* Provide extremely short loops from power pin to ground. * If it is affordable, a ferrite bead is always of benefit to isolate device from Power Supply noise and the rest of the circuit from the noise of the device.
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FN6372.3 April 25, 2007
ISL59311
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the ISL59311 drive capability is ultimately limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (+125C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated:
4 2 2 PD = ( V S x I S ) x ( C INT x V S x f ) + ( C L x V OUT x f ) 1
where: * VS is the total power supply to the ISL59311 (= VCCD) * VOUT is the swing on the output (VH - VL) * CL is the load capacitance * CINT is the internal load capacitance (80pF max) * IS is the quiescent supply current * f is frequency Having obtained the application's power dissipation, the maximum junction temperature can be calculated:
T JMAX = T MAX + JA x PD
where: * TJMAX is the maximum junction temperature (+125C) * TMAX is the maximum ambient operating temperature * PD is the power dissipation calculated above JA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves. See Technical Bulletin 389 (http://www.intersil.com/data/tb/TB389.pdf) for additional QFN PCB layout information.
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FN6372.3 April 25, 2007
ISL59311 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
A D N (N-1) (N-2) B
L32.5x6A (One of 10 Packages in MDP0046) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220)
MILLIMETERS SYMBOL A A1 MIN 0.80 0.00 NOMINAL 0.90 0.02 5.00 BSC 2.48 REF 6.00 BSC 3.40 REF 0.45 0.20 0.50 0.22 0.20 REF 0.50 BSC 32 REF 7 REF 9 REF 0.55 0.24 MAX 1.00 0.05 NOTES 4 6 5 Rev 0 9/05 NOTES:
1 2 3
D
PIN #1 I.D. MARK E
D2 E E2 L b
2X 0.075 C
c
2X 0.075 C
(N/2) TOP VIEW N LEADS 0.10 M C A B (N-2) (N-1) N b
e N ND NE
L
PIN #1 I.D. 3 1 2 3
1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the "E" side of the package (or Y-direction).
(E2)
NE 5 (N/2)
6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown.
(D2) BOTTOM VIEW
7
e C
0.10 C (c) 2
SEATING PLANE 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X"
C
A
(L) A1 N LEADS
SIDE VIEW
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6372.3 April 25, 2007

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