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PCF2123
SPI Real time clock/calendar
Rev. 01 -- 19 November 2008 Product data sheet
1. General description
The PCF2123 is a CMOS real time clock and calendar optimized for low power applications. Data is transferred serially via a Serial Peripheral Interface bus (SPI-bus) with a maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing the possibility to generate a wake-up signal on an interrupt pin. An offset register allows fine tuning of the clock.
2. Features
I Real time clock provides year, month, day, weekday, hours, minutes and seconds based on a 32.768 kHz quartz crystal I Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb = 25 C I Resolution: seconds to years I Watchdog functionality I Freely programmable timer and alarm with interrupt capability I Clock operating voltage: 1.1 V to 5.5 V I 3 line SPI-bus with separate combinable data input and output I Serial interface at VDD = 1.6 V to 5.5 V I 1 second or 1 minute interrupt output I Integrated oscillator load capacitors for CL = 7 pF I Internal power-on reset I Open-drain interrupt and clock output pins I Programmable offset register for frequency adjustment
3. Applications
I I I I I I Time keeping application Battery powered devices Metering High duration timers Daily alarms Low standby power applications
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
4. Ordering information
Table 1. Ordering information Package Name PCF2123TS PCF2123BS TSSOP14 HVQFN16 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm Version SOT402-1 SOT758-1 Type number
PCF2123U
[1]
PCF2123U/10 wire bond die; 12 bonding pads; 1.492 x 1.449 x 0.20 mm[1]
PCF2123U/10
Sawn wafer on Film Frame Carrier (FFC); 200 m thickness.
5. Marking
Table 2. Marking codes Marking code PCF2123 123 PC2123-1 Type number PCF2123TS PCF2123BS PCF2123U
PCF2123_1
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PCF2123
SPI Real time clock/calendar
6. Block diagram
OSCI OSCILLATOR 32.768 kHz OSCO MONITOR 0D OFFSET FUNCTION OFFSET TIMER FUNCTION 0E TIMER/CLKOUT CONTROL 0F COUNTDOWN TIMER CONTROL 00 POWER ON RESET 01 CONTROL/STATUS 1 CONTROL/STATUS 2 TIME 02 WATCH DOG 03 04 05 06 SDO SDI SCL CE SPI INTERFACE 07 08 OS/SECONDS VL/MINUTES HOURS DAYS WEEKDAYS MONTHS YEARS ALARM FUNCTION 09 0A MINUTE HOUR DAY WEEKDAY
001aah665
CLKOE DIVIDER CLOCK OUT CLKOUT
TEST VDD VSS
INTERRUPT
INT
PCF2123
0B 0C
Fig 1.
Block diagram of PCF2123
PCF2123_1
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PCF2123
SPI Real time clock/calendar
7. Pinning information
7.1 Pinning
16 OSCI 13 VDD 12 CLKOUT 11 CLKOE 10 SCL 9 5 6 7 8 SDI SDO
15 n.c. n.c.
terminal 1 index area OSCI OSCO n.c. TEST INT CE VSS 1 2 3 4 5 6 7
001aai551
14 VDD 13 CLKOUT 12 CLKOE OSCO TEST INT CE 1 2
PCF2123
11 n.c. 10 SCL 9 8 SDI SDO
PCF2123
3 4
VSS
n.c.
14 n.c.
001aai550
Transparent top view
Top view. For mechanical details, see Figure 29.
For mechanical details, see Figure 30.
Fig 2.
Pinning diagram of PCF2123TS (TSSOP14)
Fig 3.
Pinning diagram of PCF2123BS (HVQFN16)
6 OSCI 7 5 OSCO 8 4 TEST INT CE VSS 9 10 11 12 2
VDD CLKOUT CLKOE
PCF2123U/10
3 SCL SDI
1
SDO
001aai544
Top view. For mechanical details, see Figure 31 and Figure 33.
Fig 4.
Pinning diagram of PCF2123U (bare die)
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PCF2123
SPI Real time clock/calendar
7.2 Pin description
Table 3. Symbol OSCI OSCO n.c. TEST INT CE VSS SDO SDI SCL CLKOE CLKOUT VDD Pin description Pin TSSOP14 1 2 3, 11 4 5 6 7 8 9 10 12 13 14 HVQFN16 16 1 6, 7, 14, 15 2 3 4 5[1] 8 9 10 11 12 13 PCF2123U/10 7 8 9 10 11 12[2] 1 2 3 4 5 6 oscillator input; high-impedance node; minimize wire length between quartz and package oscillator output; high-impedance node; minimize wire length between quartz and package do not connect and do not use as feed through; connect to VDD if floating pins are not allowed test pin; not user accessible; connect to VSS or leave floating (internally pulled down) interrupt output (open-drain; active LOW) chip enable input (active HIGH) with internal pull down ground serial data output, push-pull; high-impedance when not driving; can be connected to SDI for single wire data line serial data input; may float when CE is inactive serial clock input; may float when CE is inactive CLKOUT enable or disable pin; enable is active HIGH clock output (open-drain) supply voltage; positive or negative steps in VDD may affect oscillator performance; recommend 10 nF decoupling close to device (see Figure 28) Description
[1] [2]
The die paddle (exposed pad) is wired to VSS but should not be electrically connected. The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
8. Device protection diagram
PCF2123
VDD OSCI CLKOE OSCO CLKOUT TEST SCL INT SDI CE SDO VSS
001aai552
Fig 5.
Device diode protection diagram of PCF2123
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PCF2123
SPI Real time clock/calendar
9. Functional description
The PCF2123 contains sixteen 8-bit registers with an auto-incrementing address counter, an on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock. All sixteen registers are designed as addressable 8-bit parallel registers although not all bits are implemented.
* The first two registers (memory address 00h and 01h) are used as control registers. * The memory addresses 02h through 08h are used as counters for the clock function
(seconds up to years). The Seconds, Minutes, Hours, Days, Weekdays, Months and Years registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock and calendar during a carry condition is prevented.
* * * *
Addresses 09h through 0Ch define the alarm condition. Address 0Dh defines the offset calibration. Address 0Eh defines the clock out and timer mode. Address registers 0Eh and 0Fh are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 s up to four hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. These are defined in register Control_2 (01h).
9.1 Low power operation
Minimum power operation will be achieved by reducing the number and frequency of switching signals inside the IC, i.e. low frequency timer clocks and a low frequency CLKOUT will result in lower operating power. A second prime consideration is the series resistance Rs of the quartz used.
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PCF2123
SPI Real time clock/calendar
9.1.1 Power consumption with respect to quartz series resistance
The series resistance acts as a loss element. Low Rs will reduce current consumption further.
250 IDD (nA)
(1)
001aai558
210
170
130
90
50 0 20 40 60 80 Rs(2) (k) 100
Configuration: CLKOUT disabled, VDD = 3 V, timer clock set to 160 Hz. (1) IDD (nA) minimum power mode.
Fig 6.
IDD with respect to quartz RS
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PCF2123
SPI Real time clock/calendar
9.1.2 Power consumptions with respect to timer mode
Four source clocks are possible for the timer. The 4.096 kHz source clock will add the greatest part to the power consumption. The selection of 64 Hz, 1 Hz or 160 Hz will be almost indistinguishable and add very little.
400 IDD(1) (nA) 300
001aai559
(2)
200
(3)
100
0 0 2 4 VDD (V) 6
Configuration: CLKOUT disabled, quartz RS = 15 k. (1) IDD (nA) minimum power mode. (2) Timer clock = 4 kHz. (3) Timer clock = 64 Hz, 1 Hz, 160 Hz.
Fig 7.
IDD with respect to timer clock selection
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SPI Real time clock/calendar
9.2 Register overview
16 registers are available. The time registers are encoded in the binary coded decimal format (BCD) to simplify application use. Other registers are either bit-wise or standard binary.
Table 4. Registers overview Bit positions labelled as - are not implemented and will return a 0 when read. Bit positions labelled with 0 should always be written with logic 0[1]. Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
[1]
Register name Control_1 Control_2 Seconds Minutes Hours Days Weekdays Months Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm Offset_register Timer_clkout Countdown_timer
Bit 7 EXT_TEST MI OS AEN_M AEN_H AEN_D AEN_W MODE 6 0 SI 5 STOP MSF 4 SR TI_TP 3 0 AF 2 12_24 TF 1 CIE AIE 0 0 TIE
SECONDS (0 to 59) MINUTES (0 to 59) AMPM HOURS (1 to 12) in 12 h mode HOURS (0 to 23) in 24 h mode DAYS (1 to 31) WEEKDAYS MONTHS (1 to 12)
YEARS (0 to 99) MINUTE_ALARM (0 to 59) OFFSET COF2 COF1 COF0 TE CTD1 CTD0 AMPM HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM (0 to 23) in 24 h mode DAY_ALARM (1 to 31) WEEKDAY_ALARM
COUNTDOWN_TIMER
Except in the case of software reset, see Section 9.5
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PCF2123
SPI Real time clock/calendar
9.3 Control registers
9.3.1 Register Control_1
Table 5. Bit 7 6 5 Register Control_1 (address 00h) bits description Value 0 1 STOP 0 1 Description normal mode external clock test mode unused the RTC source clock runs the RTC clock is stopped; RTC divider chain flip-flops are asynchronously set to logic 0; CLKOUT at 32.768 kHz, 16.384 kHz or 8.192 kHz is still available 4 SR 0 1 no software reset initiate software reset[1]; this register will always return a 0 when read 3 2 1 12_24 CIE 0 1 0 1 0
[1]
Symbol EXT_TEST
Reference Section 9.12 Section 9.13
Section 9.5
unused 24 hour mode is selected 12 hour mode is selected no correction interrupt generated interrupt pulses will be generated at every correction cycle unused
Section 9.11
-
-
-
To prevent an accidental software reset, 01011000 (58h) must be sent to register Control_1 (see Section 9.5).
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SPI Real time clock/calendar
9.3.2 Register Control_2
Table 6. Bit 7 6 5 MI SI MSF Register Control_2 (address 01h) bits description Value 0 1 0 1 0 1 Description minute interrupt is disabled minute interrupt is enabled second interrupt is disabled second interrupt is enabled no minute or second interrupt generated flag set when minute or second interrupt generated; flag must be cleared to clear interrupt when TI_IP = 0 4 3 TI_TP AF 0 1 0 1 2 TF 0 1 interrupt pin follows timer flags interrupt pin generates a pulse no alarm interrupt generated flag set when alarm triggered; flag must be cleared to clear interrupt no countdown timer interrupt generated flag set when countdown timer interrupt generated; flag must be cleared to clear interrupt when TI_IP = 0 1 0 AIE TIE 0 1 0 1 no interrupt generated from the alarm flag interrupt generated when alarm flag set no interrupt generated from the countdown Section 9.9.2 timer interrupt generated by the countdown timer Section 9.9.3 Section 9.7.1 Section 9.9.2 Reference Section 9.8.1 Symbol
9.4 OS flag
The PCF2123 includes a flag (bit OS) which is set whenever the oscillator is stopped (see Figure 8 and Figure 9). The flag will remain set until cleared by software. If the flag cannot be cleared, then the PCF2123 oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails.
main supply VDD battery operation
VOSC(MIN) t
001aai561
Fig 8.
OS set by failing VDD
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PCF2123
SPI Real time clock/calendar
OS = 1 and flag can not be cleared
OS = 1 and flag can be cleared
VDD
oscillation OS flag set when oscillation stops
OS flag OS flag cleared by software oscillation now stable
t
001aai553
Fig 9.
OS flag
The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s depending on crystal type, temperature and supply voltage. At power-on the OS flag is always set.
9.5 Reset
A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. It is generally recommended to make a software reset after power-on. A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 to logic 1 and all other bits to logic 0 by sending the bit sequence 01011000 (58h), see Figure 10. If this bit sequence is not correct, the software reset instruction will be ignored to protect the device from accidently being reset. When sending the software instruction, the other bits are not written. The SPI-bus is reset whenever the chip enable pin CE is inactive.
R/W b7 0 SCL CE internal reset signal b6 0 b5 0 b4 1 b3 0
addr 00HEX b2 0 b1 0 b0 0 b7 0 b6 1
software reset 58HEX b5 0 b4 1 b3 1 b2 0 b1 0 b0 0
(1)
001aai562
(1) When CE is inactive, the interface is reset.
Fig 10. Software reset command
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SPI Real time clock/calendar
Table 7. Register reset values Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Register name Control_1 Control_2 Seconds Minutes Hours Days Weekdays Months Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm Offset_register Timer_clkout Countdown_timer Bit 7 0 0 1 1 X 1 1 1 1 0 X 6 0 0 X X X X 0 0 X 5 0 0 X X X X X X X X 0 0 X 4 0 0 X X X X X X X X X 0 0 X 3 0 0 X X X X X X X X X 0 0 X 2 0 0 X X X X X X X X X X X 0 X 1 0 0 X X X X X X X X X X X 0 1 X 0 0 0 X X X X X X X X X X X 0 1 X
After reset, the following mode is entered:
* * * * * *
32.768 kHz on pin CLKOUT active 24 hour mode is selected Offset register is set to 0 No alarms set Timer disabled No interrupts enabled
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SPI Real time clock/calendar
9.6 Time and date function
The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the Minutes register in Table 8.
Table 8. BCD example Upper-digit Bit 7 0 0 0 : 0 0 : 0 0 Bit 6 0 0 0 : 0 0 : 1 1 Bit 5 0 0 0 : 0 0 : 0 0 Bit 4 0 0 0 : 0 1 : 1 1 Digit Bit 3 0 0 0 : 1 0 : 1 1 Bit 2 0 0 0 : 0 0 : 0 0 Bit 1 0 0 1 : 0 0 : 0 0 Bit 0 0 1 0 : 1 0 : 0 1
Minutes value (decimal) 00 01 02 : 09 10 : 58 59 Table 9. Bit 7
Register Seconds (address 02h) bits description Symbol OS Value 0 1 Description clock integrity is guaranteed clock integrity is not guaranteed; oscillator has stopped or been interrupted this register holds the current seconds coded in BCD format
6 to 0
[1]
SECONDS
00 to 59[1]
Values shown in decimal.
Table 10. Bit 7 6 to 0
[1]
Register Minutes (address 03h) bits description Symbol MINUTES Value 00 to 59[1] Description unused this register holds the current minutes coded in BCD format
Values shown in decimal.
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SPI Real time clock/calendar
Register Hours (address 04h) bits description Symbol mode[2] AMPM HOURS 0 1 01 to 12[1] indicates AM indicates PM this register holds the current hours coded in BCD format for 12 hour mode this register holds the current hours coded in BCD format for 24 hour mode Value Description unused
Table 11. Bit 7 and 6 12 hour 5 4 to 0
24 hour mode[2] 5 to 0
[1] [2]
HOURS
00 to 23[1]
Values shown in decimal. Hour mode is set by the 12_24 bit in register Control_1.
Table 12. Bit 7 and 6 5 to 0
[1] [2]
Register Days (address 05h) bits description Symbol DAYS Value 01 to 31[1] Description unused this register holds the current day coded in BCD format[2]
Values shown in decimal. The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00.
Table 13. Bit 7 to 3 2 to
[1] [2]
Register Weekdays (address 06h) bits description Symbol WEEKDAYS Value 0 to 6[2] Description unused this register holds the current weekday, see Table 14
0[1]
These bits may be re-assigned by the user. Values shown in decimal.
Table 14. Day[1] Sunday Monday Tuesday
Weekday assignments Upper-digit Bit 7 X X X X X X X Bit 6 X X X X X X X Bit 5 X X X X X X X Bit 4 X X X X X X X Digit Bit 3 X X X X X X X Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0
Wednesday Thursday Friday Saturday
[1]
The weekday assignments may be re-defined by the user.
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Register Months (address 07h) bits description Symbol MONTHS Value 01 to 12[1] Description unused this register holds the current month coded in BCD format, see Table 16
Table 15. Bit 7 to 5 4 to 0
[1]
Values shown in decimal.
Table 16. Month January February March April May June July August September October November December Table 17. Bit 7 to 0
[1]
Month assignments Upper-digit Bit 7 X X X X X X X X X X X X Bit 6 X X X X X X X X X X X X Bit 5 X X X X X X X X X X X X Bit 4 0 0 0 0 0 0 0 0 0 1 1 1 Digit Bit 3 0 0 0 0 0 0 0 1 1 0 0 0 Bit 2 0 0 0 1 1 1 1 0 0 0 0 0 Bit 1 0 1 1 0 0 1 1 0 0 0 0 1 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0
Register Years (address 08h) bits description Symbol YEARS Value 00 to 99[1] Description this register holds the current year coded in BCD format
Values shown in decimal.
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SPI Real time clock/calendar
9.6.1 Data flow
Figure 11 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
HOURS
LEAP YEAR CALCULATION
DAYS
WEEKDAY
MONTHS
YEARS
001aaf901
Fig 11. Data flow for the time function
In order to read the correct time it is important to read all time registers in one access i.e. seconds up to years. If the time registers are read by making individual access to the chip, then there is the risk that the time will increment between accesses.
9.7 Alarm function
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding alarm enable not bit (AEN_x) is logic 0, then that information will be compared with the current minute, hour, day and weekday.
Table 18. Bit 7 6 to 0
[1]
Register Minute_alarm (address 09h) bits description Symbol AEN_M Value 0 1 MINUTE_ALARM 00 to 59[1] Description minute alarm is enabled minute alarm is disabled this register holds the minute alarm information coded in BCD format
Values shown in decimal.
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Register Hour_alarm (address 0Ah) bits description Symbol AEN_H AMPM HOUR_ALARM Value 0 1 0 1 01 to 12[1] Description hour alarm is enabled hour alarm is disabled unused indicates AM indicates PM this register holds the hour alarm information coded in BCD format when in 12 hour mode this register holds the hour alarm information coded in BCD format when in 24 hour mode
Table 19. Bit 7 6 5 4 to 0
12 hour mode
24 hour mode 5 to 0
[1]
HOUR_ALARM
00 to 23[1]
Values shown in decimal.
Table 20. Bit 7 6 5 to 0
[1]
Register Day_alarm (address 0Bh) bits description Symbol AEN_D DAY_ALARM Value 0 1 01 to 31[1] Description day alarm is enabled day alarm is disabled unused this register holds the day alarm information coded in BCD format
Values shown in decimal.
Table 21. Bit 7 3 to 6 2 to 0
[1]
Register Weekday_alarm (address 0Ch) bits description Symbol AEN_W WEEKDAY_ ALARM Value 0 1 0 to 6[1] Description weekday alarm is enabled weekday alarm is disabled unused this register holds the weekday alarm information
Values shown in decimal.
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check now signal MINUTE AEN MINUTE ALARM = MINUTE TIME
example MINUTE AEN = 1 1 0 HOUR AEN
HOUR ALARM = HOUR TIME set alarm flag, AF(1) DAY AEN DAY ALARM = DAY TIME
WEEKDAY AEN WEEKDAY ALARM = WEEKDAY TIME
001aaf902
(1) Only when all enabled alarm settings are matching.
Fig 12. Alarm function block diagram
The generation of interrupts from the alarm function is described in Section 9.9.3.
9.7.1 Alarm flag
When all enabled comparisons first match, the alarm flag bit AF is set. Bit AF will remain set until cleared by software. Once bit AF has been cleared it will only be set again when the time increments to match the alarm condition. Alarm registers which have bit AEN_x at logic 1 are ignored. Table 23 shows an example for clearing bit AF but leaving bit MSF and bit TF unaffected. Clearing the flags is made by a write command; therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
minutes counter
44
45
46
minute alarm
45
AF
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 13. AF timing
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To prevent the timer flags being overwritten while clearing AF, a logical AND is performed during a write access. Writing a logic 1 will cause the flag to maintain its value, whereas writing a logic 0 will cause the flag to be reset.
Table 22. Register Control_2 Flag location in register Control_2 Bit 7 6 5 MSF 4 3 AF 2 TF 1 0 -
The following tables show what instruction must be sent to clear bit AF. In this example, bit MSF and bit TF are unaffected.
Table 23. Register Control_2 Example to clear only AF (bit 3) in register Control_2 Bit 7 6 5 1 4 3 0 2 1 1 0 -
9.8 Timer functions
The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 s to 4 h 15 min. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. For periods greater than 4 hours, the alarm function can be used. Registers 01h, 0Eh and 0Fh are used to control the timer function and output.
Table 24. Bit 7 3 2 TE Register Timer_clkout (address 0Eh) bits description Value [1]
Symbol
Description unused CLKOUT control countdown timer is disabled countdown timer is enabled unused 4.096 kHz countdown timer source clock 64 Hz countdown timer source clock 1 Hz countdown timer source clock
1 Hz 60
Reference Section 9.10 Section 9.8.2
6 to 4 COFx
0 1 00 01 10 11
1 to 0 CTD
countdown timer source clock
[1]
Values of COF[2:0] see Table 35.
Table 25. Bit
Register Countdown_timer (address 0Ah) bits description Value 0h to FFh Description countdown value = n; Reference Section 9.8.2 n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency
Symbol
7 to 0 COUNTDOWN_ TIMER
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9.8.1 Minute and second interrupt
The minute and second interrupts (bits MI and SI) are pre-defined timers for generating periodic interrupts. The timers can be enabled independently from one another. However, a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 14.
seconds counter
58
59
59
00
00
01
minutes counter
11
12
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
001aaf905
In this example, TI_TP is set to logic 1 resulting in 164 Hz wide interrupt pulse and the MSF flag is not cleared after an interrupt.
Fig 14. INT example for MI and SI Table 26. 0 1 0 1 Effect of bits MI and SI on INT generation Second interrupt (bit SI) 0 0 1 1 Result no interrupt generated an interrupt once per minute an interrupt once per second an interrupt once per second
Minute interrupt (bit MI)
The minute and second flag (bit MSF) is set to logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of bit MSF does not affect the INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and identify the source of the interrupt i.e. minute or second, countdown timer or alarm.
Table 27. 0 1 0 1 Effect of MI and SI on MSF Second interrupt (bit SI) 0 0 1 1 Result MSF never set MSF set when minutes counter increments MSF set when seconds counter increments MSF set when seconds counter increments
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Minute interrupt (bit MI)
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SPI Real time clock/calendar
The duration of both of these timers will be affected by the register Offset_register (see Section 9.11). Only when the Offset_register has the value 00h will the periods be consistent.
9.8.2 Countdown timer function
The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or 160 Hz) and enables or disables the timer.
Table 28. CTD[1:0] Bits CTD0 and CTD1 for timer frequency selection and countdown timer durations Timer source clock frequency[1] 4.096 kHz 64 Hz 1 Hz[2]
1 60
Delay Minimum timer duration n=1 244 s 15.625 ms 1s 60 s Maximum timer duration n = 255 62.256 ms 3.984 s 255 s 4 h 15 min
00 01 10 11
[1] [2]
Hz[2]
When not in use, CTD must be set to 160 Hz for power saving. Time periods can be affected by correction pulses.
Remark: Note that all timings which are generated from the 32.768 kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in deviation in timings. This is not applicable to interface timing. The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter with 0 stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter (see Figure 15).
countdown value, n
xx
03
timer source clock
countdown counter
xx
03
02
01
03
02
01
03
02
01
03
TE
TF
INT n duration of first timer period after enable may range from n - 1 to n + 1 n
001aaf906
In this example it is assumed that the timer flag is cleared before the next countdown period expires and that the pin INT is set to pulsed mode.
Fig 15. General countdown timer behavior
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If a new value of n is written before the end of the current timer period, then this value will take immediate effect. NXP does not recommend changing n without first disabling the counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock, therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the first period. The countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section 9.9.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous from the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock, see Table 29.
Table 29. 4.096 kHz 64 Hz 1 Hz
1 60
First period delay for timer counter value n Minimum timer period n n (n - 1) +
1 64
Timer source clock
Maximum timer period n+1 n+1
Hz
n + 164 Hz n + 164 Hz
Hz
(n - 1) + 164 Hz
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF may only be cleared by software. The asserted bit TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is used to control this mode selection and the interrupt output may be disabled with bit TIE, see Table 6. When reading the timer, the current countdown value is returned and not the initial value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. Timer source clock frequency selection of 1 Hz and 160 Hz will be affected by the Offset_register. The duration of a program period will vary according to when the offset is initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some 100 s periods will contain correction pulses and therefor be longer or shorter depending on the setting of the Offset_register. See Section 9.11 to understand the operation of the Offset_register.
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9.8.3 Timer flags
When a minute or second interrupt occurs, bit MSF is set to logic 1. Similarly, at the end of a timer countdown or alarm event, bit TF or AF are set to logic 1. These bits maintain their value until overwritten by software. If both countdown timer and minute or second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logical AND is performed during a write access. Writing a logic 1 will cause the flag to maintain its value, whilst writing a logic 0 will cause the flag to be reset. Three examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
Table 30. Register Control_2 Flag location in register Control_2 Bit 7 6 5 MSF 4 3 AF 2 TF 1 0 -
Table 31, Table 32 and Table 33 show what instruction must be sent to clear the appropriate flag.
Table 31. Register Control_2 Table 32. Register Control_2 Table 33. Register Control_2 Example to clear only TF (bit 2) in register Control_2 Bit 7 6 5 1 4 3 1 2 0 1 0 -
Example to clear only MSF (bit 5) in register Control_2 Bit 7 6 5 0 4 3 1 2 1 1 0 -
Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2 Bit 7 6 5 0 4 3 1 2 0 1 0 -
Clearing the alarm flag (bit AF) operates in exactly the same way, see Section 9.7.1.
9.9 Interrupt output
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits of register Control_2. Interrupts may be sourced from four places: second and minute timer, countdown timer, alarm function or offset function. With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses are always 1128 second long. Alarm interrupts always follow the condition of AF.
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SI MSF: MINUTE SECOND FLAG SET CLEAR MI to interface: read MSF 0 PULSE GENERATOR 1 TRIGGER CLEAR from interface: clear MSF TE TF: TIMER SET CLEAR PULSE GENERATOR 2 TRIGGER CLEAR from interface: clear TF AF: ALARM FLAG SET CLEAR from interface: clear AF offset circuit: add/substract 1/64 Hz pulse from interface: set CIE PULSE GENERATOR 3 TRIGGER CLEAR
001aai555
SECONDS COUNTER
SI
MI
MINUTES COUNTER
1
TI_TP to interface: read TF 0 1
INT
TIE
COUNTDOWN COUNTER
E.G.AIE 0 1 to interface: read AF AIE
set alarm flag, AF
CIE
When bits SI, MI, TIE, AIE and CIE are all disabled, pin INT will remain high-impedance.
Fig 16. Interrupt scheme
Remark: Note that the interrupts from the four sources are wired-OR, meaning they will mask one another (see Figure 16).
9.9.1 Minute and second interrupts
The pulse generator for the minute and second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 164 second in duration. If the MSF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 17. Instructions for clearing MSF are given in Section 9.8.3.
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seconds counter
58
59
MSF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf908
(1) Indicates normal duration of INT pulse (bit TI_TP = 1)
Fig 17. Example of shortening the INT pulse by clearing the MSF flag
The timing shown for clearing bit MSF in Figure 17 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, INT may be shortened by setting both MI and SI or MSF to logic 0.
9.9.2 Countdown timer interrupts
The generation of interrupts from the countdown timer is controlled via bit TIE. The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 34).
Table 34. INT operation (bit TI_TP = 1) INT period (s) n = 1[1] 4096 64 1
1 60 1 8192 1 128 1 64 1 64
Source clock (Hz)
n>1
1 1 1 1 4096 64 64 64
[1]
n = loaded countdown value. Timer stopped when n = 0.
If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing (see Figure 18). Instructions for clearing MSF can be found in Section 9.8.3.
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SPI Real time clock/calendar
countdown counter
01
n
TF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf909
(1) Indicates normal duration of INT pulse (bit TI_TP = 1).
Fig 18. Example of shortening the INT pulse by clearing the TF flag
The timing shown for clearing bit TF in Figure 18 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, INT may be shortened by setting bit TIE to logic 0.
9.9.3 Alarm interrupts
The generation of interrupts from the alarm function is controlled via bit AIE (see Table 6). If bit AIE is enabled, the INT pin follows the condition of bit AF. Clearing bit AF will immediately clear INT. No pulse generation is possible for alarm interrupts (see Figure 19).
minute counter
44
45
minute alarm
45
AF
INT
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 19. AF timing
9.9.3.1
Correction pulse interrupts Interrupt pulses generated by correction events can be shortened by writing a logic 1 to bit CIE in register Control_1.
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9.10 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output is high-impedance. The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all will be 50 : 50 except the 32.768 kHz frequencies. The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the STOP bit is set to logic 1, the CLKOUT pin will generate a continuous LOW for those frequencies that can be stopped. For more details of the STOP bit function see Section 9.13.
Table 35. 000 001 010 011 100 101 110 111
[1] [2]
CLKOUT frequency selection CLKOUT frequency (Hz) Typical duty cycle[1] 32768 16384 8192 4096 2048 1024 1[2] CLKOUT = high-Z 60 : 40 to 40 : 60 50 : 50 50 : 50 50 : 50 50 : 50 50 : 50 50 : 50 Effect of STOP bit no effect no effect no effect CLKOUT = LOW CLKOUT = LOW CLKOUT = LOW CLKOUT = LOW -
Bits COF[2:0]
Duty cycle definition: % HIGH-level time : % LOW-level time. 1 Hz clock pulses will be affected by offset correction pulses.
9.10.1 CLKOE pin
The CLKOE pin can be used to block the CLKOUT function and force the CLKOUT pin to an high-impedance state. The effect is the same as setting COF[2:0] = 111.
9.11 Offset register
The PCF2123 incorporates an offset register (address 0Dh) which can be used to implement several functions, such as:
* Ageing adjustment * Temperature compensation * Accuracy tuning
The offset is made once every two hours in the normal mode, or once every hour in the course mode. Each LSB will introduce an offset of 2.17 ppm for normal mode and 4.34 ppm for course mode. The values of 2.17 ppm and 4.34 ppm are based on a nominal 32.768 kHz clock. The offset value is coded in two's complement giving a range of +63 LSB to -64 LSB.
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Register Offset_register Offset value in decimal +63 +62 : +2 +1 0[1] -1 -2 : -63 -64 Offset value in ppm Normal mode MODE = 0 +136.71 +134.54 : +4.34 +2.17 0 -2.17 -4.34 : -136.71 -138.88 Course mode MODE = 1 +273.42 +269.08 : +8.68 +4.34 0 -4.34 -8.68 : -273.42 -277.76
Table 36.
OFFSET[6:0]
0111111 0111110 : 0000010 0000001 0000000 1111111 1111110 : 1000001 1000000
[1] Default mode.
The correction is made by adding or subtracting 64 Hz clock correction pulses, thereby changing the period of a single second.
Table 37. Example of converting the offset in ppm to seconds Seconds per Day 2.17 4.34 0.187 0.375 Week 1.31 2.62 Month 5.69 11.4 Year 68.2 136
Offset in ppm
In normal mode, the correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values has been implement. In course mode, the correction is triggered once per hour and then correction pulses are applied once per minute up to a maximum of 60 minutes. When correction values greater than 60 are used, additional correction pulses are made in the 59th minute (see Table 38).
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SPI Real time clock/calendar
Correction pulses for course mode Hour:Minute[1] 02:00 02:01 to 02:59 Correction pulses on INT per minute[2] 1 0 1 1 0 1 1 1 0 : 1 0 1 1 2 1 3 1 4 1 5
Table 38.
Correction value +1 or -1
+2 or -2
02:00 02:01 02:02 to 02:59
+3 or -3
02:00 02:01 02:02 02:03 to 02:59
: +59 or -59
: 02:00 to 02:58 02:59 02:00 to 02:59 02:00 to 02:58 02:59 02:00 to 02:58 02:59 02:00 to 02:58 02:59 02:00 to 02:58 02:59
+60 or -60 +61 or -61
+62 or -62
+63 or -63
-64
[1] [2]
Example is given in a time range from 2:00 to 2:59. Correction INT pulses are 1128 s wide. For multiple pulses they are repeated at 164 s interval.
It is possible to monitor when correction pulses are applied. The correction interrupt enable mode (bit CIE) will generate a 1128 second pulse on INT for every correction applied. In the case where multiple correction pulses are applied, a 1128 second interrupt pulse will be generated and repeated every 164 seconds. Correction is applied to the 1 Hz clock. Any timer or clock output using a frequency of 1 Hz or below will also be affected by the correction pulses.
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Effect of correction pulses Effect of correction no effect no effect no effect no effect no effect no effect effected no effect no effect effected effected
Table 39. CLKOUT 32768 16384 8192 4096 2048 1024 1
Frequency (Hz)
Time source clock 4096 64 1
1 60
9.12 External clock test mode
A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generates an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP must be cleared before the prescaler can operate again.) From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made.
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Operation example: 1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (Control_1, bit STOP = 1). 3. Clear STOP (Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments.
9.13 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until the STOP bit is released (see Figure 21 and Table 40). The STOP bit function will not affect the output of 32.768 kHz, 16.384 kHz or 8.192 kHz (see Section 9.10).
OSC STOP DETECTOR 32768 Hz 16384 Hz 8192 Hz
oscillator stop flag
4096 Hz
F0
F1
F2 RES
F13 RES
2 Hz
F14 1 Hz tick RES stop
OSC
512 Hz
CLKOUT source 8192 Hz 16384 Hz
001aai556
Fig 20. STOP bit
The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8.192 kHz cycle (see Figure 21).
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SPI Real time clock/calendar
8192 Hz
stop released 0 s to 122 s
001aaf912
Fig 21. STOP bit release timing
The first increment of the time circuits is between 0.499888 s and 0.500000 s after STOP bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset (see Table 40).
Table 40. Bit STOP 0 1 1 0 First increment of time circuits after STOP bit release Prescaler bits F0F1-F2 to F14 01-0 0001 1101 0100
[1]
1 Hz tick
Time hh:mm:ss 12:45:12 12:45:12 08:00:00 08:00:00 08:00:00 08:00:00 08:00:00 : 08:00:00 08:00:01 08:00:01 : 08:00:01 08:00:01 08:00:01 : 08:00:01 08:00:02
Comment
Clock is running normally prescaler counting normally prescaler is reset; time circuits are frozen prescaler is reset; time circuits are frozen prescaler is now running : 0 to 1 transition of F14 increments the time circuits : 0 to 1 transition of F14 increments the time circuits STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally XX-0 0000 0000 0000 New time is set by user XX-0 0000 0000 0000 STOP bit is released by user XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001 10-0 0000 0000 0001 :
1s
001aaf913
11-1 1111 1111 1111 00-0 0000 0000 0000 10-0 0000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001
[1]
F0 is clocked at 32.768 kHz.
PCF2123_1
0.499888 - 0.500000 s
XX-0 0000 0000 0000
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9.14 3-line serial interface
Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 41). The data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first (see Figure 23).
Table 41. Symbol CE Serial interface Function chip enable input Description when LOW, the interface is reset; pull-down resistor included; active input may be higher than VDD, but may not be wired permanently HIGH when CE is LOW, this input may float; input may be higher than VDD when CE is LOW, input may float; input may be higher than VDD; input data is sampled on the rising edge of SCL push-pull output; drives from VSS to VDD; output data is changed on the falling edge of SCL; will be high-Z when not driving; may be connected directly to SDI
SCL SDI
serial clock input serial data input
SDO
serial data output
SDI SDO two wire mode
SDI SDO single wire mode
001aai560
Fig 22. SDI, SDO configurations
The transmission is controlled by the active HIGH chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Data is sampled on the rising edge of the clock and transferred internally on the falling edge.
data bus
COMMAND
DATA
DATA
DATA
chip enable
001aaf914
Fig 23. Data transfer overview
The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information.
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Command byte definition Value 0 1 Description data read or data write selection write data read data subaddress; other codes will cause the device to ignore data transfer register address range
Table 42. Bit 7
Symbol R/W
6 to 4 SA 3 to 0 RA
001 0h to Fh
In Figure 24, the register Seconds is set to 45 seconds and the register Minutes is set to 10 minutes.
R/W b7 0 b6 0 b5 0 b4 1 b3 0
addr 02HEX b2 0 b1 1 b0 0 b7 0 b6 1
seconds data 45BCD b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0
minutes data 10BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 0
SCL
SDI
CE
address counter
xx
02
03
04
001aaf915
Fig 24. Serial bus write example
In Figure 25, the Months and Years registers are read. In this example, pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. Short transition periods in the order of 200 ns will not cause any problems.
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R/W b7 1 b6 0 b5 0 b4 1 b3 0
addr 07HEX b2 1 b1 1 b0 1 b7 0 b6 0
months data 11BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0
years data 06BCD b5 0 b4 0 b3 0 b2 1 b1 1 b0 0
SCL
SDI
SDO
CE
address counter
xx
07
08
09
001aaf916
Fig 25. Serial bus read example
9.14.1 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will automatically clear the interface and allow the time counting circuits to continue counting. CE must return LOW once more before a new data transfer can be executed.
tW(CE) < 1 s CE data WD timer time counters running valid sub-address data data data
WD timer running time counters frozen running
001aai563
a. Correct data transfer: read or write
1 s < tW(CE) < 2 s CE data WD timer time counters running valid sub-address data data data data transfer fail
WD timer running time counters frozen
WD trips running
001aai564
b. Incorrect data transfer; read or write Fig 26. Interface watchdog timer
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The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid subaddress.
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10. Limiting values
Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD VI VO II IO Ptot Tamb Vesd Ilu Tstg
[1] [2] [3] [4] [5]
Parameter supply voltage supply current input voltage output voltage input current output current total power dissipation ambient temperature electrostatic discharge voltage latch-up current storage temperature
Conditions
[1]
Min -0.5 -50
[1] [1]
Max +6.5 +50 +6.5 +6.5 +10 +10 300 +85 3000 300 200 +150
Unit V mA V V mA mA mW C V V mA C
-0.5 -0.5 -10 -10 -40
HBM MM
[2] [3] [4] [5]
-65
With respect to VSS. Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115 Pass level; latch-up testing, according to JESD78. According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
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11. Static characteristics
Table 44. Static characteristics VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 15 k; CL = 7 pF; unless otherwise specified. Symbol Supplies VDD supply voltage for clock data integrity; SPI-bus inactive Tamb = 25 C SPI-bus active IDD supply current SPI-bus active fSCL = 4.5 MHz; VDD = 5 V fSCL = 1.0 MHz; VDD = 3 V SPI-bus inactive; CLKOUT disabled Tamb = 25 C; VDD = 2.0 V Tamb = 25 C; VDD = 3.0 V Tamb = 25 C; VDD = 5.0 V SPI-bus inactive; CLKOUT disabled; Tamb = -40 C to +85 C VDD = 2.0 V VDD = 3.0 V VDD = 5.0 V SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = 25 C VDD = 2.0 V VDD = 3.0 V VDD = 5.0 V SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = -40 C to +85 C VDD = 2.0 V VDD = 3.0 V VDD = 5.0 V Inputs VIL VIH VI LOW-level input voltage HIGH-level input voltage input voltage on pins CE, SDI, SCL, OSCI, CLKOE, CLKOUT 0.7VDD -0.5 0.3VDD 5.5 V V V 450 550 750 nA nA nA 260 340 520 nA nA nA
[2] [2] [1]
Parameter
Conditions
Min 1.1 1.6 -
Typ 0.9 250 30
Max 5.5 5.5 400 80
Unit V V V A A
-
100 110 120
-
nA nA nA
-
-
330 350 380
nA nA nA
PCF2123_1
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SPI Real time clock/calendar
Table 44. Static characteristics ...continued VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 15 k; CL = 7 pF; unless otherwise specified. Symbol IL Parameter leakage current Conditions VI = VDD or VSS on pins SDI, SCL, OSCI, CLKOE, CLKOUT VI = VSS on pin CE Rpd Ci Outputs VO output voltage on pins CLKOUT and INT on pin OSCO on pin SDO VOH VOL HIGH-level output voltage on pin SDO LOW-level output voltage on pin SDO on pins CLKOUT and INT; VDD = 5 V; IOL=1.5 mA IOH IOL HIGH-level output current LOW-level output current VOH = 4.6 V; VDD = 5 V on pin SDO VOL = 0.4 V; VDD = 5 V on pins INT, SDO and CLKOUT VO = VDD or VSS on pins OSCO and OSCI
[5] [4]
Min -1 -1 [3]
Typ 0 0 240 -
Max +1 550 7 5.5 5.5 VDD+0.5 VDD 0.2VDD 0.4
Unit A A k pF V V V V V V
pull-down resistance input capacitance
on pin CE -
-0.5 -0.5 -0.5 0.8VDD VSS VSS
-1.5
-
1.5 -
mA mA
ILO CL(itg)
output leakage current integrated load capacitance
-1 3.3
0 7
+1 14
A pF
[1] [2] [3] [4] [5]
For reliable oscillator start at power-on: VDD = VDD(min) + 0.3 V. Timer source clock = 160 Hz, level of pins CE, SDI and SCL is VDD or VSS. Implicit by design. Refers to external pull-up voltage.
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series. C L ( itg ) = --------------------------------------------
( C OSCI C OSCO ) ( C OSCI + C OSCO )
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12. Dynamic characteristics
Table 45. SPI-bus characteristics VSS = 0 V; Tamb = -40 C to +85 C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.6 V Min Timing characteristics (see Figure 27) fclk(SCL) tSCL tclk(H) tclk(L) tr tf tsu(CE) th(CE) trec(CE) tw(CE) SCL clock frequency SCL time clock HIGH time clock LOW time rise time fall time CE set-up time CE hold time CE recovery time CE pulse width measured after valid subaddress is received set-up time for SDI data bus load = 50 pF for SCL signal for SCL signal 345 90 200 40 40 30 2.9 100 100 0.99 220 50 120 35 30 25 4.54 100 100 0.99 175 45 95 30 25 20 5.71 50 50 0.99 125 40 70 25 15 15 8.0 50 50 0.99 MHz ns ns ns ns ns ns ns ns s Max VDD = 2.4 V Min Max VDD = 3.3 V Min Max VDD = 5.0 V Min Max Unit
tsu th td(R)SDO tdis(SDO)
set-up time hold time SDO read delay time SDO disable time
10
190 70
5 10 -
108 45
3 8 -
85 40
2 5 -
60 27
ns ns ns ns
hold time for SDI data 25 no load value; bus will be held up by bus capacitance; use RC time constant with application values to avoid bus conflict 0
tt(SDI-SDO) transition time from SDI to SDO
-
0
-
0
-
0
-
ns
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SPI Real time clock/calendar
tw(CE) CE tsu(CE) tr tf SCL 20% 80% tSCL tclk(H) tclk(L) trec(CE) th(CE)
WRITE
tSU;DAT tHD;DAT R/W SA2 RA0 b7 b6 b0
SDI
SDO
Hi Z
READ
SDI
b7
b6
b0 tt(SDI-SDO) td(R)SDO tdis(SDO) b6 b0
001aai554
SDO
Hi Z
b7
Fig 27. SPI-bus timing
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13. Application information
1F supercapacitor
100 nF
VDD OSCI
CLKOE CLKOUT
INT CE SCL SDI
PCF2123
VSS
OSCO
SDO
001aai557
A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks.
Fig 28. Typical application diagram
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14. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 29. Package outline of PCF2123TS (SOT402-1)
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SPI Real time clock/calendar
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
D
B
A
terminal 1 index area
E
A A1 c
detail X
e1
1/2 e
C vMCAB wM C 8 y1 C y
e 5 L 4
b
9 e
Eh
1/2 e
e2
1
12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.75 1.45 E (1) 3.1 2.9 Eh 1.75 1.45 e 0.5 e1 1.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT758-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21
Fig 30. Package outline of PCF2123BS (SOT758-1)
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SPI Real time clock/calendar
15. Bare die outline
Wire bond die; 12 bonding pads; 1.492 x 1.449 x 0.20 mm
D
7 8 9 10 11 12 6 5 4
PCF2123U/10
A
P4 P3 E
x 0 0 y
3 2 1
P2 P1 detail X
eD DIMENSIONS (mm are the original dimensions) UNIT mm nom A 0.20 D(1) E(1) eD P1(2) 0.09
X
P2(3) 0.081
P3(2) 0.09
P4(3) 0.081 0 scale 1 mm
1.492 1.449 1.296
Notes 1. Dimension includes saw lane 2. P1 and P3: pad size 3. P2 and P4: passivation opening OUTLINE VERSION PCF2123U/10 REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-07-16 08-07-24
Fig 31. Bare die outline of PCF2123U/10 Table 46. Symbol SDO SDI SCL CLKOE CLKOUT VDD OSCI OSCO TEST INT CE VSS
[2]
Bonding pad locations Pad 1 2 3 4 5 6 7 8 9 10 11 12 Coordinates[1] x 648.0 648.0 648.0 648.0 648.0 648.0 -648.0 -648.0 -648.0 -648.0 -648.0 -648.0 693 y -575.0 -377.0 -179.0 171.2 369.2 625.7 639.0 421.9 -25.9 -223.9 -441.0 -639.0 -516.2
Alignment mark
[1] [2]
All coordinates are referenced in m to the center of the die (see Figure 31). The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
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Product data sheet
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SPI Real time clock/calendar
REF
001aai565
Fig 32. Alignment mark
PCF2123_1
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16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
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17. Packing information
214.50 mm 150 mm 73.68 mm metal frame 71.79 mm 1.2+0 mm -0.1
58 mm
plastic film X wafer 214.50 mm 193.50 mm
0.25
1.492 mm
22
5.
50
m
m
~18 m
1 1.449 mm
1
45 m Saw lane
~18 m
Y 70 m detail Y straight edge of the wafer detail X
1
1
001aai574
Fig 33. PCF2123U/10, sawn wafer on film frame carrier; 200 m thickness
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SPI Real time clock/calendar
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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SPI Real time clock/calendar
18.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 34) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 47 and 48
Table 47. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 48. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 34.
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SPI Real time clock/calendar
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 34. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
19. Abbreviations
Table 49. Acronym CMOS BCD FFC HBM LSB MM MOS MSB MSL PCB RTC SMD SPI Abbreviations Description Complementary Metal Oxide Semiconductor Binary Coded Decimal Film Frame Carrier Human Body Model Least Significant Bit Machine Model Metal Oxide Semiconductor Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Real Time Clock Surface Mount Device Serial Peripheral Interface
20. Revision history
Table 50. Revision history Release date 20081119 Data sheet status Product data sheet Change notice Supersedes (c) NXP B.V. 2008. All rights reserved.
Document ID PCF2123_1
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Product data sheet
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SPI Real time clock/calendar
21. Legal information
21.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
21.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
22. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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SPI Real time clock/calendar
23. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device protection diagram . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Low power operation. . . . . . . . . . . . . . . . . . . . . 6 Power consumption with respect to quartz series resistance . . . . . . . . . . . . . . . . . . 7 9.1.2 Power consumptions with respect to timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9.2 Register overview . . . . . . . . . . . . . . . . . . . . . . . 9 9.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . 10 9.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . 10 9.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11 9.4 OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.6 Time and date function . . . . . . . . . . . . . . . . . . 14 9.6.1 Data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.7 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 17 9.7.1 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.8 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 20 9.8.1 Minute and second interrupt . . . . . . . . . . . . . . 21 9.8.2 Countdown timer function . . . . . . . . . . . . . . . . 22 9.8.3 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.9 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 24 9.9.1 Minute and second interrupts . . . . . . . . . . . . . 25 9.9.2 Countdown timer interrupts. . . . . . . . . . . . . . . 26 9.9.3 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 27 9.9.3.1 Correction pulse interrupts . . . . . . . . . . . . . . . 27 9.10 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.10.1 CLKOE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.11 Offset register . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.12 External clock test mode. . . . . . . . . . . . . . . . . 31 9.13 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 32 9.14 3-line serial interface. . . . . . . . . . . . . . . . . . . . 34 9.14.1 Interface watchdog timer. . . . . . . . . . . . . . . . . 36 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 39 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 41 13 Application information. . . . . . . . . . . . . . . . . . 43 1 2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.1.1 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 46 48 49 50 50 50 50 51 52 52 53 53 53 53 53 53 54
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 November 2008 Document identifier: PCF2123_1

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