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STL75NH3LL
N-channel 30 V, 0.004 20 A, PowerFLATTM (6x5) , ultra low gate charge STripFETTM Power MOSFET
Features
Type STL75NH3LL VDSS 30V RDS(on) max ID
< 0.0057 20 A (1)
1. This value is according Rthj-pcb
Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Very low gate charge Low threshold device
PowerFLATTM(6x5)
Application
Switching applications
Figure 1.
Internal schematic diagram
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Table 1.
Device summary
Marking L75NH3LL Package PowerFLATTM (6 x 5) Packaging Tape and reel
Order code STL75NH3LL
June 2008
Rev 1
1/12
www.st.com 12
Contents
STL75NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5
Test circuits
.............................................. 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STL75NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC = 100 C Drain current (continuous) at TC = 25 C Drain current (continuous) at TC = 100 C Drain current (pulsed) Total dissipation at TC = 25 C Total dissipation at TC = 25 C Derating factor Value 30 16 75 47 20 12.5 80 60 4 0.03 -55 to 150 Unit V V A A A A A W W W/C C
ID (1) ID(2) ID
(2) (3)
IDM
PTOT(1) PTOT(2)
Tj Tstg
Operating junction temperature Storage temperature
1. The value is rated according Rthj-C 2. This value is according Rthj-pcb 3. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case (drain) max Thermal resistance junction-pcb max
1inch2, 2 oz Cu, t < 10 sec
Value 2.08 31.3
Unit C/W C/W
1. When mounted on FR-4 board of
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Electrical characteristics
STL75NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating,@125 C VDS = 16 V VDS = VGS, ID = 250 A VGS= 10 V, ID= 10 A VGS= 4.5 V, ID= 10 A 1 0.004 0.005 0.0057 0.0075 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions Min. Typ. 1810 565 41 18 4.8 5.3 0.5 1.5 24 Max. Unit pF pF pF nC nC nC
VDS = 25 V, f = 1 MHz, VGS=0 VDD = 15 V, ID = 20 A, VGS = 4.5 V (see Figure 14) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain
3
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STL75NH3LL
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 15 V, ID = 10 A , RG= 4.7 VGS= 10 V (see Figure 16) VDD = 15 V, ID = 10 A , RG= 4.7 VGS= 10 V (see Figure 16) Min. Typ. 8 65 30 20 Max. Unit ns ns ns ns
Table 7.
Symbol ISD ISDM VSD (1) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 20 A, VGS = 0 ISD = 20 A, di/dt = 100 A/s VDD = 20 V (see Figure 15) 22 32 1.9 Test conditions Min Typ. Max 20 80 1.3 Unit A A V ns nC A
1. Pulsed: Pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
STL75NH3LL
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
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STL75NH3LL Figure 8. Gate charge vs gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
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Test circuits
STL75NH3LL
3
Test circuits
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STL75NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL75NH3LL
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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STL75NH3LL
Revision history
5
Revision history
Table 8.
Date 12-Jun-2008
Document revision history
Revision 1 First release Changes
11/12
STL75NH3LL
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