View DS1875_4307838.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 1; 10/08
PON Triplexer and SFP Controller
General Description
The DS1875 controls and monitors all functions for burstmode transmitters, APD receivers, and video receivers. It also includes a power-supply controller for APD bias generation, and provides all SFF-8472 diagnostic and monitoring functionality. The combined solution of the DS1875 and the MAX3643 laser driver provides APC loop, modulation current control, and eye safety functionality. Ten ADC channels monitor VCC, temperature (both internal signals), and eight external monitor inputs (MON1-MON8) that can be used to meet transmitter, digital receiver, video receiver, and APD receiver-signal monitoring requirements. Four total DAC outputs are available. A PWM controller with feedback and compensation pins can be used to generate the bias for an APD or as a step-down converter. Five I/O pins allow additional monitoring and configuration.
Features
Meets All PON Burst-Timing Requirements for Burst-Mode Operation Laser Bias Controlled by APC Loop and Temperature Lookup Table (LUT) Laser Modulation Controlled by Temperature LUT Six Total DACs: Four External, Two Internal Two 8-Bit DACs, One of Which is Optionally Controlled by MON4 Voltage Internal 8-Bit DAC Controlled by a TemperatureIndexed LUT PWM Controller Boost or Buck Mode Boost Mode: Uses Optional External Components, Up to 90V Bias Generation 131kHz, 262kHz, 525kHz, or 1050kHz SelectableSwitching Frequency APD Overcurrent Protection Using Optional Fast Shutdown 10 Analog Monitor Channels: Temperature, VCC, Eight Monitors Internal, Factory-Calibrated Temperature Sensor RSSI with 29dB Electrical Dynamic Five I/O Pins for Additional Control and Monitoring Functions, Four of Which are Either Digital I/O or Analog Monitors Comprehensive Fault-Measurement System with Maskable Laser Shutdown Capability Two-Level Password Access to Protect Calibration Data 120 Bytes of Password-1 Protected Memory 128 Bytes of Password-2 Protected Memory in Main Device Address 256 Additional Bytes Located at A0h Slave Address I2C-Compatible Interface for Calibration and Monitoring 2.85V to 3.9V Operating Voltage Range -40C to +95C Operating Temperature Range 38-Pin TQFN (5mm x 7mm) Package
DS1875
Applications
BPON, GPON, or EPON Optical Triplexers SFF, SFP, and SFP+ Transceiver Modules APD Controller
Ordering Information
PART DS1875T+ DS1875T+T&R TEMP RANGE -40C to +95C -40C to +95C PIN-PACKAGE 38 TQFN-EP* 38 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Pin Configuration
COMP DAC1 MOD BMD BIAS GND
TOP VIEW
VCC
MON3N
M4DAC
MON3P
31 30 29 28 27 26 25 24 23 22 21 20 GND 32 GND 33 SW 34 VCC 35 N.C. 36 N.C. 37 N.C. 38 DS1875 19 MON4 18 MON2 17 MON1 16 MON8/D3 15 MON7/D2 14 MON6/D1
N.C. 13 MON5/D0 LOSI
FB
+
1 BEN 2 SDA 3 SCL 4 TX-F 5 N.C. 6 FETG 7 N.C. 8 TX-D 9 VCC GND
*EP 10 11 12 N.C.
TQFN (5mm x 7mm x 0.8mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PON Triplexer and SFP Controller DS1875
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics (DAC1 and M4DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Analog Input Characteristics (BMD, TXP HI, TXP LO, HBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Analog Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Timing Characteristics (Control Loop and Quick Trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Analog Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Digital Thermometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Autodetect Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Open-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Closed-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BIAS and MOD Output During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BIAS and MOD Output as a Function of Transmit Disable (TX-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 APC and Quick-Trip Shared Comparator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 MON3 Quick Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Transmit Fault (TX-F) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Safety Shutdown (FETG) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Determining Alarm Causes Using the I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2 _______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
TABLE OF CONTENTS (continued)
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Enhanced RSSI Monitoring (Dual Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Stability and Compensation Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DAC1 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 M4DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 00h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 03h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 00h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 03h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 05h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
_______________________________________________________________________________________ 3
PON Triplexer and SFP Controller DS1875
TABLE OF CONTENTS (continued)
Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
LIST OF FIGURES
Figure 1. Power-Up Timing (BEN is a Long Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 2. TX-D Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 3. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 4. M3QT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 5. ADC Timing with EN5TO8B = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 6. ADC Timing with EN5TO8B = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 7. TX-F Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 8. FETG/Output Disable Timing (Fault Condition Detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 9. SEE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 10. RSSI Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 11. PWM Controller Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 12. PWM Controller Typical APD Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 13. PWM Controller Voltage Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 14. PWM Controller Current-Sink Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 15. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 16. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LIST OF TABLES
Table 1. DS1875 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 2. Update Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 3. ADC Default Monitor Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 4. TX-F as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 5. FETG, MOD, and BIAS Outputs as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 6. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 7. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4
_______________________________________________________________________________________
PON Triplexer and SFP Controller
ABSOLUTE MAXIMUM RATINGS
Voltage Range on MON1-MON8, BEN, BMD, and TX-D Pins Relative to Ground .................................-0.5V to (VCC + 0.5V)* Voltage Range on VCC, SDA, SCL, D0-D3, and TX-F Pins Relative to Ground...............-0.5V to 6V *Subject to not exceeding +6V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DS1875
Operating Temperature Range ...........................-40C to +95C Programming Temperature Range .........................0C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +95C, unless otherwise noted.)
PARAMETER Main Supply Voltage High-Level Input Voltage (SDA, SCL, BEN) Low-Level Input Voltage (SDA, SCL, BEN) High-Level Input Voltage (TX-D, LOSI, D0, D1, D2, D3) Low-Level Input Voltage (TX-D, LOSI, D0, D1, D2, D3) SYMBOL VCC VIH:1 VIL:1 VIH:2 VIL:2 (Note 1) CONDITIONS MIN +2.85 0.7 x VCC -0.3 2.0 -0.3 TYP MAX +3.9 VCC + 0.3 0.3 x VCC VCC + 0.3 +0.8 UNITS V V V V V
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Supply Current Output Leakage (SDA, TX-F, D0, D1, D2, D3) Low-Level Output Voltage (SDA, TX-F, FETG, D0, D1, D2, D3) High-Level Output Voltage (FETG) FETG Before Recall Input Leakage Current (SCL, BEN, TX-D, LOSI) Digital Power-On Reset Analog Power-On Reset ILI:1 POD POA 1.0 2.1 SYMBOL ICC ILO VOL VOH (Notes 1, 2) (Note 2) I OL = 4mA I OL = 6mA I OH = 4mA (Note 3) VCC 0.4 10 100 1 2.2 2.75 CONDITIONS MIN TYP 5.5 MAX 10 1 0.4 0.6 UNITS mA A V V nA A V V
_______________________________________________________________________________________
5
PON Triplexer and SFP Controller DS1875
ELECTRICAL CHARACTERISTICS (DAC1 AND M4DAC)
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER DAC Output Range DAC Output Resolution DAC Output Integral Nonlinearity DAC Output Differential Nonlinearity DAC Error DAC Temperature Drift DAC Offset Maximum Load Maximum Load Capacitance TA = +25C -1 -1 -1.25 -2 -12 -500 SYMBOL CONDITIONS MIN TYP 2.5 8 +1 +1 +1.25 +2 +12 +500 250 MAX UNITS V Bits LSB LSB %FS %FS mV A pF
ANALOG INPUT CHARACTERISTICS (BMD, TXP HI, TXP LO, HBIAS)
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER BMD, TXP HI, TXP LO Full-Scale Voltage HBIAS Full-Scale Voltage BMD Input Resistance Resolution Error Integral Nonlinearity Differential Nonlinearity Temperature Drift TA = +25C (Note 6) -1 -1 -2.5 SYMBOL VAPC (Note 4) (Note 5) 35 CONDITIONS MIN TYP 2.5 1.25 50 8 2 +1 +1 +2.5 65 MAX UNITS V V k Bits %FS LSB LSB %FS
ANALOG OUTPUT CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER BIAS Current IBIAS Shutdown Current Voltage at IBIAS MOD Full-Scale Voltage MOD Output Impedance VMOD Error VMOD Integral Nonlinearity VMOD Differential Nonlinearity VMOD Temperature Drift VMOD (Note 5) (Note 7) TA = +25C (Note 8) -1.25 -1 -1 -2 SYMBOL IBIAS IBIAS:OFF 0.7 (Note 1) CONDITIONS MIN TYP 1.2 10 1.2 1.25 3 +1.25 +1 +1 +2 100 1.4 MAX UNITS mA nA V V k %FS LSB LSB %FS
6
_______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
PWM CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER PWM-DAC Full-Scale Voltage PWM-DAC Resolution VPWM-DAC Full-Scale Voltage Error VPWM-DAC Integral Nonlinearity VPWM-DAC Differential Nonlinearity VPWM-DAC Temperature Drift SW Output Impedance SW Frequency Error SW Duty Cycle Error-Amplifier Source Current Error-Amplifier Sink Current COMP High-Voltage Clamp COMP Low-Voltage Clamp Error-Amplifier Transconductance Error-Amplifier Output Impedance FB Pin Capacitance GM REA f SWER DMAX (Note 9) -5 89 90 -10 +10 2.1 0.8 425 260 5 TA = +25C -1 -1 -2 1.25 1 1 +2 20 +7 91 % % A A V V S M pF SYMBOL VPWM-DAC CONDITIONS MIN TYP 1.25 8 MAX UNITS V Bits % LSB LSB %FS
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER First BMD Sample Following BEN Remaining Updates During BEN BEN High Time BEN Low Time Output-Enable Time Following POA BIAS and MOD Turn-Off Delay BIAS and MOD Turn-On Delay FETG Turn-On Delay FETG Turn-Off Delay SYMBOL tFIRST tUPDATE tBEN:HIGH tBEN:LOW t INIT t OFF t ON tFETG:ON tFETG:OFF (Note 10) (Note 10) 400 96 10 5 5 5 5 ns ns ms s s s s CONDITIONS MIN TYP MAX UNITS
_______________________________________________________________________________________
7
PON Triplexer and SFP Controller DS1875
ANALOG VOLTAGE MONITORING
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER ADC Resolution Input/Supply Accuracy (MON1-MON8, VCC) Update Rate for Temp, MON1-MON4, and VCC Update Rate for MON5-MON8 Input/Supply Offset (MON1-MON8, VCC) MON1-MON8 Factory Setting VCC MON3 Fine Full scales are user programmable ACC tFRAME:1 tFRAME:2 VOS Bit EN5TO8B is enabled in Table 02h, Register 89h (Note 11) At factory setting SYMBOL CONDITIONS MIN TYP 13 0.25 78 156 0 2.5 6.5536 312.5 0.50 95 190 5 MAX UNITS Bits %FS ms ms LSB V V
DIGITAL THERMOMETER
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Thermometer Error SYMBOL T ERR CONDITIONS -40C to +95C MIN TYP MAX 3.0 UNITS C
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS At +85C (Note 11) At +25C (Note 11) MIN 50,000 200,000 TYP MAX UNITS
8
_______________________________________________________________________________________
PON Triplexer and SFP Controller
I2C TIMING SPECIFICATIONS
(VCC = +2.85V to +3.9V, TA = -40C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 15.)
PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time Between STOP and START Condition START Hold Time START Setup Time Data in Hold Time Data in Setup Time Capacitive Load for Each Bus Line Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals STOP Setup Time EEPROM Write Time SYMBOL f SCL tLOW tHIGH tBUF tHD:STA t SU:STA tHD:DAT t SU:DAT CB tR tF t SU:STO tW (Note 14) (Note 13) (Note 13) 20 + 0.1CB 20 + 0.1CB 0.6 20 (Note 12) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns pF ns ns s ms
DS1875
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:
All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative. Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. SW, DAC1, and M4DAC are not loaded. See the Safety Shutdown (FETG) Output section for details. Eight ranges allow the full scale to change from 625mV to 2.5V. Eight ranges allow the full scale to change from 312.5mV to 1.25V. This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register description for available full-scale ranges. The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output impedance would be approximately 1.56k. This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register description for available full-scale ranges. The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz. See the APC and Quick-Trip Shared Comparator Timing section for details. Guaranteed by design. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. CB--Total capacitance of one bus line in pF. EEPROM write begins after a STOP condition occurs.
_______________________________________________________________________________________
9
PON Triplexer and SFP Controller DS1875
Typical Operating Characteristics
(VCC = +2.85V to +3.9V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1875 toc01
SUPPLY CURRENT vs. TEMPERATURE
SDA = SCL = VCC VCC = 3.9V
DS1875 toc02
SUPPLY CURRENT vs. TEMPERATURE VCC = 3.3V, NO BIAS CURRENT
7.3 7.2 7.1 ICC (mA) 7.0 6.9 6.8 6.7 6.6 6.5 6.4 SW = 131.25kHz -40 -20 0 20 40 60 80 SW = 262.5kHz SW = 525kHz SW = 1050kHz
DS1875 toc03
9.0 8.5 SUPPLY CURRENT (mA) 8.0 7.5 7.0 6.5 6.0 5.5
SDA = SCL = VCC
9.0 8.5 SUPPLY CURRENT (mA) 8.0 7.5 7.0 6.5 6.0 5.5
7.4
+95C +25C
VCC = 2.85V
-40C 5.0 4.5 2.85 3.35 VCC (V) 3.85 5.0 4.5 -40 -20 0 20 40 60 80 TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE VCC = 5V, NO BIAS CURRENT
DS1875 toc04
DAC1 AND M4DAC DNL
DS1875 toc05
DAC1 AND M4DAC INL
0.8 DAC1 AND M4DAC INL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
DS1875 toc06
8.8 8.6 8.4 SW = 1050kHz ICC (mA) 8.2 8.0 7.8 7.6 7.4 -40 -20 0 20 40 60 80 TEMPERATURE (C) SW = 262.5kHz SW = 131.25kHz SW = 525kHz
1.0 0.8 DAC1 AND M4DAC DNL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 50 100 150 200 250 DAC1 AND M4DAC POSITION (DEC)
1.0
0
50
100
150
200
250
DAC1 AND M4DAC POSITION (DEC)
DAC1 AND M4DAC OFFSET vs. VCC
DS1875 toc07
DAC1 AND M4DAC OFFSET VARIATION vs. LOAD CURRENT
DS1875 toc08
DAC1 AND M4DAC OUTPUT vs. LOAD CURRENT
1.259 DAC1 AND M4DAC OUTPUT (V) 1.257 1.255 1.253 1.251 1.249 1.247 1.245 VCC = 3.9V VCC = 2.85V OUTPUT WITHOUT OFFSET
DS1875 toc09
0.05 0.04 DAC1 AND M4DAC OFFSET (mV) 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
TA = -40C TO +95C LOAD = -0.5mA TO +0.5mA
0.0010 0.0008 DAC1 AND M4DAC OFFSET (mV) 0.0006 0.0004 0.0002 0 -0.0002 -0.0004 -0.0006 -0.0008 -0.0010 VCC = 3.9V VCC = 3.6V VCC = 2.85V
2.85
3.05
3.25
3.45
3.65
3.85
-0.5
-0.3
-0.1
0.1
0.3
0.5
-0.5
-0.3
-0.1
0.1
0.3
0.5
VCC (V)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
10
______________________________________________________________________________________
PON Triplexer and SFP Controller
Typical Operating Characteristics (continued)
(VCC = +2.85V to +3.9V, TA = +25C, unless otherwise noted.)
DS1875
CALCULATED AND DESIRED % CHANGE IN VMOD vs. MOD RANGING
DS1875 toc10
DESIRED AND CALCULATED CHANGE IN VBMD vs. COMP RANGING
DS1875 toc11
MON1 TO MON8 INL
0.8 MON1 TO MON8 INL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V
DS1875 toc12
100 90 80 CHANGE IN VMOD (%) 70 60 50 40 30 20 10 0 000 001 002 003 004 005 006 007 MOD RANGING VALUE (DEC) CALCULATED VALUE DESIRED VALUE
100 90 80 CHANGE IN VBMD (%) 70 60 50 40 30 20 10 0 000 001 010 011 100 101 110 111 COMP RANGING (DEC) CALCULATED VALUE DESIRED VALUE
1.0
0
0.5
1.0
1.5
2.0
2.5
MON1 TO MON8 INPUT VOLTAGE (V)
MON1 TO MON8 DNL
DS1875 toc13
VBMD INL vs. APC INDEX
DS1875 toc14
VMOD INL vs. MOD INDEX
0.8 0.6 VMOD INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
DS1875 toc15
1.0 0.8 MON1 TO MON8 DNL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0
USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V
1.0 0.8 0.6 VBMD INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
0.5
1.0
1.5
2.0
2.5
0
50
100
150
200
250
0
50
100
150
200
250
MON1 TO MON8 INPUT VOLTAGE (V)
APC INDEX (DEC)
MOD INDEX (DEC)
FB VOLTAGE vs. TEMPERATURE PWM DAC = FFh
DS1875 toc16
VOUT vs. VCC VIN = 3.3V
DS1875 toc17
DUTY-CYCLE LIMIT vs. TEMPERATURE
90.75 90.50 VOUT (V) 90.25 90.00 89.75 89.50 89.25 89.00 SW FREQUENCY 525kHz 262.5kHz 131.25kHZ 1050kHz
DS1875 toc18
1.260
77.0 76.8 76.6 76.4 VOUT (V) 76.2 76.0 75.8 75.6
91.00
1.255 VOUT (V)
1.250
1.245
75.4 75.2
1.240 -40 -20 0 20 40 60 80 TEMPERATURE (C)
75.0 2.85 3.35 VCC (V) 3.85
-40
-20
0
20
40
60
80
TEMPERATURE (C)
______________________________________________________________________________________
11
PON Triplexer and SFP Controller DS1875
Typical Operating Characteristics (continued)
(VCC = +2.85V to +3.9V, TA = +25C, unless otherwise noted.)
PWM DAC DNL
DS1875 toc19
PWM DAC INL
DS1875 toc20
M3QT DAC DNL
0.75 0.50 DAC DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
DS1875 toc21
1.00 0.75 0.50 DAC DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 32 64 96
1.00 0.75 0.50 DAC INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
1.00
128 160 192 224 256
0
32
64
96
128 160 192 224 256
0
32
64
96
128 160 192 224 256
DAC SETTING (DEC)
DAC SETTING (DEC)
DAC SETTING (DEC)
M3QT DAC INL
DS1875 toc22
SW CURRENT INTO BSS123 FET FREQUENCY = 1050kHz 50% DUTY CYCLE
DS1875 toc23
1.00 0.75 0.50 DAC INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 32 64 96
1V/div 0V
SW
10mA/div 0mA
SW CURRENT
128 160 192 224 256
100ns/div
DAC SETTING (dec)
PWM DAC CHANGING FROM 00h TO 80h RCOMP = 24.3k, CCOMP = 220nF
DS1875 toc24
SWITCHING WAVEFORMS VIN = 3.3V, VOUT ~ 90V, IOUT ~ 1.25mA, C2 = 0.1F
DS1875 toc25
20V/div 0V 200mV/div 0V
VOUT FB
5V/div 0V 50V/div 0V
INDUCTOR VOLTAGE
SW
COMP 100mA/div 200mV/div DUTY CYCLE 0V 5ms/div 10%/div 0% 0mA 100mV/div 0V
INDUCTOR CURRENT
VOUT RIPPLE (AC-COUPLED)
2s/div
12
______________________________________________________________________________________
PON Triplexer and SFP Controller
Pin Description
PIN 1 2 3 4 5, 7, 11, 20, 36, 37, 38 6 8 9, 31, 35 10, 24, 32, 33 12 NAME BEN SDA SCL TX-F N.C. FETG TX-D VCC GND LOSI I2C Serial-Data Input/Output I2C Serial-Clock Input Transmit-Fault Output No Connection FET Gate Output. Signals an external n-channel or p-channel MOSFET to enable/disable the laser's current. Transmit-Disable Input. Disables analog outputs. Power-Supply Input (2.85V to 3.9V) Ground Connection Loss-of-Signal Input. Open-collector buffer for external loss-of-signal input. This input is accessible in the status register through the I2C interface. External Monitor Input 5 or Digital I/O 0. This signal is the open-collector output driver for IN. It can also be controlled by the MUX0 and OUT0 bits. The voltage level of this pin can be read at IN0. In analog input mode, the voltage at this pin is digitized by the internal 13-bit analog-todigital converter and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the processor based on the ADC result. External Monitor Inputs 6, 7, and 8 or Digital I/O 1, 2, and 3. In digital mode, these open-collector outputs are controlled by the OUTx bits, and their voltage levels can be read at the INx bits. In analog input mode, the voltages at these pins are digitized by the internal 13-bit analog-to-digital converter and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the processor based on the ADC result. D2 is configurable as a quick-trip output for MON3. External Monitor Input 1, 2, and 4. The voltage at these pins is digitized by the internal 13-bit analog-to-digital converter and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the processor based on the ADC result. External Monitor Input 3. This is a differential input that is digitized by the internal 13-bit ADC and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the processor based on the ADC result. When used as a single-ended input, connect MON3N to ground. 8-Bit DAC Output. Driven either by I2C interface or temperature-indexed LUT. 8-Bit DAC Output for Generating Analog Voltage. Can be controlled by a LUT indexed by the voltage applied to MON4. Converter Feedback. Input to error amplifier. The other input to the error amplifier is an 8-bit DAC. The DAC can be driven by a temperature-indexed LUT. The output of the error amplifier is the input of the comparator used to create the PWM signal. Bias-Current Output. This 13-bit current output generates the bias current reference for the MAX3643. Modulation Output Voltage. This 8-bit voltage output has eight full-scale ranges from 1.25V to 0.3125V. This pin is connected to the MAX3643's VMSET input to control the modulation current. Compensation for Error Amplifier in PWM Controller Back Monitor Diode Input (Feedback Voltage, Transmit Power Monitor) PWM Output. This is typically the switching node of a PWM converter. In conjunction with FB, a boost converter, buck converter, or analog 8-bit output can be created. Exposed Pad FUNCTION Burst-Enable Input. Triggers the samples for the APC and quick-trip monitors.
DS1875
13
MON5/D0
14, 15, 16
MON6/D1, MON7/D2, MON8/D3 MON1, MON2, MON4 MON3N, MON3P DAC1 M4DAC
17, 18, 19
21, 22
23 25
26 27 28 29 30 34 --
FB BIAS MOD COMP BMD SW EP
______________________________________________________________________________________
13
PON Triplexer and SFP Controller DS1875
Block Diagram
VCC VCC SDA SCL DS1865 MEMORY ORGANIZATION MAIN MEMORY EEPROM/SRAM ADC CONFIGURATION/RESULTS TABLE 00h (EEPROM) SYSTEM STATUS BITS ADDITIONAL MONITORS ALARM/WARNING COMPARISONS TABLE 01h (EEPROM) USER MEMORY, ALARM TRAP EEPROM 256 BYTES AT A0h SLAVE ADDRESS VCC TABLE 02h (EEPROM) CONFIGURATION AND CALIBRATION TABLE 03h (EEPROM) USER MEMORY TABLE 04h (EEPROM) MODULATION LUT TABLE 05h (EEPROM) ADC TE LUT TABLE 06h (EEPROM) M4DAC LUT TABLE 07h (EEPROM) PWM LUT TABLE 08h (EEPROM) BIAS OL LUT
I2C INTERFACE
SRAM RESET
POWER-ON ANALOG VCC > VPOA NONMASKABLE INTERRUPT TX-F
MON1 MON2 ANALOG MUX MON3N INTERRUPT MASK INTERRUPT LATCH
MON3P MON4 MON[5:8] TEMP SENSOR
13-BIT ADC
DIGITAL LIMIT COMPARATOR FOR ADC RESULTS
LATCH ENABLE
INTERRUPT MASK
INTERRUPT LATCH
FETG
BEN
SAMPLE CONTROL MUX
BIAS MAX QUICK TRIP
TABLE 08h BIAS OL LUT TEMP INDEXED
BMD HBIAS QUICK-TRIP LIMIT HTXP QUICK-TRIP LIMIT LTXP QUICK-TRIP LIMIT APC SET POINT FROM TRACKING-ERROR TABLE TX-D MON5/D0 MON5 0 1 TTL LOS STATUS/ D0 IN D0 OUT INV0 TABLE 07h PWM VOLTAGE LUT CAN BE INDEXED BY TEMP SENSOR MUX 8-BIT DAC WITH SCALING MUX DIGITAL APC INTEGRATOR MUX 13-BIT DAC BIAS
TX-D INPUT MOD LUT
8-BIT DAC WITH SCALING
MOD
8-BIT PWM-DAC PWM SW
TTL
LOSI MUX0 MON6/D1 MON6 TTL D1 IN D1 OUT I2C CONTROL COMP FB
MON7/D2 MON7 0 1
TTL
D2 IN D2 OUT INV M3QT M3QT MUX2 D3 IN D3 OUT
TABLE 06h M4DAC LUT INDEXED BY MON4
M4DAC 8-BIT, 2.5V FULL SCALE
M4DAC
TTL
I2C CONTROL
MON8/D3 MON8 GND
TTL
DAC1 8-BIT, 2.5V FULL SCALE
DAC1
DS1875
14
______________________________________________________________________________________
PON Triplexer and SFP Controller
Typical Operating Circuit
3.3V
DS1875
IN+ INBEN+ BENDIS MAX3643
VCC OUT+ OUTBIAS-
BIAS+ MODSET BIASSET BENOUT BCMON VMSET VBSET IMAX
VREF
GND
MAX4003 12V RF DETECTOR
MOD I2C COMMUNICATION FAULT OUTPUT DISABLE INPUT RECEIVER LOS OPEN-DRAIN LOS OUTPUT SDA SCL TX-F TX-D LOSI D0
BIAS BEN BMD MON1 MON2 MON3 MON4 FETG M4DAC GAIN CONTROL CATV SHUTDOWN CONTROL 3.3V TRANSMIT POWER RECEIVE POWER CATV RF POWER MAX3654 FTTH CATV TIA CATV
ADDITIONAL DIGITAL I/O
D3
D1
VCC DS1875 SW GND ADDITIONAL MONITORS MON[5:7] FB DAC1 VOLTAGE REFERENCE MAX4007 CURRENT MONITOR RECEIVE POWER (CURRENT) RAGC 3.3V
D2
APD OVERLOAD QUICK TRIP
MON8 COMP
APD VOLTAGE MONITOR APD OPTIONAL
ROSA
TIA
______________________________________________________________________________________
15
PON Triplexer and SFP Controller DS1875
Detailed Description
The DS1875 integrates the control and monitoring functionality required to implement a PON system using Maxim's MAX3643 compact burst-mode laser driver. The compact laser-driver solution offers a considerable cost benefit by integrating control and monitoring features in the low-power CMOS process, while leaving only the high-speed portions to the laser driver. Key components of the DS1875 are shown in the Block Diagram and described in subsequent sections. Table 1 contains a list of acronyms used in this data sheet.
Bias Control
Bias current is controlled by an APC loop. The APC loop uses digital techniques to overcome the difficulties associated with controlling burst-mode systems.
Table 1. DS1875 Acronyms
ACRONYM 10GEPON ADC AGC APC APD BM BPON CATV EPON ER DAC FTTH FTTX GEPON GPON LOS LUT TE TIA ROSA RSSI PON PWM SFF SFF-8472 SFP SFP+ TOSA DEFINITION 10-Gigabit Ethernet PON Analog-to-Digital Converter Automatic Gain Control Automatic Power Control Avalanche Photodiode Burst Mode Broadband PON Cable Television Ethernet PON Extinction Ratio Digital-to-Analog Converter Fiber-to-the-Home Fiber-to-the-X Gigabit Ethernet PON Gigabit PON Loss of Signal Lookup Table Tracking Error Transimpedance Amplifier Receiver Optical Subassembly Receive Signal Strength Indicator Passive Optical Network Pulse-Width Modulation Small Form Factor Document Defining Register Map of SFPs and SFFs Small Form Factor Pluggable Enhanced SFP Transmit Optical Subassembly
Autodetect Bias Control This is the default mode of operation. In autodetect bias control, transmit burst length is monitored. A "short burst" is declared when the burst is shorter than expected based on the sample rate setting in Table 02h, Register 88h. In the case that 32 consecutive short bursts are transmitted, the integrator is disabled and the BIAS DAC is loaded from the BIAS LUT (Table 08h). Any single burst of adequate burst length re-enables the APC integrator. Open-Loop Bias Control Open-loop control is configured by setting FBOL in Table 02h, Register C7h. In this mode, the BIAS LUT (Table 08h) is directly loaded to the BIAS DAC output. The BIAS LUT can be programmed in 2C increments over the 40C to +102C range. It is left-shifted so that the LUT value is loaded to either the DAC MSB or the DAC MSB-1 (Bit BOLFS, Table 02h, Register 89h). Closed-Loop Bias Control The closed-loop control requires a burst length long enough to satisfy the sample rate settings in Table 02h, Register 88h (APC_SR[3:0]). Closed-loop control is configured by setting FBCL in Table 02h, Register C7h. In this mode, the APC integrator is enabled, which controls the BIAS DAC. The APC loop begins by loading the value from the BIAS LUT (Table 08h) indexed by the present temperature conversion. The feedback for the APC loop is the monitor diode (BMD) current, which is converted to a voltage using an external resistor. The feedback voltage is compared to an 8-bit scaleable voltage reference, which determines the APC set point of the system. Scaling of the reference voltage accommodates the wide range in photodiode sensitivities. This allows the application to take full advantage of the APC reference's resolution. The DS1875 has an LUT to allow the APC set point to change as a function of temperature to compensate for TE. The TE LUT (Table 05h) has 36 entries that determine the APC setting in 4C windows between -40C to +100C. Ranging of the APC DAC is possible by programming a single byte in Table 02h, Register 8Dh.
16
______________________________________________________________________________________
PON Triplexer and SFP Controller
DC Operation When using autodetect mode or closed-loop mode, BEN should be equal to VCC or long burst. In open-loop mode, BEN should be ground or any burst length.
BIAS and MOD Output During Power-Up
On power-up the modulation and bias outputs remain off until VCC is above VPOA, a temperature conversion has been completed, and, if the VCC ADC alarm is enabled, a VCC conversion above the customer-defined VCC low alarm level must clear the VCC low alarm (tINIT). Once all these conditions (tINIT) are satisfied, the MOD output is enabled with the value determined by the temperature conversion and the modulation LUT (Table 04h). When the MOD output is enabled, the BIAS output is turned on to a value equal to the temperature-indexed value in the BIAS LUT (Table 08h). Next, the APC integrator is enabled, and single LSB steps are taken to tightly control the average power. If a fault is detected and TX-D is toggled to re-enable the outputs, the DS1875 powers up following a similar sequence to an initial power-up. The only difference is that the DS1875 already determined the present temperature, so the t INIT time is not required for the DS1875 to recall the APC and MOD set points from EEPROM.
DS1875
Modulation Control
The MOD output is an 8-bit scaleable voltage output that interfaces with the MAX3643's VMSET input. An external resistor to ground from the MAX3643's MODSET pin sets the maximum current that the voltage at the VMSET input can produce for a given output range. This resistor value should be chosen to produce the maximum modulation current the laser type requires over temperature. Then the MOD output's scaling is used to calibrate the full-scale (FS) modulation output to a particular laser's requirements. This allows the application to take full advantage of the MOD output's resolution. The modulation LUT can be programmed in 2C increments over the -40C to +102C range. Ranging of the MOD DAC is possible by programming a single byte in Table 02h, Register 8Bh.
VCC
VPOA tINIT
VMOD
BIAS LUT VALUE APC INTEGRATOR ON IBIAS
BIAS SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. Power-Up Timing (BEN is a Long Burst)
______________________________________________________________________________________
17
PON Triplexer and SFP Controller DS1875
BIAS and MOD Output as a Function of Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal operation, the outputs are disabled within tOFF. When TX-D is deasserted (logic 0), the DS1875 turns on the MOD output with the value associated with the present temperature and initializes the BIAS using the same search algorithm used at startup. When asserted, the SOFT TX-D bit (Lower Memory, Register 6Eh) offers a software control identical to the TX-D pin (see Figure 2). The DS1875 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options suitable for burst-mode transmitters. The rising edge of BEN triggers the sample to occur, and the Update Rate register (Table 02h, Register 88h) determines the sampling time. The first sample occurs (tFIRST) after the rising edge of BEN. The internal clock is asynchronous to BEN, causing a 50ns uncertainty regarding when the first sample will occur following BEN. After the first sample occurs, subsequent samples occur on a regular interval, tREP. Table 2 shows the sample rate options available. Updates to the TXP HI and TXP LO quick-trip alarms do not occur during the BEN low time. The BIAS HI quick trip can be sampled during the burst-low time. Any
TX-D IBIAS VMOD tOFF tOFF tON tON
Table 2. Update Rate Timing
APC_SR[3:0] MINIMUM TIME FROM BEN TO FIRST SAMPLE (tFIRST) 50ns (ns) 350 550 750 950 1350 1550 1750 2150 2950 3150 REPEATED SAMPLE PERIOD FOLLOWING FIRST SAMPLE (tREP) (ns) 800 1200 1600 2000 2800 3200 3600 4400 6000 6400
Figure 2. TX-D Timing
APC and Quick-Trip Shared Comparator Timing
As shown in Figure 3, the DS1875's input comparator is shared between the APC control loop and the three quick-trip alarms (TXP HI, TXP LO, and BIAS HI). The comparator polls the alarms in a multiplexed sequence. Six of every eight comparator readings are used for APC loop-bias current control. The other two updates are used to check the HTXP/LTXP (monitor diode voltage) and the HBIAS (MON1) signals against the internal APC and BIAS reference. If the last APC comparison was higher than the APC set point, it makes an HTXP comparison, and if it is lower, it makes an LTXP comparison. Depending on the results of the comparison, the corresponding alarms and warnings (TXP HI, TXP LO) are asserted or deasserted.
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b*
*All codes greater than 1001b (1010b to 1111b) use the maximum sample time of code 1001b.
BEN
tFIRST tREP APC QUICK-TRIP SAMPLE TIMES APC SAMPLE APC SAMPLE APC SAMPLE APC SAMPLE APC SAMPLE APC SAMPLE HTXP/LTXP SAMPLE HBIAS SAMPLE APC SAMPLE
Figure 3. APC Loop and Quick-Trip Sample Timing
18
______________________________________________________________________________________
PON Triplexer and SFP Controller
quick-trip alarm that is detected by default remains active until a subsequent comparator sample shows the condition no longer exists. A second bias-current monitor (BIAS MAX) compares the DS1875's BIAS DAC's code to a digital value stored in the MAX BIAS register. This comparison is made at every bias-current update to ensure that a high bias current is quickly detected. tion. The BIAS MAX quick trip is a digital comparison that determines if the BIAS DAC indicates that the bias current is above specification. IBIAS is not allowed to exceed the value set in the MAX BIAS register. When the DS1875 detects that the bias is at the limit, it sets the BIAS MAX status bit and clamps the bias current at the MAX BIAS level. In the closed-loop mode, if the recalled value from the BIAS LUT is greater than MAX BIAS then, the update is not done and IBIAS reverts to the previous IBIAS value. The quick trips are routed to the TX-F and FETG outputs through interrupt masks to allow combinations of these alarms to be used to trigger these outputs. When FETG is triggered, the DS1875 also disables the MOD and BIAS outputs. See the BIAS and MOD Output During Power-Up section for details.
DS1875
Monitors and Fault Detection
Monitors Monitoring functions on the DS1875 include a power-on analog (POA) VCC comparison, five quick-trip comparators, and ADC channels. This monitoring combined with the interrupt masks determine if the DS1875 shuts down its outputs and triggers the TX-F and FETG outputs. All the monitoring levels and interrupt masks are user programmable with the exception of POA, which trips at a fixed range and is nonmaskable for safety reasons. Power-On Analog (POA) POA holds the DS1875 in reset until VCC is at a suitable level (VCC > VPOA) for the part to accurately measure with its ADC and compare analog signals with its quicktrip monitors. Because VCC cannot be measured by the ADC when VCC is less than VPOA, POA also asserts the VCC low alarm, which is cleared by a VCC ADC conversion greater than the customer-programmable VCC low ADC limit. This allows a programmable limit to ensure that the head room requirements of the transceiver are satisfied during slow power-up. The TX-F and FETG outputs do not latch until there is a conversion above the VCC low limit. The POA alarm is nonmaskable. The TX-F and FETG outputs are asserted when V CC is below VPOA. See the Low-Voltage Operation section for more information. Five Quick-Trip Monitors and Alarms Five quick-trip monitors are provided to detect potential laser safety issues. These monitor: 1) High Bias Current (HBIAS)
2) Low Transmit Power (LTXP) 3) High Transmit Power (HTXP) 4) Max Output Current (BIAS MAX) 5) MON3 Quick Trip (M3QT) The high- and low-transmit power quick-trip registers (HTXP and LTXP) set the thresholds used to compare against the BMD voltage to determine if the transmit power is within specification. The HBIAS quick trip compares the MON1 input (generally from the MAX3643 bias monitor output) against its threshold setting to determine if the present bias current is above specifica-
MON3 Quick Trip One additional quick trip is used to protect the APD from overcurrent. MON3P is used to monitor the current through the APD. When MON3P exceeds a threshold set by the M3QT DAC register (Table 02h, Register C3h), the PWM is shut down by blocking SW pulses. The MON3 comparison is single-ended referenced to ground. In the case where MON3 is used differentially and not referenced to ground, this must be considered when setting the MON3 quick-trip threshold. Additionally, the D2 pin can be driven either high or low as determined by INV M3QT and MUX M3QT bits in Lower Memory, Register 79h. An external switch controlled by pin D2 may be used to clamp the converter's output when MON3 quick trip occurs. This external switch discharges the output voltage much faster than allowing the load to discharge the rail. The MON3 quick-trip alarm can be latched by enabling M3QT LEN in Table 02h, Register 89h. The latch is reset by setting M3QT RESET in Lower Memory, Register 78h. A soft quick trip is performed by setting SOFT M3QT in Lower Memory, Register 78h (see Figure 4). ADC Monitors and Alarms The ADC monitors six channels that measure temperature (internal temp sensor), VCC, and MON1-MON4 using an analog multiplexer to measure them round robin with a single ADC. Each channel has a customerprogrammable full-scale range and offset value that is factory programmed to default value (see Table 3). Additionally, MON1-MON4 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2n their specified range to measure small signals. The DS1875 can then right-shift the results by n bits to maintain the bit weight of their specification.
19
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
TRIP CONDITION
mCLK (525kHz)
CAPTURE ALARM
M3QT ALARM (UNLATCHED)
Figure 4. M3QT Timing
ONE ADC CYCLE MON4 TEMP VCC MON1 MON2 MON3 MON4 TEMP
tFRAME1
Figure 5. ADC Timing with EN5TO8B = 0
TEMP
VCC
MON1
MON2
MON3
MON4
MON5
MON6
TEMP
VCC
MON1
MON2
MON3
MON4
MON7
MON8
tFRAME2
tFRAME2
Figure 6. ADC Timing with EN5TO8B = 1
The ADC results (after right-shifting, if used) are compared to high and low alarm and warning thresholds after each conversion. The alarm values can be used to trigger the TX-F or FETG outputs. These ADC thresholds are user programmable through the I2C interface, as well as masking registers that can be used to prevent the alarms from triggering the TX-F and FETG outputs.
Table 3. ADC Default Monitor Ranges
SIGNAL Temperature (C) VCC (V) MON1-MON8 (V) +FS SIGNAL 127.996 6.5528 2.4997 +FS HEX 7FFF FFF8 FFF8 -FS SIGNAL -128 0 0 -FS HEX 8000 0000 0000
ADC Timing There are 10 analog channels that are digitized in a sequential fashion. The MON5-MON8 channels are sampled depending on the state of the EN5TO8B bit in Table 02h, Register 89h. If the bit is programmed to logic 0, the ADC cycles through temperature, VCC, and MON1-MON4 (Figure 5). If the bit is programmed to logic 1, all 10 channels are digitized, including channels MON5-MON8 (Figure 6). In this mode (EN5TO8B = 0), each of MON5-MON8 is sampled on alternate cycles, as shown in Figure 5. The total time required to convert one set of channels is the sequential ADC cycle time, tFRAME1 or tFRAME2 (see Figure 6).
20
______________________________________________________________________________________
PON Triplexer and SFP Controller
Right-Shifting ADC Result If the weighting of the ADC digital reading must conform to a predetermined full-scale value defined by a standard's specification, then right-shifting can be used to adjust the predetermined full-scale analog measurement range while maintaining the weighting of the ADC results. The DS1875's range is wide enough to cover all requirements; when the maximum input value is 1/2 the FS value, right-shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8th the specified predetermined full-scale value, so only 1/8th the converter's range is used. An alternative is to calibrate the ADC's full-scale range to 1/8th the readable predetermined full-scale value and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard's specification (i.e., SFF-8472). The right-shift operation on the ADC result is carried out based on the contents of RIGHT SHIFT1/0 registers (Table 02h, Registers 8Eh-8Fh). Four analog channels, MON1-MON4, have 3 bits each allocated to set the number of right-shifts. Up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (Table 01h, Registers
62h-6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions.
DS1875
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the ADC alarms and the QT alarms to select which comparisons cause it to assert. In addition, the FETG alarm is selectable through the TX-F mask to cause TX-F to assert. All alarms, with the exception of FETG, only cause TX-F to remain active while the alarm condition persists. However, the TX-F latch bit can enable the TX-F output to remain active until it is cleared by the TX-F reset bit, TX-D, SOFT TX-D, or by power cycling the part. If the FETG output is configured to trigger TX-F, it indicates that the DS1875 is in shutdown and requires TX-D, SOFT TX-D, or cycling power to reset. Only enabled alarms activate TX-F (see Figure 7). Table 4 shows TX-F as a function of TX-D and the alarm sources.
Table 4. TX-F as a Function of TX-D and Alarm Sources
VCC > VPOA No Yes Yes Yes TX-D X 0 0 1 NONMASKED TX-F ALARM X 0 1 X TX-F 1 0 1 0
TX-F LATCHED OPERATION DETECTION OF TX-F FAULT
TX-D OR TX-F RESET TX-F
TX-F NONLATCHED OPERATION DETECTION OF TX-F FAULT
TX-F
Figure 7. TX-F Timing
______________________________________________________________________________________
21
PON Triplexer and SFP Controller DS1875
DETECTION OF FETG FAULT
TX-D
IBIAS
tOFF
tON
VMOD
tOFF
tON
FETG* *FETG DIR = 0
tFETG:ON
tFETG:OFF
Figure 8. FETG/Output Disable Timing (Fault Condition Detected)
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from TX-F) for the ADC alarms and the QT alarms to select which comparisons cause it to assert. Unlike TX-F, the FETG output is always latched. Its output polarity is programmable to allow an external nMOS or pMOS to open during alarms to shut off the laser-diode current. If the FETG output triggers, indicating that the DS1875 is in shutdown, it requires TX-D, SOFT TX-D, or cycling power to be reset. Under all conditions, when the analog outputs are reinitialized after being disabled, all the alarms with the exception of the VCC low ADC alarm are cleared. The VCC low alarm must remain active to prevent the output from attempting to operate when inadequate VCC exists to operate the laser driver. Once adequate VCC is present to clear the VCC low alarm, the outputs are enabled following the same sequence as the power-up sequence. As previously mentioned, the FETG is an output used to disable the laser current through a series nMOS or pMOS. This requires that the FETG output can sink or source current. Because the DS1875 does not know if it should sink or source current before V CC exceeds VPOA, which triggers the EE recall, this output is high impedance when VCC is below VPOA (see the LowVoltage Operation section for details and diagram). The application circuit should use a pullup or pulldown resistor on this pin that pulls FETG to the alarm/shutdown state (high for a pMOS, low for a nMOS). Once VCC is above VPOA, the DS1875 pulls the FETG output to the state determined by the FETG DIR bit (Table 02h,
22
Register 89h). Set FETG DIR to 0 if an nMOS is used and 1 if a pMOS is used.
Table 5. FETG, MOD, and BIAS Outputs as a Function of TX-D and Alarm Sources
VCC > VPOA Yes Yes Yes TX-D NONMASKED FETG ALARM 0 1 X FETG FETG DIR FETG DIR FETG DIR MOD AND BIAS OUTPUTS Enabled Disabled Disabled
0 0 1
Determining Alarm Causes Using the I2C Interface
To determine the cause of the TX-F or FETG alarm, the system processor can read the DS1875's alarm trap bytes (ATB) through the I2C interface (Table 01h, Registers F8h-FBh). The ATB has a bit for each alarm. Any time an alarm occurs, regardless of the mask bit's state, the DS1875 sets the corresponding bit in the ATB. Active ATB bits remain set until written to 0s through the I2C interface. On power-up, the ATB is 0s until alarms dictate otherwise. FETG causes additional alarms that make it difficult to determine the root cause of the problem. Therefore, no updates are made to the ATB when FETG occurs.
______________________________________________________________________________________
PON Triplexer and SFP Controller
Die Identification
The DS1875 has an ID hard-coded to its die. Two registers (Table 02h, Registers 86h-87h) are assigned for this feature. Byte 86h reads 75h to identify the part as the DS1875; byte 87h reads the die revision. Any time VCC is above VPOD, the I2C interface can be used to determine if VCC is below the VPOA level. This is accomplished by checking the RDYB bit in the status (Lower Memory, Register 6Eh) byte. RDYB is set when V CC is below V POA . When V CC rises above V POA , RDYB is timed (within 500s) to go to 0, at which point the part is fully functional. For all device addresses sourced from EEPROM (Table 02h, Register 8Ch), the default device address is A2h until VCC exceeds VPOA, allowing the device address to be recalled from the EEPROM.
DS1875
Low-Voltage Operation
The DS1875 contains two power-on reset (POR) levels. The lower level is a digital POR (VPOD) and the higher level is an analog POR (VPOA). At startup, before the supply voltage rises above VPOA, the outputs are disabled (FETG and BIAS outputs are high impedance, MOD is low), all SRAM locations are low (including shadowed EEPROM (SEE)), and all analog circuitry is disabled. When V CC reaches V POA , the SEE is recalled, and the analog circuitry is enabled. While VCC remains above VPOA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below VPOA but is still above VPOD, the SRAM retains the SEE settings from the first SEE recall, but the device analog is shut down and the outputs are disabled. FETG is driven to its alarm state defined by the FETG DIR bit (Table 02h, Register 89h). If the supply voltage recovers back above VPOA, the device immediately resumes normal functioning. When the supply voltage falls below VPOD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings. The EEPROM recall occurs the next time VCC exceeds VPOA. Figure 9 shows the sequence of events as the voltage varies.
Enhanced RSSI Monitoring (Dual Range Functionality)
The DS1875 offers a new feature to improve the accuracy and range of MON3, which is most commonly used for monitoring RSSI. This feature enables rightshifting (along with its gain and offset settings) when the input signal is below a set threshold (within the range that benefits using right-shifting) and then automatically disables right-shifting (recalling different gain and offset settings) when the input signal exceeds the threshold. Also, to prevent "chattering," hysteresis prevents excessive switching between modes in addition to ensuring that continuity is maintained. Dual range operation is enabled by default (factory programmed in EEPROM). However, it can easily be disabled through the RSSI_FF and RSSI_FC bits. When dual range operation is disabled, MON3 operates identically to the other MON channels, although featuring a differential input.
SEE RECALL VPOA
SEE RECALL
VCC
VPOD
FETG
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN TO FETG DIR
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN TO FETG DIR
NORMAL OPERATION
DRIVEN TO FETG DIR
HIGH IMPEDANCE
SEE
PRECHARGED TO 0
RECALLED VALUE
PRECHARGED TO 0
RECALLED VALUE
PRECHARGED TO 0
Figure 9. SEE Timing
______________________________________________________________________________________
23
PON Triplexer and SFP Controller
MON3 TIMESLICE
PERFORM FINEMODE CONVERSION
DID PRIOR MON3 TIMESLICE RESULT IN A COARSE CONVERSION? (LAST RSSI = 1?)
Y
N
N
WAS CURRENT FINEMODE CONVERSION 93.75% OF FS?
DID CURRENT FINEMODE CONVERSION REACH MAX?
Y
Y PERFORM COARSEMODE CONVERSION
N LAST RSSI = 0 LAST RSSI = 1
REPORT FINE CONVERSION RESULT
REPORT COARSE CONVERSION RESULT
END OF MON3 TIMESLICE
Figure 10. RSSI Flowchart
Dual-range functionality consists of two modes of operation: fine mode and coarse mode. Each mode is calibrated for a unique transfer function, hence the term, dual range. Table 6 highlights the registers related to MON3. Fine mode is equivalent to the other MON channels. Fine mode is calibrated using the gain, offset, and right-shifting registers at locations shown in Table 6 and is ideal for relatively small analog input voltages. Coarse mode is automatically switched to when the input exceeds the threshold (to be discussed in a subsequent paragraph). Coarse mode is calibrated using different gain and offset registers, but lacks right-shifting (since coarse mode is only used on large input signals). The gain and offset registers for coarse mode are also shown in Table 6. With the use of right-shifting, the fine mode full scale is programmed to (1/2N)th the coarse mode full scale. The DS1875 will now autorange to choose the range that gives the best resolution for the measurement. To eliminate chatter, 6.25% of hysteresis is applied when the input resides at the boundary of the two ranges. See Figure 10. Additional information for each of the registers can be found in the Memory Map section. Dual range operation is transparent to the end user. The results of MON3 analog-to-digital conversions are still stored/reported in the same memory locations (68-69h, Lower Memory) regardless of whether the conversion was performed in fine mode or coarse mode. When the DS1875 is powered up, analog-to-digital conversions begin in a round-robin fashion. Every MON3 timeslice begins with a fine mode analog-to-digital conversion (using fine mode's gain, offset, and right-shifting settings). See the flowchart in Figure 10. Then, depending on whether the last MON3 timeslice resulted in a coarse-mode conversion and also depending on the value of the current fine conversion, decisions are made whether to use the current fine-mode conversion result or to make an additional conversion (within the same MON3 timeslice), using coarse mode (using coarse mode's gain and offset settings, and no rightshifting) and reporting the coarse-mode result. The flowchart also illustrates how hysteresis is implemented. The fine-mode conversion is compared to one of
DS1875
Table 6. MON3 Configuration Registers
REGISTER MON3 FINE SCALE MON3 FINE OFFSET RIGHT SHIFT0/1 CONFIG (RSSI_FC, RSSI_FF bits) MON3 VALUE FINE MODE 98h-99h, Table 02h A8h-A9h, Table 02h 8Eh-8Fh, Table 02h 89h, Table 02h 68h-69h, Lower Memory COARSE MODE 9Ch-9Dh, Table 02h ACh-ADh, Table 02h --
24
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 7. MON3 Hysteresis Threshold Values
NO. OF RIGHTSHIFTS 0 1 2 3 4 5 6 7 FINE MODE (MAX) FFF8h 7FFCh 3FFEh 1FFFh 0FFFh 07FFh 03FFh 01FFh COARSE MODE (MIN*) F000h 7800h 3C00h 1E00h 0F00h 0780h 03C0h 01E0h
and RSSI_FF to 1. These bits are also useful when calibrating MON3. For additional information, see the Memory Map section.
DS1875
PWM Controller
The DS1875 has a PWM controller that, when used with external components, generates a low-noise, high-voltage output to bias APDs in optical receivers. The achievable boost voltage is determined by the external component selection. Figure 12 shows a typical schematic. Selection of switching frequency, external inductor, capacitors, resistor network, switching FET, and switch diode determine the performance of the DC-DC converter. The PWM controller can be configured in boost or buck mode. Both modes require an external nMOS or npn transistor. The DS1875 PWM controller consists of several sections used to create a PWM signal to drive a DC-DC converter. Figure 11 is a block diagram of the DS1875 PWM controller. Following is a description of each block in the PWM controller and some guidelines for selecting components for the DC-DC converter. The PWM DAC is used to set the desired output voltage of the DC-DC converter section. The feedback from the DC-DC converter is compared to the output from the PWM DAC by an error amplifier. If the FB level is less
*This is the minimum reported coarse-mode conversion.
two thresholds. The actual threshold values are a function of the number of right-shifts being used. Table 7 shows the threshold values for each possible number of right-shifts. The RSSI_FF and RSSI_FC (Table 02h, Register 89h) bits are used to force fine-mode or coarse-mode conversions, or to disable the dual-range functionality. Dual-range functionality is enabled by default (both RSSI_FC and RSSI_FF are factory programmed to 0 in EEPROM). It can be disabled by setting RSSI_FC to 0
PWM EN PWM DAC TEMPERATUREREFERENCED LUT TABLE 07h MANUAL I2C CONTROL 10A MUX PWM DAC TABLE 02h REGISTER FEh PWM DAC 8-BIT 0 TO 1.25V
VOLTAGE CLAMP HIGH = 2.1V LOW = 0.8V COMP M3QT ERROR AMPLIFIER
GATE DRIVER 90% MAX DUTY CYCLE
SW
10A
1.9V DS1875 PWM CONTROLLER 90% DUTY CYCLE OSC FB RAMP 1.0V
PWM_FR[1:0]
Figure 11. PWM Controller Diagram
______________________________________________________________________________________ 25
PON Triplexer and SFP Controller
than the PWM DAC level, the error amplifier increases the level on the COMP pin. The level on the COMP pin is compared to the signal from the oscillator and ramp generator to set the duty cycle that is input to the gate driver and maximum duty-cycle limiting block. An increase on the COMP pin increases the duty cycle. Conversely, if FB is greater than the PWM DAC, the level on COMP is decreased, decreasing the duty cycle. The gate driver and maximum duty-cycle block is used to limit the maximum duty cycle of the PWM controller to 90%. This block also disables the PWM driver if an M3QT has resulted from the APD current exceeding a desired limit. The output from the PWM DAC is used to control the output voltage of the DC-DC converter. The values for the PWM DAC are recalled from the Table 07h, which is a temperature-indexed LUT. The temperature-indexed value from the LUT is written to the PWM DAC register (Table 02h, Register FEh), which updates the setting of the PWM DAC. The PWM DAC can also be operated in a manual mode by disabling the automatic updating from the LUT. This is done by clearing the PWM EN bit (Table 02h, Register 80h, Bit 5). The PWM DAC fullscale output is 1.25V with 8 bits of resolution. When designing the feedback for the DC-DC converter section, the user needs to make sure that the desired level applied to the FB pin is in this range. The COMP pin is driven by the error amplifier comparing the PWM DAC to the DC-DC converter feedback signal at the FB pin. The error amplifier can sink and source 10A. An external resistor and capacitor connected to the COMP pin determine the rate of change the COMP pin. The resistor provides an initial step when the current from the error amplifier changes. The capacitor determines how quickly the COMP pin charges to the desired level. The COMP pin has internal voltage clamps that limit the voltage level to a minimum of 0.8V and a maximum of 2.1V. The oscillator and ramp generator create a ramped signal. The frequency of this signal can be 131.25kHz, 262.5kHz, 525kHz, or 1050kHz and is set by the PWM_FR[1:0] bits (Table 02h, Register 88h, Bits 5:4). The low level and high level for the ramped signal are approximately 1.0V and 1.9V, respectively. The ramped signal is compared to the voltage level on the COMP pin to determine the duty cycle that is input to the gate driver and duty-cycle limiting block. When COMP is clamped low at 0.8V, below the level of the ramped signal, the comparator outputs a 0% dutycycle signal to the gate driver block. When COMP is clamped at 2.1V, above the level of the ramped signal, the comparator outputs a 100% duty-cycle signal to the gate driver and duty-cycle limiting block. The dutycycle liming block is used to limit the duty cycle of the PWM signal from the SW pin to 90%. The PWM controller is designed to protect expensive APDs against adverse operating conditions while providing optimal bias. The PWM controller monitors photodiode current to protect APDs under avalanche conditions using the MON3 quick trip. A voltage level that is proportional to the APD current can be input to the MON3 pin. When this voltage exceeds the level set by the M3QT DAC (Table 02h, Register C3h), pulses from the PWM controller are blocked until the fault is cleared. The quick trip can also toggle the digital output D2. D2 can be connected to an external FET to quickly discharge the DC-DC converter filter capacitors.
DS1875
Inductor Selection Optimum inductor selection depends on input voltage, output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and resistance (LR). The inductance value is given by:
L= VIN 2 x D 2 x T x 2 IOUT(MAX) x VOUT
Where: VIN = DC-DC converter input voltage VOUT = Output of DC-DC converter IOUT(MAX) = Maximum output current delivered T = Time period of switching frequency (seconds) D = Duty cycle = Estimated power conversion efficiency The equation for inductance factors in conversion efficiency. For inductor calculation purposes, an of 0.5 to 0.75 is usually suitable. For example, to obtain an output of 80V with a load current of 1.0mA from an input voltage of 5.0V using the maximum 90% duty cycle and frequency of 1050kHz (T = 952ns), and assuming an efficiency of 0.5, the previous equation yields an L of 120H, so a 100H inductor would be a suitable value. The peak inductor current is given by: IPK = VIN x D x T L
26
______________________________________________________________________________________
PON Triplexer and SFP Controller
Stability and Compensation Component Selection The components connected to the COMP pin (RCOMP and CCOMP) introduce a pole and zero that are necessary for stable operation of the PWM controller (Figure 12). The dominant pole, POLE1, is formed by the output impedance of the error amplifier (REA) and CCOMP. The zero formed by the components on COMP, ZERO1, is selected to cancel POLE2 formed by the output filter cap C3 and output load RLOAD. The additional pole, POLE3, formed by R1 and C3 should be at least a decade past the crossover frequency to not affect stability. The following formulas can be used to calculate the poles and zero for the application shown in Figure 12.
POLE1 (dominant pole) = 1/(2 x REA x CCOMP) ZERO1 (compensation zero) = 1/(2 x RCOMP x CCOMP) POLE2 (output load pole) = 2 x VOUT - VIN 1 x VOUT - VIN 2 x R LOAD x ( C2 + C3 ) POLE3 (output filter pole) = 1/(2 x R1 x C3) The DC open-loop gain is given by:
AOL = GM x R EA x V - VIN R LOAD x T 2 x VIN VFB x x OUT x 0. 85 2 x VOUT - VIN 2xL VOUT
M4DAC Output
The M4DAC output has a full-scale 2.5V range with 8 bits of resolution, and is controlled by an LUT indexed by the MON4 voltage. The M4DAC LUT (Table 06h) is nonvolatile and PW2 protected. See the Memory Organization section for details. The recalled value is either 16-bit or 32-bit depending on bits DBL_SB and UP_LOWB in Table 02h, Register C7h.
DS1875
Digital I/O Pins
Five digital I/O pins are provided for additional monitoring and control. By default the LOSI pin is used to convert a standard comparator output for loss of signal (LOSI) to an open-collector output. This means the mux shown on the block diagram by default selects the LOSI pin as the source for the D0 output transistor. The level of the D0 pin can be read in the STATUS byte (Lower Memory, Register 6Eh) as the LOS STATUS bit. The LOS STATUS bit reports back the logic level of the D0 pin, so an external pullup resistor must be provided for this pin to output a high level. The LOSI signal can be inverted before driving the open-drain output transistor using the XOR gate provided. The MUX LOS allows the D0 pin to be used identically to the D1, D2, and D3 pins. However, the mux setting (stored in the EEPROM) does not take effect until VCC > VPOA, allowing the EEPROM to recall. This requires the LOSI pin to be grounded for D0 to act identical to the D1, D2, and D3 pins. Digital pins D1, D2, and D3 can be used as inputs or outputs. External pullup resistors must be provided to realize high-logic levels. The DIN byte indicates the logic levels of these input pins (Lower Memory, Register 79h), and the open-drain outputs can be controlled using the DOUT byte (Lower Memory, Register 78h). When VCC < VPOA, these outputs are high impedance. Once V CC V POA , the outputs go to the power-on default state stored in the DPU byte (Table 02h, Register C0h). The EEPROM-determined default state of the pin can be modified with PW2 access. After the default state has been recalled, the SRAM registers controlling outputs can be modified without password access. This allows the outputs to be used to control serial interfaces without wearing out the default EEPROM setting. D2 can be configured as the output of a quick-trip monitor for MON3. The main application is to quickly shut down the PWM converter and discharge the voltage created by the converter. This is shown in the typical application circuit.
Where: REA = 260M GM = 425S RLOAD = Parallel combination of feedback network and load resistance VOUT = Output of DC-DC converter VIN = DC-DC converter input voltage VFB = Feedback voltage at the FB pin T = Time period of switching frequency (seconds) L = Inductor value (henries)
DAC1 Output
The DAC1 output has a full-scale 2.5V range with 8 bits of resolution, and is programmed through the I2C interface. The DAC1 setting is nonvolatile and password-2 (PW2) protected.
______________________________________________________________________________________
27
PON Triplexer and SFP Controller DS1875
VIN L1 C1 D1 C2 R1 C3 R2 SW Q1 R3 FB MAX4007 R4 3.3V VOUT
RCOMP CCOMP COMP
RMON
DS1875 D2 APD OVERLOAD QUICK TRIP
C4
ROSA APD
TIA
MON3
Figure 12. PWM Controller Typical APD Bias Circuit
CURRENT SINK VOLTAGE OUTPUT SW SW
DS1875 FB COMP
DS1875
FB COMP
Figure 13. PWM Controller Voltage Output Configuration
Figure 14. PWM Controller Current-Sink Output Configuration
28
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 15. I2C Timing Diagram
I2C Communication
I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 15 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 15 for applicable timing.
Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated START conditions are commonly used during read operations to identify a specific memory
address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 15 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (Figure 15). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read (Figure 15). The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledge-ment (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 15). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data.
29
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1875 responds to two slave addresses. The auxiliary memory always responds to a fixed I2C slave address, A0h. The Lower Memory and tables 00h-08h respond to I2C slave addresses that can be configured to any value between 00h-FEh using the Device Address byte (Table 02h, Register 8Ch). The user also must set the ASEL bit (Table 02h, Register 89h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS1875 assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent. If the main device's slave address is programmed to be A0h, access to the auxiliary memory is disabled. Memory Address: During an I2C write operation to the DS1875, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS1875 writes 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages result in the address counter wrapping around to the beginning of the present row. Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result is that addresses 06h and 07h contain 11h and 22h, respectively, and the third data byte, 33h, is written to address 00h. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time a EEPROM location is written, the DS1875 requires the EEPROM write time (tW) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS1875, which allows the next page to be written as soon as the DS1875 is ready to receive the data. The alternative to acknowledge polling is to wait for a maximum period of t W to elapse before attempting to write again to the DS1875. EEPROM Write Cycles: When EEPROM writes occur to the memory, the DS1875 writes the whole EEPROM memory page, even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes that
I2C Protocol
Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. The
30
______________________________________________________________________________________
PON Triplexer and SFP Controller
were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears the EEPROM out eight times faster than writing the entire page at once. The DS1875's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It can handle approximately 10 times that many writes at room temperature. Writing to SRAM-shadowed EEPROM memory with SEEB = 1 does not count as a EEPROM write cycle when evaluating the EEPROM's estimated lifetime. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers, as well as other miscellaneous control bytes. Table 03h is strictly user EEPROM that is protected by a PW2-level password. Table 04h contains a temperature-indexed LUT for control of the modulation voltage. The modulation LUT can be programmed in 2C increments over the -40C to +102C range. Access to this register is protected by a PW2-level password. Table 05h contains a temperature-indexed LUT that allows the APC set point to change as a function of temperature to compensate for Tracking Error (TE). The APC LUT has 36 entries that determine the APC setting in 4C windows between -40C to 100C. Access to this register is protected by a PW2-level password. Table 06h contains a MON4-indexed LUT for control of the M4DAC voltage. The MON4 LUT has 32 entries that are configurable to act as one 32-entry LUT of two 16byte LUTs. When configured as one 32-byte LUT, each entry corresponds to an increment of 1/32 the full scale. When configured as two 16-byte LUTs, the first 16 bytes and the last 16 bytes each correspond to 1/16 full scale. Either of the two sections is selected with a separate configuration bit. Access to this register is protected by a PW2-level password. Table 07h contains a temperature-indexed LUT for control of the PWM reference voltage (integration of FB input). The PWM LUT has 36 entries that determine the APC setting in 4C windows between -40C to +100C. Access to this register is protected by a PW2-level password. Table 08h contains a temperature-indexed LUT for control of the BIAS current. The BIAS LUT can be programmed in 2C increments over the 40C to +102C range. Access to this register is protected by a PW2level password. Auxiliary Memory (Device A0h) contains 256 bytes of EE memory accessible from address 00h-FFh. It is selected with the device address of A0h. See the Register Descriptions section for a more complete detail of each byte's function, as well as for read/write permissions for each byte.
DS1875
Memory Map
Memory Organization
The DS1875 features 10 separate memory tables that are internally organized into 8-byte rows. The Lower Memory is addressed from 00h to 7Fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the table select byte. Table 00h contains conversion results for MON5 through MON8. Table 01h primarily contains user EEPROM (with PW1 level access) as well as some alarm and warning status bytes.
______________________________________________________________________________________
31
PON Triplexer and SFP Controller DS1875
DEC HEX 0 0h I2C SLAVE ADDRESS A0h (FIXED) 00h AUXILIARY MEMORY I2C SLAVE ADDRESS A2h (DEFAULT) 00h LOWER MEMORY DIGITAL DIAGNOSTIC FUNCTIONS 2Fh 30h PW2 LEVEL ACCESS EEPROM (48 BYTES) 5Fh 60h DIGITAL DIAGNOSTIC FUNCTIONS 7Ah
PASSWORD ENTRY (PWE) (7Bh-Eh) TABLE SELECT BYTE EEPROM DEC HEX 128 80h 80h 89h MON5-MON8 CONV 80h 88h TABLE 01h PW1 LEVEL ACCESS EEPROM (120 BYTES) TABLE 02h CONFIGURATION AND CONTROL TABLE 03h PW2 LEVEL ACCESS EEPROM (128 BYTES) TABLE 04h MODULATION LUT TABLE 05h APC TE LUT TABLE 06h M4DAC LUT 9Fh A3h TABLE 00h NO MEMORY D8h NO MEMORY F7h F8h 255 FFh FFh 255 FFh FFh ATB FFh F7h F8h MISC. CONTROL FFh BITS FFh D7h C7h C7h A3h TABLE 07h PWM REF LUT TABLE 08h BIAS OPEN-LOOP LUT 80h 80h 80h 80h 80h 80h 80h 7Fh
Figure 16. Memory Map
Shadowed EEPROM
Many NV memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM that are controlled by the SEEB bit in Table 02h, Byte 80h. The DS1875 incorporates shadowed-EEPROM memory locations for key memory addresses that can be written many times. By default the shadowed-EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB, these locations function like SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tWR. Because changes made with SEEB disabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEEB enabled. This function can be used to limit the number of EEPROM writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times EEPROM is written. The Memory Map description indicates which locations are shadowed EEPROM.
32
______________________________________________________________________________________
PON Triplexer and SFP Controller
Register Descriptions
Lower Memory Register Map
This register map shows each byte/word (2 bytes) in terms of the row it is on in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word's address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description.
LOWER MEMORY ROW (HEX) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 ROW NAME
<1>THRESHOLD0 <1>THRESHOLD1 <1>THRESHOLD2 <1>THRESHOLD3 <1>THRESHOLD4 <1>THRESHOLD5 <1>PW2 EE <1>PW2 EE <1>PW2 EE <1>PW2 EE <1>PW2 EE <1>PW2 EE <2>ADC
DS1875
WORD 0 BYTE 0/8 BYTE 1/9 TEMP ALARM HI VCC ALARM HI MON1 ALARM HI MON2 ALARM HI MON3 ALARM HI MON4 ALARM HI EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B TEMP ALARM LO VCC ALARM LO MON1 ALARM LO MON2 ALARM LO MON3 ALARM LO MON4 ALARM LO EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D TEMP WARN HI VCC WARN HI MON1 WARN HI MON2 WARN HI MON3 WARN HI MON4 WARN HI EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F TEMP WARN LO VCC WARN LO MON1 WARN LO MON2 WARN LO MON3 WARN LO MON4 WARN LO EE EE EE EE EE EE EE EE EE EE EE EE
VALUES0
<0>ADC VALUES1 <2>ALARM/
TEMP VALUE
<2>MON3 VALUE
VCC VALUE
<2>MON4 VALUE
MON1 VALUE
<2>RESERVED
MON2 VALUE
<0>STATUS <3>UPDATE
WARN
<0>TABLE
ALARM3
<5>DOUT
ALARM2
<2>DIN
ALARM1
<6>
ALARM0
WARN3
WARN2
RESERVED RESERVED
<5>TBL
SELECT
RESERVED
<6>PWE MSB
<6>PWE LSB
SEL
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
33
PON Triplexer and SFP Controller DS1875
Table 00h Register Map
TABLE 00h ROW (HEX) 80 88-FF ROW NAME
<2>ADC VALUES2
WORD 0 BYTE 0/8 EMPTY BYTE 1/9 EMPTY MON5 VALUE
WORD 1 BYTE 2/A EMPTY BYTE 3/B EMPTY MON6 VALUE
WORD 2 BYTE 4/C EMPTY BYTE 5/D EMPTY MON7 VALUE
WORD 3 BYTE 6/E EMPTY BYTE 7/F EMPTY MON8 VALUE
EMPTY
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
34
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 01h Register Map
TABLE 01h (PW1) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 ROW NAME
<7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <7>PW1 EE <11>ALARM
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE ALARM3 BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE ALARM2 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE ALARM0 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE WARN2 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE RESERVED
TRAP
ALARM1
WARN3
RESERVED
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
35
PON Triplexer and SFP Controller DS1875
Table 02h Register Map
TABLE 02h (PW2) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8-F7 F8 ROW NAME
<0>CONFIG0 <8>CONFIG1 <8>SCALE0 <8>SCALE1 <8>OFFSET0 <8>OFFSET1 <9>PWD VALUE <8>INTERRUPT <8>CNTL OUT <8>SCALE2 <8>OFFSET1
WORD 0 BYTE 0/8
<8>MODE
WORD 1 BYTE 2/A BYTE 3/B
WORD 2 BYTE 4/C BYTE 5/D
<4>M4DAC
WORD 3 BYTE 6/E ID RSHIFT1 BYTE 7/F VER RSHIFT0
<10>DEVICE <10>DEVICE
BYTE 1/9
<4>TINDEX <4>MOD DAC <4>APC DAC <4>VINDEX
SAMPLE RATE
CONFIG
RESERVED
MOD RANGING
DEVICE ADDRESS
COMP RANGING
RESERVED MON3 FINE SCALE RESERVED MON3 FINE OFFSET PW1 MSW FETG ENABLE1 DPU FETG ENABLE0 RESERVED
VCC SCALE MON4 SCALE VCC OFFSET MON4 OFFSET PW1 LSW TX-F ENABLE1 RESERVED TX-F ENABLE0 M3QT DAC
MON1 SCALE MON3 COARSE SCALE MON1 OFFSET MON3 COARSE OFFSET PW2 MSW HTXP DAC1 LTXP RESERVED
MON2 SCALE RESERVED MON2 OFFSET INTERNAL TEMP OFFSET* PW2 LSW HBIAS RESERVED MAX BIAS M4 LUT CNTL
MON5 SCALE MON5 OFFSET EMPTY
<4>MAN
MON6 SCALE MON6 OFFSET EMPTY
<4>MAN_
MON7 SCALE MON7 OFFSET EMPTY
<10>BIAS
MON8 SCALE MON8 OFFSET EMPTY PWM DAC EMPTY RESERVED
EMPTY
<0>MAN BIAS
EMPTY
<4>MAN
EMPTY
<10>BIAS
EMPTY BIAS OL
BIAS1
BIAS0
CNTL
DAC1
DAC0
*The final result must be XORed with BB40h before writing to this register.
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
36
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 03h Register Map
TABLE 03h (PW2) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 ROW NAME
<8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE <8>PW2 EE
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
37
PON Triplexer and SFP Controller DS1875
Table 04h Register Map
TABLE 04h (MODULATION LUT) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 ROW NAME
<8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4 <8>LUT4
WORD 0 BYTE 0/8 MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 1/9 MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 1 BYTE 2/A MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 3/B MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 2 BYTE 4/C MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 5/D MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 3 BYTE 6/E MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 7/F MOD MOD MOD MOD MOD MOD MOD MOD MOD
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
Table 05h Register Map
TABLE 05h (APC TE LUT) ROW (HEX) 80 88 90 98 A0 ROW NAME
<8>LUT5 <8>LUT5 <8>LUT5 <8>LUT5 <8>LUT5
WORD 0 BYTE 0/8 APC REF APC REF APC REF APC REF APC REF BYTE 1/9 APC REF APC REF APC REF APC REF APC REF
WORD 1 BYTE 2/A APC REF APC REF APC REF APC REF APC REF BYTE 3/B APC REF APC REF APC REF APC REF APC REF
WORD 2 BYTE 4/C APC REF APC REF APC REF APC REF RESERVED BYTE 5/D APC REF APC REF APC REF APC REF RESERVED
WORD 3 BYTE 6/E APC REF APC REF APC REF APC REF RESERVED BYTE 7/F APC REF APC REF APC REF APC REF RESERVED
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
38
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 06h Register Map
TABLE 06h (M4DAC LUT) ROW (HEX) 80 88 90 98 ROW NAME
<8>LUT6 <8>LUT6 <8>LUT6 <8>LUT6
WORD 0 BYTE 0/8 M4DAC M4DAC M4DAC M4DAC BYTE 1/9 M4DAC M4DAC M4DAC M4DAC
WORD 1 BYTE 2/A M4DAC M4DAC M4DAC M4DAC BYTE 3/B M4DAC M4DAC M4DAC M4DAC
WORD 2 BYTE 4/C M4DAC M4DAC M4DAC M4DAC BYTE 5/D M4DAC M4DAC M4DAC M4DAC
WORD 3 BYTE 6/E M4DAC M4DAC M4DAC M4DAC BYTE 7/F M4DAC M4DAC M4DAC M4DAC
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
Table 07h Register Map
TABLE 07h (PWM REFERENCE LUT) ROW (HEX) 80 88 90 98 A0 ROW NAME
<8>LUT7 <8>LUT7 <8>LUT7 <8>LUT7 <8>LUT7
WORD 0 BYTE 0/8 PWM REF PWM REF PWM REF PWM REF PWM REF BYTE 1/9 PWM REF PWM REF PWM REF PWM REF PWM REF
WORD 1 BYTE 2/A PWM REF PWM REF PWM REF PWM REF PWM REF BYTE 3/B PWM REF PWM REF PWM REF PWM REF PWM REF
WORD 2 BYTE 4/C PWM REF PWM REF PWM REF PWM REF RESERVED BYTE 5/D PWM REF PWM REF PWM REF PWM REF RESERVED
WORD 3 BYTE 6/E PWM REF PWM REF PWM REF PWM REF RESERVED BYTE 7/F PWM REF PWM REF PWM REF PWM REF RESERVED
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
39
PON Triplexer and SFP Controller DS1875
Table 08h Register Map
TABLE 08h (BIAS OPEN-LOOP LUT) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 ROW NAME
<8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8 <8>LUT8
WORD 0 BYTE 0/8 BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BYTE 1/9 BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL
WORD 1 BYTE 2/A BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BYTE 3/B BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL
WORD 2 BYTE 4/C BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BYTE 5/D BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL
WORD 3 BYTE 6/E BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BYTE 7/F BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL BIAS_OL
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
40
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Auxiliary A0h Memory Register Map
AUXILIARY MEMORY (A0h) ROW (HEX) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 ROW NAME
<5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE <5>AUX EE
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ACCESS CODE Read Access Write Access
<0>
<1> All
<2> All
<3> All All and DS1875 hardware
<4> PW2 PW2 + mode bit
<5> All
<6> N/A
<7> PW1
<8> PW2
<9> N/A
<10> PW2
<11> All
See each bit/byte separately
PW2
N/A
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
41
PON Triplexer and SFP Controller DS1875
Lower Memory Register Descriptions
Lower Memory, Register 00h to 01h: TEMP ALARM HI Lower Memory, Register 04h to 05h: TEMP WARN HI
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 26 2-2 7FFFh All PW2 Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0
00h, 04h 01h, 05h
S 2-1 BIT 7
Temperature measurement updates above this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit.
Lower Memory, Register 02h to 03h: TEMP ALARM LO Lower Memory, Register 06h to 07h: TEMP WARN LO
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 26 2-2 8000h All PW2 Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0
02h, 06h 03h, 07h
S 2-1 BIT 7
Temperature measurement updates below this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit.
42
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 08h to 09h: VCC ALARM HI Lower Memory, Register 0Ch to 0Dh: VCC WARN HI Lower Memory, Register 10h to 11h: MON1 ALARM HI Lower Memory, Register 14h to 15h: MON1 WARN HI Lower Memory, Register 18h to 19h: MON2 ALARM HI Lower Memory, Register 1Ch to 1Dh: MON2 WARN HI Lower Memory, Register 20h to 21h: MON3 ALARM HI Lower Memory, Register 24h to 25h: MON3 WARN HI Lower Memory, Register 28h to 29h: MON4 ALARM HI Lower Memory, Register 2Ch to 2Dh: MON4 WARN HI
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 08h, 0Ch, 10h, 14h, 18h, 1Ch, 20h, 24h, 28h, 2Ch 09h, 0Dh, 11h, 15h, 19h, 1Dh, 21h, 25h, 29h, 2Dh FFFFh All PW2 Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit.
______________________________________________________________________________________
43
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 0Ah to 0Bh: VCC ALARM LO Lower Memory, Register 0Eh to 0Fh: VCC WARN LO Lower Memory, Register 12h to 13h: MON1 ALARM LO Lower Memory, Register 16h to 17h: MON1 WARN LO Lower Memory, Register 1Ah to 1Bh: MON2 ALARM LO Lower Memory, Register 1Eh to 1Fh: MON2 WARN LO Lower Memory, Register 22h to 23h: MON3 ALARM LO Lower Memory, Register 26h to 27h: MON3 WARN LO Lower Memory, Register 2Ah to 2Bh: MON4 ALARM LO Lower Memory, Register 2Eh to 2Fh: MON4 WARN LO
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 0Ah, 0Eh, 12h, 16h, 1Ah, 1Eh, 22h, 26h, 2Ah, 2Eh 0Bh, 0Fh, 13h, 17h, 1Bh, 1Fh, 23h, 27h, 2Bh, 2Fh 0000h All PW2 Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit.
44
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 30h to 5Fh: PW2 EE
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW2 Nonvolatile (EE)
30h to 5Fh
EE BIT 7
EE
EE
EE
EE
EE
EE
EE BIT 0
PW2 level access-controlled EEPROM.
Lower Memory, Register 60h to 61h: TEMP VALUE
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 26 2-2 0000h All N/A Volatile 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0
60h 61h
S 2-1 BIT 7
Signed two's complement direct-to-temperature measurement.
______________________________________________________________________________________
45
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 62h to 63h: VCC VALUE Lower Memory, Register 64h to 65h: MON1 VALUE Lower Memory, Register 66h to 67h: MON2 VALUE Lower Memory, Register 68h to 69h: MON3 VALUE Lower Memory, Register 6Ah to 6Bh: MON4 VALUE
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 62h, 64h, 66h, 68h, 6Ah 63h, 65h, 67h, 69h, 6Bh 0000h All N/A Volatile
215
214
213
212
211
210
29
28
27 BIT 7
26
25
24
23
22
21
20 BIT 0
Left-justified unsigned voltage measurement.
Lower Memory, Register 6Ch to 6D: RESERVED
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A
6Ch, 6Dh
0 BIT 7
0
0
0
0
0
0
0 BIT 0
These registers are reserved. The value when read is 00h.
46
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 6Eh: STATUS
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access 6Eh X000 0XXXb All See below Volatile
N/A FETG STATUS BIT 7
All SOFT FETG
N/A RESERVED
All TX-F RESET
All SOFT TX-D
N/A TX-F STATUS
N/A LOS STATUS
N/A RDYB BIT 0
BIT 7
FETG STATUS: Reflects the active state of FETG. The FETG DIR bit in Table 02h, Register 89h defines the polarity of FETG. 0 = Normal operation. Bias and modulation outputs are enabled. 1 = The FETG output is active. Bias and modulation outputs are disabled. SOFT FETG: 0 = (Default) 1 = Forces the bias and modulation outputs to their off state and assert the FETG output. RESERVED (Default = 0) TX-F RESET: 0 = (Default) 1 = Resets the latch for the TX-F output. This bit is self-clearing after resetting TX-F. SOFT TX-D: This bit allows a software control that is identical to the TX-D pin. See the BIAS and MOD Output as a Function of Transmit Disable (TX-D) section for further information. Its value is wired-ORed with the logic value of the TX-D pin. 0 = Internal TX-D signal is equal to the external TX-D pin. 1 = Internal TX-D signal is high. TX-F STATUS: Reflects the active state of the TX-F pin. 0 = TX-F pin is not active. 1 = TX-F pin is active. LOS STATUS: Loss of Signal. Reflects the logic level of the LOSI input pin. 0 = LOSI is logic-low. 1 = LOSI is logic-high. RDBY: Ready Bar. 0 = VCC is above POA. 1 = VCC is below POA and/or too low to communicate over the I2C bus.
BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
______________________________________________________________________________________
47
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 6Fh: UPDATE
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All All + DS1875 Hardware Volatile
6Fh
TEMP RDY BIT 7
VCC RDY
MON1 RDY
MON2 RDY
MON3 RDY
MON4 RDY
MON5/7 RDY
MON6/8 RDY BIT 0
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified.
48
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 70h: ALARM3
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 10h All N/A Volatile
70h
TEMP HI BIT 7
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO BIT 0
BIT 7
TEMP HI: High alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High alarm status for VCC measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. MON1 HI: High alarm status for MON1 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON1 LO: Low alarm status for MON1 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. MON2 HI: High alarm status for MON2 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON2 LO: Low alarm status for MON2 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting.
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
______________________________________________________________________________________
49
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 71h: ALARM2
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A Volatile
71h
MON3 HI BIT 7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED BIT 0
BIT 7
MON3 HI: High alarm status for MON3 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON3 LO: Low alarm status for MON3 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. MON4 HI: High alarm status for MON4 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON4 LO: Low alarm status for MON4 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. RESERVED
BIT 6
BIT 5
BIT 4 BITS 3:0
50
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 72h: ALARM1
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A Volatile
72h
RESERVED BIT 7
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TXP HI
TXP LO BIT 0
BITS 7:4 BIT 3 BIT 2 BIT 1
RESERVED BIAS HI: High alarm status bias; fast comparison. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. RESERVED TXP HI: High alarm status TXP; fast comparison. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. TXP LO: Low alarm status TXP; fast comparison. 0 = (Default) Last comparison was above threshold setting. 1 = Last comparison was below threshold setting.
BIT 0
Lower Memory, Register 73h: ALARM0
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A Volatile
73h
M3QT HI BIT 7
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
RESERVED BIT 0
BIT 7 BITS 6:4 BIT 3 BITS 2:0
M3QT HI: High alarm status for MON3; fast comparison. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. RESERVED BIAS MAX: Alarm status for maximum digital setting of BIAS. 0 = (Default) The value for BIAS is equal to or below the MAX BIAS register. 1 = Requested value for BIAS is greater than the MAX BIAS register. RESERVED
______________________________________________________________________________________
51
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 74h: WARN3
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 10h All N/A Volatile
74h
TEMP HI BIT 7
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO BIT 0
BIT 7
TEMP HI: High warning status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low warning status for temperature measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High warning status for VCC measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. MON1 HI: High warning status for MON1 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON1 LO: Low warning status for MON1 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. MON2 HI: High warning status for MON2 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON2 LO: Low warning status for MON2 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting.
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
52
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 75h: WARN2
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A Volatile
75h
MON3 HI BIT 7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED BIT 0
BIT 7
MON3 HI: High warning status for MON3 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON3 LO: Low warning status for MON3 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. MON4 HI: High warning status for MON4 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON4 LO: Low warning status for MON4 measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. RESERVED
BIT 6
BIT 5
BIT 4 BITS 3:0
Lower Memory Register 76h to 77h: RESERVED MEMORY
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers are reserved. The value when read is 00h. 00h All N/A
______________________________________________________________________________________
53
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 78h: DOUT
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE M3QT RESET BIT 7 SOFT M3QT Recalled from Table 02h, Register C0h All All Volatile
78h
RESERVED
RESERVED
D3 OUT
D2 OUT
D1 OUT
D0 OUT BIT 0
BIT 7
M3QT RESET: Resets the latch for M3QT. The PWM does not begin normal operation until the MON3 voltage is below M3QT, regardless of resetting the latch. 0 = (default) 1 = M3QT alarm is reset. SOFT M3QT: Software control for setting the M3QT alarm. The PWM output pulse SW is disabled. 0 = (Default) Internal signal is controlled by trip point comparison. 1 = M3QT alarm is set to 1. RESERVED D3 OUT: Controls the output of the open-drain pin D3. 0 = Output is held low. 1 = Output is high impedance. D2 OUT: Controls the output of the open-drain pin D2. 0 = Output is held low. 1 = Output is high impedance. D1 OUT: Controls the output of the open-drain pin D1. 0 = Output is held low. 1 = Output is high impedance. D0 OUT: Controls the output of the open-drain pin D0. 0 = Output is held low. 1 = Output is high impedance.
BIT 6 BITS 5:4 BIT 3
BIT 2
BIT 1
BIT 0
At power-on, these bits are defined by the value stored in the DPU byte (Table 02h, Register C0h). These bits define the value of the logic states of their corresponding output pins.
54
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 79h: DIN
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE See description All N/A Volatile
79h
INV M3QT BIT 7
MUX M3QT
INV LOS
MUX LOS
D3 IN
D2 IN
D1 IN
D0 IN BIT 0
BIT 7
INV M3QT: Status of inversion of M3QT (internal signal) to D2 pin. MUX M3QT bit must be set to 1 or this bit does not affect the output. The value is controlled (or set) by the DPU byte. 1 = M3QT buffered to D2 is inverted. MUX M3QT: Determines control of D2 pin. The value is controlled (or set) by the DPU byte. 0 = Logic value of D2 is controlled by DOUT byte. 1 = Logic value of D2 is controlled by M3QT (internal signal) and INV M3QT bit. INV LOS: Status of inversion of LOSI pin to D0 pin. MUX LOS bit must be set to 1 or this bit does not effect the output. The value is controlled (or set) by the DPU byte. 1 = LOSI buffered D0 is inverted. MUX LOS: Determines control of D0 pin. The value is controlled (or set) by the DPU byte. 0 = Logic value of D0 is controlled by DOUT byte. 1 = Logic value of D0 is controlled by LOSI pin and INV LOS bit. D3 IN: Reflects the logic value of D3 pin. D2 IN: Reflects the logic value of D2 pin. D1 IN: Reflects the logic value of D1 pin. D0 IN: Reflects the logic value of D0 pin.
BIT 6
BIT 5
BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Lower Memory, Register 7Ah: RESERVED
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All N/A N/A
This register is reserved. The value when read is 00h.
______________________________________________________________________________________
55
PON Triplexer and SFP Controller DS1875
Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE)
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A All Volatile 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0
7Bh 7Ch 7Dh 7Eh
There are two passwords for the DS1875. Each password is 4 bytes long. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At power-up, all PWE bits are set to 1. All reads at this location are 0.
Lower Memory, Register 7Fh: Table Select (TBL SEL)
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h All All Volatile 25 24 23 22 21 20 BIT 0
7Fh
The upper memory tables (Table 00h to 08h) of the DS1875 are accessible by writing the desired table value in this register.
56
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 00h Register Descriptions
Table 00h, Register 80h to 81h: MON5 VALUE Table 00h, Register 82h to 83h: MON6 VALUE Table 00h, Register 84h to 85h: MON7 VALUE Table 00h, Register 86h to 87h: MON8 VALUE
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h, 82h, 84h, 86h 81h, 83h, 85h, 87h 0000h All N/A Volatile
215 27 BIT 7
214 26
213 25
212 24
211 23
210 22
29 21
28 20 BIT 0
Left-justified unsigned voltage measurement.
Table 01h Register Descriptions
Table 01h, Register 80h to F7h: PW1 EEPROM
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW1 PW1 Nonvolatile (EE)
80h to F7h
EE BIT 7
EE
EE
EE
EE
EE
EE
EE BIT 0
EEPROM for PW1-level access.
______________________________________________________________________________________
57
PON Triplexer and SFP Controller DS1875
Table 01h, Register F8h: ALARM3
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
F8h
TEMP HI BIT 7
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h with two exceptions. 1. VCC LO alarm is not set at power-on. 2. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register F9h: ALARM2
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
F9h
MON3 HI BIT 7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED BIT 0
Layout is identical to ALARM2 in Lower Memory, Register 71h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access.
58
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 01h, Register FAh: ALARM1
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
FAh
RESERVED BIT 7
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TXP HI
TXP LO BIT 0
Layout is identical to ALARM1 in Lower Memory, Register 72h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FBh: ALARM0
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
FBh
M3QT HI BIT 7
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
RESERVED BIT 0
Layout is identical to ALARM0 in Lower Memory, Register 73h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access
Table 01h, Register FCh: WARN3
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
FCh
TEMP HI BIT 7
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO BIT 0
Layout is identical to WARN3 in Lower Memory, Register 74h with two exceptions. 1. VCC LO warning is not set at power-on. 2. These bits are latched. They are cleared by power-down or a write with PW1 access.
______________________________________________________________________________________
59
PON Triplexer and SFP Controller DS1875
Table 01h, Register FDh: WARN2
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
FDh
MON3 HI BIT 7
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
RESERVED BIT 0
Layout is identical to WARN2 in Lower Memory, Register 75h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FEh to FFh: RESERVED
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 00h All PW1 Volatile
These registers are reserved.
60
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h Register Descriptions
Table 02h, Register 80h: MODE
POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB BIT 7 RESERVED 3Fh PW2 PW2 Volatile PWM EN M4DAC EN AEN MOD EN APC EN BIAS EN BIT 0 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. RESERVED PWM EN: 0 = PWM DAC is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for the PWM DAC. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for PWM DAC. M4DAC EN: 0 = M4DAC is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for M4DAC. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for M4DAC. AEN: 0 = The temperature-calculated index value TINDEX is writable by users and the updates of calculated indexes are disabled. This allows users to interactively test their modules by controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC registers after the next completion of a temperature conversion. MOD EN: 0 = MOD DAC is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for modulation. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for modulation. APC EN: 0 = APC DAC is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for APC reference. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for APC reference. BIAS EN: 0 = BIAS DAC is controlled by the user and the APC is in manual mode. The BIAS DAC value is written to the MAN BIAS register. All values that are written to MAN BIAS and are greater than the MAX BIAS register setting are not updated and set the BIAS MAX alarm bit. The BIAS DAC register continues to reflect the value of the BIAS DAC. This allows users to interactively test their modules by writing the DAC value for bias. The output is updated with the new value at the end of the write cycle to the MAN BIAS register. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control for the APC feedback.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
______________________________________________________________________________________
61
PON Triplexer and SFP Controller DS1875
Table 02h, Register 81h: Temperature Index (TINDEX)
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and AEN = 0 Volatile 25 24 23 22 21 20 BIT 0
81h
Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h, 05h, 07h, and 08h. Temperature measurements below -40C or above +102C are clamped to 00h and C7h, respectively. The calculation of TINDEX is as follows:
TINDEX =
Temp _ Value + 40C + 80h 2C
For the temperature-indexed LUTs, the index used during the lookup function for each table is as follows: Table 04h (MOD) Table 05h (APC) Table 07h (PWM) Table 08h (BIAS) 1 1 1 1 TINDEX6 0 0 TINDEX6 TINDEX5 TINDEX6 TINDEX6 TINDEX5 TINDEX4 TINDEX5 TINDEX5 TINDEX4 TINDEX3 TINDEX4 TINDEX4 TINDEX3 TINDEX2 TINDEX3 TINDEX3 TINDEX2 TINDEX1 TINDEX2 TINDEX2 TINDEX1 TINDEX0 TINDEX1 TINDEX1 TINDEX0
Table 02h, Register 82h: MOD DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and MOD EN = 0 Volatile 25 24 23 22 21 20 BIT 0
82h
The digital value used for MOD and recalled from Table 04h at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
VMOD =
Full Scale 255
MOD DAC
62
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register 83h: APC DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and APC EN = 0 Volatile 25 24 23 22 21 20 BIT 0
83h
The digital value used for APC reference and recalled from Table 05h at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
VBMD =
Full Scale 255
APC DAC
Table 02h, Register 84h: Voltage Index (VINDEX)
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and AEN = 0 Volatile 25 24 23 22 21 20 BIT 0
84h
Holds the calculated index based on the MON4 voltage measurement. This index is used for the address during lookup of Table 06h. M4DAC LUT is 32 bytes from address 80h to 9Fh. The calculation of VINDEX is as follows:
VINDEX =
MON4 + 80h 800h
When configured as a single LUT, all 32 bytes are used for lookup. When configured as a double LUT, the first 16 bytes (80h to 8Fh) form the lower LUT and the last 16 bytes (90h to 9Fh) form the upper LUT. For the three different modes, the index used during the lookup function of Table 06h is as follows: Single Double/Lower Double/Upper 1 1 1 0 0 0 0 0 0 VINDEX4 0 1 VINDEX3 VINDEX4 VINDEX4 VINDEX2 VINDEX3 VINDEX3 VINDEX1 VINDEX2 VINDEX2 VINDEX0 VINDEX1 VINDEX1
______________________________________________________________________________________
63
PON Triplexer and SFP Controller DS1875
Table 02h, Register 85h: M4DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and M4DAC EN = 0 Volatile 25 24 23 22 21 20 BIT 0
85h
The digital value used for M4DAC and recalled from Table 06h at the adjusted memory address found in VINDEX. This register is updated at the end of the MON4 conversion.
VM4DAC =
2.5 256
(M4DAC + 1)
Table 02h, Register 86h: DEVICE ID
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 75h PW2 N/A ROM
86h
0 BIT 7
1
1
1
0
1
0
1 BIT 0
Hardwired connections to show the device ID.
Table 02h, Register 87h: DEVICE VER
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE DEVICE VERSION PW2 N/A ROM
87h BIT 7
DEVICE VERSION BIT 0
Hardwired connections to show device version.
64
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register 88h: SAMPLE RATE
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h PW2 PW2 Nonvolatile (SEE)
88h
SEE BIT 7
SEE
PWM_FR1
PWM_FR0
APC_SR3
APC_SR2
APC_SR1
APC_SR0 BIT 0
BITS 7:6
SEE PWM_FR[1:0]: 2-bit frequency rate for the SW pulsed output used with PWM. When switching a lower to a higher frequency, disable the SW output by setting SOFT M3QT (Byte 78h) to a 1 before changing PWM_FR. After changing PWM_FR, wait 200 periods of the new frequency before enabling the SW output. This delay allows for the internal signals to integrate and lock to the new frequency without creating a large duty cycle. 00b: 131.25kHz 01b: 262.5kHz 10b: 525kHz 11b: 1050kHz (Default) APC_SR[3:0]: 4-bit sample rate for comparison of APC control.
BITS 5:4
BITS 3:0
Defines the sample rate for comparison of APC control.
MINIMUM TIME FROM BEN TO FIRST SAMPLE (tFIRST) 50ns (ns) 350 550 750 950 1350 1550 1750 2150 2950 3150 REPEATED SAMPLE PERIOD FOLLOWING FIRST SAMPLE (tREP) (ns) 800 1200 1600 2000 2800 3200 3600 4400 6000 6400
APC_SR[3:0]
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b*
*All codes greater than 1001b (1010b to 1111b) use the maximum sample time of code 1001b.
______________________________________________________________________________________
65
PON Triplexer and SFP Controller DS1875
Table 02h, Register 89h: CONFIG
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
89h
FETG DIR BIT 7
TX-F LEN
M3QT LEN
ASEL
BOLFS
RSSI_FC
RSSI_FF
EN5TO8B BIT 0
Configure the memory location and the polarity of the digital outputs.
BIT 7
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation. 0 = (Default) Under normal operation, FETG is pulled low. 1 = Under normal operation, FETG is pulled high. TX-F LEN: The TX-F output pin always reflects the wired-OR of all TX-F enabled alarm states. This bit enables the latching of the alarm state for the TX-F output pin. 0 = (Default) Not latched. 1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If the VCC alarm is enabled for either FETG or TX-F, then latching is disabled until after the first VCC measurement is made above the VCC ALARM LO set point to allow for proper operation during slow power-on cycles. M3QT LEN: This bit enables the latching of the alarm for the M3QT. 0 = (Default) Not latched. 1 = The alarm bit is latched until cleared by setting the M3QT RESET bit (Byte 78h). ASEL: Address select. 0 = (Default) Device address of A2h. 1 = Device address is equal to the value found in the DEVICE ADDRESS byte (Table 02h, 8Ch). BOLFS: Bias open-loop full scale. 0 = (Default) Full scale is 600A. 1 = Full scale is 1.2mA. RSSI_FC and RSSI_FF: RSSI force coarse and RSSI force fine. Control bits for RSSI mode of operation on the MON3 conversion. 00b = (Default) Normal RSSI mode of operation. 01b = The fine settings of scale and offset are used for MON3 conversions. 10b = The coarse settings of scale and offset are used for MON3 conversions. 11b = Normal RSSI mode of operation. EN5TO8B: This bit enables MON5-MON8 conversion (voltage of D0-D3 pins). 0 = (Default) Temperature, VCC, and MON1-MON8 conversions are enabled. 1 = Temperature, VCC, and MON1-MON4 conversions are enabled.
BIT 6
BIT 5
BIT 4
BIT 3
BITS 2:1
BIT 0
66
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register 8Ah: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. 00h PW2 PW2 Nonvolatile (SEE)
Table 02h, Register 8Bh: MOD RANGING
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
8Bh
RESERVED BIT 7
RESERVED
RESERVED
RESERVED
RESERVED
MOD2
MOD1
MOD0 BIT 0
The lower nibble of this byte controls the full-scale range of the Modulation DAC BITS 7:3 RESERVED (Default = 0) MOD[2:0]: MOD FS RANGING: 3-bit value to select the FS output voltage for MOD. Default is 000b and creates a FS of 1.25V. MOD[2:0] 000b 001b 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.05 66.75 50.13 40.15 33.50 28.74 25.17 FS VOLTAGE (V) 1.250 1.001 0.834 0.627 0.502 0.419 0.359 0.315
BITS 2:0
______________________________________________________________________________________
67
PON Triplexer and SFP Controller DS1875
Table 02h, Register 8Ch: DEVICE ADDRESS
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
8Ch
This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is set. If A0h is programmed to this register, the auxiliary memory is disabled.
68
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register 8Dh: COMP RANGING
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
8Dh
RESERVED BIT 7
BIAS2
BIAS1
BIAS0
RESERVED
APC2
APC1
APC0 BIT 0
The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closedloop monitoring of APC.
BIT 7
RESERVED (Default = 0) BIAS[2:0] BIAS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BIAS found on MON1. Default is 000b and creates a FS of 1.25V. BIAS[2:0] 000b 001b % OF 1.25V 100.00 80.04 66.73 50.10 40.11 33.45 28.69 25.12 FS VOLTAGE (V) 1.250 1.001 0.834 0.626 0.501 0.418 0.359 0.314
BITS 6:4
010b 011b 100b 101b 110b 111b
BIT 3
RESERVED (Default = 0) APC[2:0] APC Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BMD with the APC. Default is 000b and creates a FS of 2.5V. APC[2:0] 000b 001b % OF 2.50V 100.00 80.04 66.73 50.10 40.11 33.45 28.69 25.12 FS VOLTAGE (V) 1.250 1.001 0.834 0.626 0.501 0.418 0.359 0.314
BITS 2:0
010b 011b 100b 101b 110b 111b
______________________________________________________________________________________
69
PON Triplexer and SFP Controller DS1875
Table 02h, Register 8Eh: RIGHT SHIFT1 (RSHIFT1)
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
8Eh
RESERVED BIT 7
MON12
MON11
MON10
RESERVED
MON22
MON21
MON20 BIT 0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.
Table 02h, Register 8Fh: RIGHT SHIFT0 (RSHIFT0)
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 30h PW2 PW2 Nonvolatile (SEE)
8Fh
RESERVED BIT 7
MON32
MON31
MON30
RESERVED
MON42
MON41
MON40 BIT 0
Allows for right-shifting the final answer of MON3 and MON4 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.
Table 02h, Register 90h to 91h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 0000h PW2 PW2 Nonvolatile (SEE)
These registers are reserved.
70
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register 92h to 93h: VCC SCALE Table 02h, Register 94h to 95h: MON1 SCALE Table 02h, Register 96h to 97h: MON2 SCALE Table 02h, Register 98h to 99h: MON3 FINE SCALE Table 02h, Register 9Ah to 9Bh: MON4 SCALE Table 02h, Register 9Ch to 9Dh: MON3 COARSE SCALE
FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE 92h, 94h, 96h, 98h, 9Ah, 9Ch 93h, 95h, 97h, 99h, 9Bh, 9Dh PW2 PW2 Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27 BIT 7
26
25
24
23
22
21
20 BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for VCC and 2.5V for MON1, MON2, MON3, and MON4.
Table 02h, Register 9Eh to A1h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
These registers are reserved.
______________________________________________________________________________________
71
PON Triplexer and SFP Controller DS1875
Table 02h, Register A2h to A3h: VCC OFFSET Table 02h, Register A4h to A5h: MON1 OFFSET Table 02h, Register A6h to A7h: MON2 OFFSET Table 02h, Register A8h to A9h: MON3 FINE OFFSET Table 02h, Register AAh to ABh: MON4 OFFSET Table 02h, Register ACh to ADh: MON3 COARSE OFFSET
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE A2h, A4h, A6h, A8h, AAh, ACh A3h, A5h, A7h, A9h, ABh, ADh 00h PW2 PW2 Nonvolatile (SEE)
S
S
215
214
213
212
211
210
29 BIT 7
28
27
26
25
24
23
22 BIT 0
Allows for offset control of these voltage measurements if desired.
Table 02h, Register AEh to AFh: INTERNAL TEMP OFFSET
FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE 28 20 PW2 PW2 Nonvolatile (SEE) 27 2-1 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 BIT 0
AEh AFh
S 21 BIT 7
Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.
72
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register B0h to B3h: PW1
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0
B0h B1h B2h B3h
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all 1s. Thus, writing these bytes to all 1s grants PW1 access on power-on without writing the password entry. All reads of this register are 00h.
Table 02h, Register B4h to B7h: PW2
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0
B4h B5h B6h B7h
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all 1s. Thus writing these bytes to all 1s grants PW2 access on power-on without writing the password entry. All reads of this register are 00h.
______________________________________________________________________________________
73
PON Triplexer and SFP Controller DS1875
Table 02h, Register B8h: FETG ENABLE1
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
B8h
TEMP EN BIT 7
VCC EN
MON1 EN
MON2 EN
MON3 EN
MON4 EN
RESERVED
RESERVED BIT 0
Configures the maskable interrupt for the FETG pin.
BIT 7
TEMP EN: Enables/disables active interrupts on the FETG pin due to temperature measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable VCC EN: Enables/disables active interrupts on the FETG pin due to VCC measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON1 EN: Enables/disables active interrupts on the FETG pin due to MON1 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON2 EN: Enables/disables active interrupts on the FETG pin due to MON2 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON3 EN: Enables/disables active interrupts on the FETG pin due to MON3 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON4 EN: Enables/disables active interrupts on the FETG pin due to MON4 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable RESERVED (Default = 0)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BITS 1:0
74
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register B9h: FETG ENABLE0
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE) BIAS MAX EN
B9h
TXP HI EN BIT 7
TXP LO EN
BIAS HI EN
RESERVED
RESERVED
RESERVED
RESERVED BIT 0
Configures the maskable interrupt for the FETG pin.
BIT 7
TXP HI EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons above the threshold limit. 0 = Disable (Default) 1 = Enable TXP LO EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons below the threshold limit. 0 = Disable (Default) 1 = Enable BIAS HI EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons above the threshold limit. 0 = Disable. (Default) 1 = Enable BIAS MAX EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons below the threshold limit. 0 = Disable (Default) 1 = Enable RESERVED (Default = 0)
BIT 6
BIT 5
BIT 4
BITS 3:0
______________________________________________________________________________________
75
PON Triplexer and SFP Controller DS1875
Table 02h, Register BAh: TX-F ENABLE1
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
BAh
TEMP EN BIT 7
VCC EN
MON1 EN
MON2 EN
MON3 EN
MON4 EN
RESERVED
RESERVED BIT 0
Configures the maskable interrupt for the TX-F pin.
BIT 7
TEMP EN: Enables/disables active interrupts on the TX-F pin due to temperature measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable VCC EN: Enables/disables active interrupts on the TX-F pin due to VCC measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON1 EN: Enables/disables active interrupts on the TX-F pin due to MON1 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON2 EN: Enables/disables active interrupts on the TX-F pin due to MON2 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON3 EN: Enables/disables active interrupts on the TX-F pin due to MON3 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable MON4 EN: Enables/disables active interrupts on the TX-F pin due to MON4 measurements outside the threshold limits. 0 = Disable (Default) 1 = Enable RESERVED (Default = 0)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BITS 2:0
76
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register BBh: TX-F ENABLE0
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE) BIAS MAX EN
BBh
TXP HI EN BIT 7
TXP LO EN
BIAS HI EN
RESERVED
RESERVED
RESERVED
FETG EN BIT 0
Configures the maskable interrupt for the TX-F pin.
BIT 7
TXP HI EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons above the threshold limit. 0 = Disable (Default) 1 = Enable TXP LO EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons below the threshold limit. 0 = Disable (Default) 1 = Enable BIAS HI EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons above the threshold limit. 0 = Disable (Default) 1 = Enable BIAS MAX EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons above the threshold limit. 0 = Disable (Default) 1 = Enable RESERVED (Default = 0) FETG EN: 0 = Normal FETG operation (Default). 1 = Enables FETG to act as an input to TX-F output.
BIT 6
BIT 5
BIT 4
BITS 3:1 BIT 0
______________________________________________________________________________________
77
PON Triplexer and SFP Controller DS1875
Table 02h, Register BCh: HTXP
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
BCh
Fast comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from Table 04h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than VHTXP, compared against VBMD, create a TXP HI alarm. The same ranging applied to the APC DAC should be used here.
VHTXP =
Full Scale 255
(HTXP + APC DAC)
Table 02h, Register BDh: LTXP
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
BDh
Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC DAC value recalled from Table 04h. If the difference is less than 0x00, 0x00 is used. Comparisons less than VLTXP, compared against VBMD, create a TXP LO alarm. The same ranging applied to the APC DAC should be used here.
VLTXP =
Full Scale 255
( APC DAC
LTXP )
78
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register BEh: HBIAS
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
BEh
Fast-comparison DAC setting for high BIAS. Comparisons greater than VHBIAS, found on the MON1 pin, create a BIAS HI alarm. Full Scale VHBIAS = HBIAS 255
Table 02h, Register BFh: MAX BIAS
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 212 BIT 7 211 00h PW2 PW2 Nonvolatile (SEE) 210 29 28 27 26 25 BIT 0
BFh
This value defines the maximum DAC value allowed for the upper 8 bits of BIAS output during all operations.
______________________________________________________________________________________
79
PON Triplexer and SFP Controller DS1875
Table 02h, Register C0h: DPU
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
C0h
INV M3QT BIT 7
MUX M3QT
INV LOS
MUX LOS
D3 CNTL
D2 CNTL
D1 CNTL
D0 CNTL BIT 0
BIT 7
INV M3QT: Inverts the internal M3QT signal to output pin D2 if MUX M3QT is set. If MUX M3QT is not set, this bit's value is a don't care. 0 = (Default) Noninverted M3QT to D2 pin. 1 = Inverted M3QT to D2 pin. MUX M3QT: Chooses the control for D2 output pin. 0 = (Default) D2 is controlled by bit D2 IN found in byte 79h. 1 = M3QT is buffered to D2 pin. INV LOS: Inverts the buffered input pin LOSI to output pin D0 if MUX LOS is set. If MUX LOS is not set, this bit's value is a don't care. 0 = (Default) Noninverted LOSI to D0 pin. 1 = Inverted LOSI to D0 pin. MUX LOS: Chooses the control for D0 output pin. 0 = (Default) DO is controlled by bit D0 IN found in byte 79h. 1 = LOSI is buffered to D0 pin. D3 CNTL: At power-on, this bit's value is loaded into bit D3 OUT of byte 78h to control the output pin D3. 0 = (Default) D2 CNTL: At power-on, this bit's value is loaded into bit D2 OUT of byte 78h to control the output pin D2. 0 = (Default) D1 CNTL: At power-on, this bit's value is loaded into bit D1 OUT of byte 78h to control the output pin D1. 0 = (Default) D0 CNTL: At power-on, this bit's value is loaded into bit D0 OUT of byte 78h to control the output pin D0. 0 = (Default)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin.
80
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register C1h to C2h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C3h: M3QT DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 Register to control M3QT DAC. 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
C3h
VM3QT =
1.25 256
(M3QT DAC + 1)
Table 02h, Register C4h: DAC1
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 Register to control DAC1. 26 00h PW2 PW2 Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0
C4h
VDACI =
2.5 256
(DAC1+ 1)
______________________________________________________________________________________
81
PON Triplexer and SFP Controller DS1875
Table 02h, Register C5h to C6h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C7h: M4 LUT CNTL
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
C7h
RESERVED BIT 7
RESERVED
RESERVED
RESERVED
FBOL
FBCL
DBL_SB
UP_LOWB BIT 0
BITS 7:4
RESERVED (Default = 000000b) FBOL and FBCL: Force bias open loop and force bias closed loop. 00b = (Default) normal operation. 10b = Force control of IBIAS to be open loop regardless of duration of BEN pulses. 01b = Force control of IBIAS to be closed loop regardless of duration of BEN pulses. 11b = Same as 10b. When forcing open-loop mode, BEN should be ground or at any burst length. DBL_SB: Chooses the size of LUT for Table 06h. 0 = (Default) Single LUT of 32 bytes. 1 = Double LUT of 16 bytes. UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of this bit is a don't care. 0 = (Default) Chooses the lower 16 bytes of Table 06h (80h to 8Fh). 1 = Chooses the upper 16 bytes of Table 06h (90h to 9Fh).
BITS 3:2
BIT 1
BIT 0
Controls the size and location of LUT functions for the MON4 measurement.
82
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register C8h to C9h: MON5 SCALE Table 02h, Register CAh to CBh: MON6 SCALE Table 02h, Register CCh to CDh: MON7 SCALE Table 02h, Register CEh to CFh: MON8 SCALE
FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE C8h, CAh, CCh, CEh C9h, CBh, CDh, CFh PW2 PW2 Nonvolatile (SEE)
215 27 BIT 7
214 26
213 25
212 24
211 23
210 22
29 21
28 20 BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS voltage of 2.5V for MON5, MON6, MON7, and MON8.
Table 02h, Register D0h to D1h: MON5 OFFSET Table 02h, Register D2h to D3h: MON6 OFFSET Table 02h, Register D4h to D5h: MON7 OFFSET Table 02h, Register D6h to D7h: MON8 OFFSET
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE D0h, D2h, D4h, D6h D1h, D3h, D5h, D7h 00h PW2 PW2 Nonvolatile (SEE)
S 29 BIT 7
S 28
215 27
214 26
213 25
212 24
211 23
210 22 BIT 0
Allows for offset control of these voltage measurements if desired.
______________________________________________________________________________________
83
PON Triplexer and SFP Controller DS1875
Table 02h, Register D8h to F7h: EMPTY Table 02h, Register F8h to F9h: MAN BIAS
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 and BIAS EN = 1 Volatile 212 25 211 24 210 23 29 22 28 21 27 20 BIT 0
F8h F9h
RESERVED 27 BIT 7
RESERVED 26
When BIAS EN (Table 02h, Register 80h) is written to 0, writes to these bytes control the BIAS DAC.
Table 02h, Register FAh: MAN_CNTL
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 and BIAS EN = 1 Volatile
FAh
RESERVED BIT 7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MAN_CLK BIT 0
When BIAS EN (Table 02h, Register 80h) is written to 0, bit 0 of this byte controls the updates of the MAN BIAS value to the BIAS output. The values of MAN BIAS should be written with a separate write command. Setting bit 0 to a 1 clocks the MAN BIAS value to the output DAC. 1. Write the MAN BIAS value with a write command. 2. Set the MAN_CLK bit to a 1 with a separate write command. 3. Clear the MAN_CLK bit to a 0 with a separate write command.
84
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 02h, Register FBh to FCh: BIAS DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 8000h PW2 N/A Volatile 212 25 211 24 210 23 29 22 28 21 27 20 BIT 0
FBh FCh
BOL 27 BIT 7
0 26
The bias open-loop bit (BOL) reflects the status of the BIAS current-control loop. If it is 1, the loop is open and the DS1875 is controlling the BIAS output from the LUT. If it is 0, the loop is closed and the BIAS output is controlled by active feedback from the BMD pin. The remaining bits are the digital value used for the BIAS output regardless of the value of OL.
Table 02h, Register FDh: BIAS OL
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and APC EN = 1 Volatile 25 24 23 22 21 20 BIT 0
FDh
The digital value used for BIAS at power-on and during open loop. It is recalled from Table 08h at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. The correct value depends on the value of BOLFS (Table 02h, Register 89h, bit 3). If BOLFS = 0, BIAS OL[7:0] = IBIAS[11:4]. If BOLFS = 1, BIAS OL[7:0] = IBIAS [12:5].
______________________________________________________________________________________
85
PON Triplexer and SFP Controller DS1875
Table 02h, Register FEh: PWM DAC
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 and PWM EN = 0 Volatile 25 24 23 22 21 20 BIT 0
FEh
The digital value used for PWM integration of the FB pin. It is recalled from Table 07h at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
VPWM =
1.25 256
(PWM DAC + 1)
Table 02h, Register FFh: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE This register is reserved. 00h PW2 N/A N/A
86
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 03h Register Descriptions
Table 03h, Register 80h to FFh: PW2 EEPROM
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (EE)
80h to FFh
EE BIT 7
EE
EE
EE
EE
EE
EE
EE BIT 0
PW2-protected EEPROM.
Table 04h Register Descriptions
Table 04h, Register 80h to C7h: MODULATION LUT
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to C7h
The digital value for the modulation DAC output. The MODULATION LUT is a set of registers assigned to hold the temperature profile for the modulation DAC. The values in this table combined with the MOD bits in the MOD RANGING register (Table 02h, Register 8Bh) determine the set point for the modulation voltage. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2C increments from -40C to +102C, starting at 80h in Table 04h. Register 80h defines the -40C to -38C MOD output, Register 81h defines the -38C to -36C MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD DAC (Table 02h, Register 82h) location that holds the value until the next temperature conversion. The DS1875 can be placed into a manual mode (MOD EN bit, Table 02h, Register 80h), where MOD DAC is directly controlled for calibration. If the temperature compensation functionality is not required, then program the entire Table 04h, to the desired modulation setting.
______________________________________________________________________________________
87
PON Triplexer and SFP Controller DS1875
Table 05h Register Descriptions
Table 05h, Register 80h to A3h: APC TE LUT
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to A3h
The APC TE LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC. The values in this table combined with the APC bits in the COMP RANGING register (Table 02h, Register 8Dh) determine the set point for the APC loop. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 4C increments from -40C to +100C, starting at Register 80h in Table 05h. Register 80h defines the -40C to -36C APC reference value, Register 81h defines the -36C to -32C APC reference value, and so on. Values recalled from this EEPROM memory table are written into the APC DAC (Table 02h, Register 83h) location that holds the value until the next temperature conversion. The DS1875 can be placed into a manual mode (APC EN bit, Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If TE temperature compensation is not required by the application, program the entire LUT to the desired APC set point.
Table 05h, Register A4h to A7h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (EE)
These registers are reserved.
88
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 06h Register Descriptions
Table 06h, Register 80h to 9Fh: M4DAC LUT
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to 9Fh
The M4DAC LUT is set of registers assigned to hold the voltage profile for the M4DAC. The values in this table determine the set point for the M4DAC. The MON4 voltage measurement is used to index the LUT (VINDEX, Table 02h, Register 84h), starting at Register 80h in Table 06h. Values recalled from this EEPROM memory table are written into the M4DAC (Table 02h, Register 85h) location that holds the value until the next MON4 voltage conversion. The DS1875 can be placed into a manual mode (M4DAC EN bit, Table 02h, Register 80h), where M4DAC is directly controlled for calibration. If voltage compensation is not required by the application, program the entire LUT to the desired M4DAC set point.
______________________________________________________________________________________
89
PON Triplexer and SFP Controller DS1875
Table 07h Register Descriptions
Table 07h, Register 80h to A3h: PWM REFERENCE LUT
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h PW2 PW2 Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to A3h
The PWM REFERENCE LUT is a set of registers assigned to hold the temperature profile for the PWM feedback. The values in this table determine the set point for the PWM loop. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 4C increments from -40C to +100C, starting at Register 80h in Table 07h. Register 80h defines the -40C to -36C PWM reference value, Register 81h defines the -36C to -32C PWM reference value, and so on. Values recalled from this EEPROM memory table are written into the PWM DAC (Table 02h, Register FEh) location that holds the value until the next temperature conversion. The DS1875 can be placed into a manual mode (PWM EN bit, Table 02h, Register 80h), where PWM DAC can be directly controlled for calibration. If temperature compensation is not required by the application, program the entire LUT to the desired PWM set point.
Table 07h, Register A4h to A7h: RESERVED
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE)
These registers are reserved.
90
______________________________________________________________________________________
PON Triplexer and SFP Controller DS1875
Table 08h Register Descriptions
Table 08h, Register 80h to C7h: BIAS OPEN-LOOP LUT
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h All All Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to C7h
The BIAS OPEN-LOOP LUT is a set of registers assigned to hold the temperature profile for the BIAS OL DAC. The values in this table determine the set point for the BIAS current. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2C increments from -40C to +102C, starting at 80h in Table 08h. Register 80h defines the -40C to -38C BIAS OL output, Register 81h defines the -38C to -36C BIAS OL output, and so on. Values recalled from this EEPROM memory table are written into the BIAS OL (Table 02h, Register FDh) location that holds the value until the next temperature conversion. The DS1875 can be placed into a manual mode (BIAS EN bit, Table 02h, Register 80h), where BIAS OL DAC is directly controlled for calibration. If the temperature compensation functionality is not required, then program the entire Table 08h to the desired BIAS OL setting.
Auxiliary Memory A0h Register Descriptions
Auxiliary Memory A0h, Register 00h to FFh: EEPROM
FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 27 BIT 7 26 00h ALL ALL Nonvolatile (EE) 25 24 23 22 21 20 BIT 0
80h to FFh
Accessible with the slave address A0h.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 38 TQFN-EP PACKAGE CODE T3857+1 DOCUMENT NO. 21-0172
______________________________________________________________________________________
91
PON Triplexer and SFP Controller DS1875
Revision History
REVISION NUMBER 0 1 REVISION DATE 7/08 10/08 Initial release. Updated all instances of the operating voltage range from 5.5V to 3.9V on multiple pages. DESCRIPTION PAGES CHANGED -- 1, 5-13
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
92 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of DS1875

	To Download DS1875 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .