View MC34712_4301766.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Advance Information
Document number: MC34712 Rev. 5.0, 12/2008
3.0 A 1.0 MHz Fully Integrated DDR Switch-Mode Power Supply
The 34712 is a highly integrated, space efficient, low cost, single synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with the ability to track an external reference voltage. Its high efficient 3.0 A sink and source capability combined with its voltage tracking/sequencing ability and tight output regulation, makes it ideal to provide the termination voltage (VTT) for modern data buses such as Double-Data-Rate (DDR) memory buses. It also provides a buffered output reference voltage (VREF) to the memory chipset The 34712 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. It is housed in a Pb-free, thermally enhanced, and space efficient 24 Pin Exposed Pad QFN. Features * 50 m integrated N-channel power MOSFETs * Input voltage operating range from 3.0 to 6.0 V * 1% Accurate output voltage, ranging from 0.7 to 1.35 V * 1% Accurate buffered reference output voltage * Programmable switching frequency range from 200 kHz to 1.0 MHz with a default of 1.0 MHz * Over-current limit and short-circuit protection * Thermal shutdown * Output over-voltage and under-voltage detection * Active low power good output signal * Active low standby and shutdown inputs * Pb-free packaging designated by suffix code EP.
VIN (3.0 TO 6.0 V)
34712
SWITCH-MODE POWER SUPPLY
EP SUFFIX 98ARL10577D 24-PIN QFN
ORDERING INFORMATION
Device MC34712EP/R2 Temperature Range (TA) -40 to 85C Package 24 QFN
34712
PVIN VDDQ VREFIN SW VIN VDDI FREQ GND SD VOUT VDDQ MEMORY BUS BOOT VTT TERMINATING RESISTORS
INV
COMP VREFOUT PGND PG VIN
DDR MEMORY CHIPSET VREF DDR MEMORY CONTROLER VDDQ
MCU
STBY
Figure 1. 34712 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-8. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
STBY
SD
Thermal Monitoring
PG
M1 System Reset Ilimit Isense Current Monitoring Discharge System Control
Internal Voltage Regulator M2 VDDI
VIN
BOOT
VBOOT
VIN
FREQ
Prog. Frequency
Oscillator Buck Control Logic FSW M3 Gate Driver Isense
PVIN SW PGND
M4
VDDI
VDDI
Bandgap Regulator VBG Ramp Generator
PWM Comparitor
COMP
+ -
COMP
Error Amplifier
VREFIN
RREF1 RREF2
+ -
INV
Buffer Discharge M6 Discharge
GND
VREFOUT
Figure 2. 34712 Simplified Internal Block Diagram
- +
M5
VOUT
34712
2
Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
BOOT
VDDI
PVIN
24
GND FREQ NC PG STBY SD
23
22
21
20
19 18 PVIN 17
SW SW SW
1 2 3 4 5 6 7
VREFIN Transparent Top View PIN 25
PVIN
VIN
VIN
16 15
14 PGND 13 8
VREFOUT PGND
9
COMP
10
INV
11
VOUT
12
PGND
Figure 3. 34712 Pin Connections Table 1. 34712 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12,13,14 15,16,17 18,19,20 21 Pin Name GND FREQ NC PG
STBY SD
Pin Function Ground Passive None Output Input Input Input Output Passive Input Output Ground Output Supply Passive
Formal Name Signal Ground Analog signal ground of IC
Definition
Frequency Adjustment Buck converter switching frequency adjustment pin No Connect Power Good Standby Shutdown Voltage Tracking Reference Input Reference Voltage Output Compensation Error Amplifier Inverting Input Output Voltage Discharge FET Power Ground Switching Node Power-circuit Supply Input Bootstrap No internal connections to this pin Active-low (open drain) power-good status reporting pin Standby mode input control pin Shutdown mode input control pin Voltage tracking reference voltage input Buffered output equal to 1/2 of voltage-tracking reference Buck converter external compensation network pin Buck converter error amplifier inverting input pin Discharge FET drain connection (connect to buck converter output capacitors) Ground return for buck converter and discharge FET Buck converter power switching node Buck converter main supply voltage input Bootstrap switching node (connect to bootstrap capacitor)
VREFIN VREFOUT
COMP
INV VOUT PGND SW PVIN BOOT
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34712 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 22,23 24 25 Pin Name
VIN
Pin Function Supply Passive Ground
Formal Name Logic-circuit Supply Input Internal Voltage Regulator Thermal Pad
Definition Logic circuits supply voltage input Internal VDD Regulator (connect filter capacitor to this pin) Thermal pad for heat transfer. Connect the thermal pad to the analog ground and the ground plane for heat sinking.
VDDI GND
34712
4
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Input Supply Voltage (VIN) Pin High Side MOSFET Drain Voltage (PVIN) Pin Switching Node (SW) Pin BOOT Pin (Referenced to SW Pin) PG, VOUT, SD, and STBY Pins VDDI, FREQ, INV, COMP, VREFIN, and VREFOUT Pins Continuous Output Current(1) ESD Voltage(2) Human Body Model Machine Model (MM) Device Charge Model (CDM) THERMAL RATINGS Operating Ambient Temperature(3) Storage Temperature Peak Package Reflow Temperature During Reflow(4),(5) Maximum Junction Temperature Power Dissipation (TA = 85 C)(6) Notes 1. Continuous output current capability so long as TJ is TJ(MAX). 2. 3. 4. 5. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Maximum power dissipation at indicated ambient temperature. TA TSTG TPPRT TJ(MAX) PD -40 to 85 -65 to +150 Note 5 +150 2.9 C C C C W VESD1 VESD2 VESD3 2000 200 750 V VIN PVIN VSW VBOOT - VSW IOUT -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 3.0 3.0 V V V V V V A Symbol Value Unit
6.
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RESISTANCE (7) Thermal Resistance, Junction to Ambient, Single-layer Board (1s)(8) Thermal Resistance, Junction to Ambient, Four-layer Board (2s2p) Thermal Resistance, Junction to Board
(10) (9)
Symbol
Value
Unit
RJA RJMA RJB
139 43 22
C/W C/W C/W
Notes 7. The PVIN, SW, and GND pins comprise the main heat conduction paths. 8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the board. 10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
34712
6
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic IC INPUT SUPPLY VOLTAGE (VIN) Input Supply Voltage Operating Range Input DC Supply Current(11) Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs Input DC Supply Current(11) Standby Mode, SD = 1 & STBY = 0 Input DC Supply Current(11) Shutdown Mode, SD = 0 & STBY = X INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI) Internal Supply Voltage Range BUCK CONVERTER (PVIN, SW, GND, BOOT, INV, COMP) High Side MOSFET Drain Voltage Range Output Voltage Adjustment Range Output Voltage Line
(12)
Symbol
Min
Typ
Max
Unit
VIN IIN IINQ IINOFF
3.0 -
-
6.0 25
V
mA
-
-
15
mA
-
-
100
A
VDDI
2.35
2.5
2.65
V
PVIN VOUT REGLN REGLD
2.5 0.7 -1.0 -1.0
-
6.0 1.35 1.0 1.0
V V % %
Accuracy(12),(13),(14)
Regulation(12)
Normal Operation, VIN = 3.0 to 6.0 V, IOUT = 3.0 A Load Regulation(12) Normal Operation, IOUT = -3.0 to 3.0 A Error Amplifier Common Mode Voltage Range(12),(15) Output Under-voltage Threshold Output Over-voltage Threshold Continuous Output Current Over-current Limit, Sinking and Sourcing Short-circuit Current Limit (Sourcing and Sinking) High Side N-CH Power MOSFET (M3) RDS(ON)(12) IOUT = 1.0 A, VBOOT - VSW = 3.3 V Low Side N-CH Power MOSFET (M4) RDS(ON)(12) IOUT = 1.0 A, VIN = 3.3 V Notes 11. 12. 13. 14. 15.
-1.0 0.0 -8.0 1.5 -3.0 -
4.0 6.5
1.0 1.35 -1.5 8.0 3.0 -
% V % % A A A
VREF
VUVR VOVR IOUT ILIM ISHORT RDS(ON)HS RDS(ON)LS
10
-
50
m
10
-
50
m
See section "MODES OF OPERATION", page 14 has a detailed description of the different operating modes of the 34712 Design information only, this parameter is not production tested. 1% is assured at room temperature. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended. The 1% output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7 V at room temperature.
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic M2 RDS(ON) (VIN = 3.3 V, M2 is on) SW Leakage Current (Standby and Shutdown modes) PVIN Pin Leakage Current (Standby and Shutdown Modes) INV Pin Leakage Current Error Amplifier DC Gain
(16)
Symbol RDS(ON)M2 ISW IPVIN IINV AEA UGBWEA SREA OFFSETEA TSDFET TSDHYFET
Min 1.5 -10 -10 -1.0 -3.0 -
Typ 150 3.0 7.0 0 170 25
Max 4.0 10 10 1.0 3.0 -
Unit A A A dB MHz V/s mV C C
Error Amplifier Unit Gain
Bandwidth(16)
(16) (16)
Error Amplifier Slew Rate
Error Amplifier Input Offset Thermal Shutdown
Threshold(16)
(16)
Thermal Shutdown Hysteresis OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range TRACKING (VREFIN, VREFOUT, VOUT) VREFIN External Reference Voltage Range(16) VREFOUT Buffered Reference Voltage Range VREFOUT Buffered Reference Voltage Accuracy(17)
VFREQ
0.0
-
VDDI
V
VREFIN VREFOUT IREFOUT IREFOUTLIM RTDR(M6) RTDR(M5) IVOUTLKG
0.0 0.0 -1.0 0.0 -1.0
11 50 50 -
2.7 1.35 1.0 8.0 1.0
V V % mA mA A
VREFOUT Buffered Reference Voltage Current Capability VREFOUT Buffered Reference Voltage Over-current Limit VREFOUT Total Discharge Resistance(16)
(16)
VOUT Total Discharge Resistance VOUT Pin Leakage Current (Standby Mode, VOUT = 3.6 V)
CONTROL AND SUPERVISORY (STBY, SD, PG) STBY High Level Input Voltage STBY Low Level Input Voltage STBY Pin Internal Pull-up Resistor SD High Level Input Voltage SD Low Level Input Voltage SD Pin Internal Pull-up Resistor PG Low Level Output Voltage (IPG = 3.0 mA) PG Pin Leakage Current (M1 is off, Pulled up to VIN) IPGLKG -1.0 1.0 A VPGLO 0.4 V VSTBYHI VSTBYLO RSTBYUP VSDHI VSDLO RSDUP 2.0 1.0 2.0 1.0 0.4 2.0 0.4 2.0 V V M V V M
Notes 16. Design information only, this parameter is not production tested. 17. The 1 % accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature.
34712
8
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic BUCK CONVERTER (PVIN, SW, GND, BOOT) Switching Node (SW) Rise Time(19) (PVIN = 3.3 V, IOUT = 3.0 A) Switching Node (SW) Fall Time(19) (PVIN = 3.3 V, IOUT = 3.0 A) Minimum OFF Time Minimum ON Time Soft Start Duration (Normal Mode) Over-current Limit Timer Over-current Limit Retry Timeout Period Output Under-voltage/Over-voltage Filter Delay Timer OSCILLATOR (FREQ) Oscillator Default Switching Frequency(18) (FREQ = GND) Oscillator Switching Frequency Range CONTROL AND SUPERVISORY (STBY, SD, PG) PG Reset Delay Thermal Shutdown Retry Time-out Period(19) Notes 18. Oscillator Frequency tolerance is 10%. 19. Design information only, this parameter is not production tested. tPGRESET tTIMEOUT 8.0 80 12 120 ms ms FSW FSW 200 1.0 1000 MHz kHz tSS tLIM tTIMEOUT tFILTER 1.3 80 5.0 10 2.6 120 25 ms ms ms s tFALL tOFFMIN tONMIN 20 150 100 ns ns ns tRISE 14 ns Symbol Min Typ Max Unit
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
In modern microprocessor/memory applications, address commands and control lines require system level termination to a voltage (VTT) equal to 1/2 the memory supply voltage (VDDQ). Having the termination voltage at midpoint, the power supply insures symmetry for switching times. Also, a reference voltage (VREF) that is free of any noise or voltage variations is needed for the DDR SDRAM input receiver, VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will effect the setup and hold time of the memory. To comply with DDR requirements and to obtain best performance, VTT and VREF need to be tightly regulated to track 1/2 VDDQ across voltage, temperature, and noise margins. VTT should track any variations in the DC VREF value (VTT = VREF +/- 40mV), (See Figure 4) for a DDR system level diagram. The 34712 supplies the VTT and a buffered VREF output. To ensure compliance with DDR specifications, the VDDQ line is applied to the VREFIN pin and divided by 2 internally through a precision resistor divider. This internal voltage is then used as the reference voltage for the VTT output. The same internal voltage is also buffered to give the VREF voltage at the VREFOUT pin for the application to use without the need for an external resistor divider. The 34712 provides the tight voltage regulation and power sequencing/tracking required along with handling the DDR peak transient current requirements. Buffering the VREF output helps its immunity against noise and load changes. The 34712 utilizes a voltage mode synchronous buck switching converter topology with integrated low RDS(ON) (50 m) N-channel power MOSFETs to provide a VTT voltage with an accuracy of less than 2.0%. It has a programmable switching frequency that allows for flexibility and optimization over the operating conditions and can operate at up to 1.0 MHz to significantly reduce the external components size and cost. The 34712 can sink and source up to 3.0 A of continuous current. It provides protection against output over-current, over-voltage, under-voltage, and overtemperature conditions. It also protects the system from short circuit events. It incorporates a power-good output signal to alert the host when a fault occurs. For boards that support the Suspend-To-RAM (S3) and the Suspend-To-Disk (S5) states, the 34712 offers the STBY and the SD pins respectively. Pulling any of these pins low, puts the IC in the corresponding state. By integrating the control/supervisory circuitry along with the Power MOSFET switches for the buck converter into a space-efficient package, the 34712 offers a complete, smallsize, cost-effective, and simple solution to satisfy the needs of DDR memory applications. Besides DDR memory termination, the 34712 can be used to supply termination for other active buses and graphics card memory. It can be used in Netcom/Telecom applications like servers. It can also be used in desktop motherboards, game consoles, set top boxes, and high end high definition TVs.
VDDQ
VTT
VDDQ
RS
BUS
RT VREF
DDR Memory Controller
DDR Memory Input Receiver
Figure 4. DDR System Level Diagram
FUNCTIONAL PIN DESCRIPTION REFERENCE VOLTAGE INPUT (VREFIN)
The 34712 will track 1/2 the voltage applied at this pin.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converter switching frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and GND pins. The default switching frequency (FREQ pin connected to ground, GND) is set at 1.0 MHz.
REFERENCE VOLTAGE OUTPUT (VREFOUT)
This is a buffered reference voltage output that is equal to 1/2 VREFIN. It has a 10 mA current drive capability. This output is used as the VREF voltage rail and should be filtered against any noise. Connect a 0.1 F, 6.0 V low ESR ceramic filter capacitor between this pin and the GND pin and between this pin and VDDQ rail. VREFOUT is also used as the reference voltage for the buck converter error amplifier.
SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are referenced to this pin voltage.
34712
10
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
This is the output of the internal bias voltage regulator. Connect a 1.0 F, 6.0 V low ESR ceramic filter capacitor between this pin and the GND pin. Filtering any spikes on this output is essential to the internal circuitry stable operation.
POWER INPUT VOLTAGE (PVIN)
Buck converter power input voltage. This is the drain of the buck converter high side power MOSFET.
BOOTSTRAP INPUT (BOOT)
Bootstrap capacitor input pin. Connect a capacitor (as discussed on page 19) between this pin and the SW pin to enhance the gate of the high side Power MOSFET during switching.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT)
Output voltage of the Buck Converter is connected to this pin. it only serves as the output discharge path once the SD signal is asserted.
SHUTDOWN INPUT (SD) ERROR AMPLIFIER INVERTING INPUT (INV)
Buck converter error amplifier inverting input. Connect the VTT voltage directly to this pin. If this pin is tied to the GND pin, the device will be in Shutdown mode. If left unconnected or tied to the VIN pin, the device will be in Normal mode. The pin has an internal pullup of 1.5 M. This input accepts the S5 (Suspend-To-Disk) control signal.
COMPENSATION INPUT (COMP)
Buck converter external compensation network connects to this pin. Use a type III compensation network.
STANDBY INPUT (STBY)
If this pin is tied to the GND pin, the device will be in Standby mode. If left unconnected or tied to the VIN pin, the device will be in Normal mode. The pin has an internal pullup of 1.5 M. This input accepts the S3 (Suspend-To-RAM) control signal.
INPUT SUPPLY VOLTAGE (VIN)
IC power supply input voltage. Input filtering is required for the device to operate properly.
POWER GROUND (PGND)
Buck converter and discharge MOSFETs power ground. It is the source of the buck converter low side power MOSFET.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to report the status of the device to a host. This output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. This output activates after a 10 ms delay and must be pulled up by an external resistor to a supply voltage (e.g.,VIN.).
SWITCHING NODE (SW)
Buck converter switching node. This pin is connected to the output inductor.
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34712 - Functional Block Diagram
Internal Bias Circuits
System Control and Logic
Oscillator
Protection Functions
Control and Supervisory Functions
Tracking and Sequencing
Buck Converter
Figure 5. 34712 Internal Block Diagram
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary supply voltages and bias currents for the internal circuitry. It consists of: * Internal voltage supply regulator: This regulator supplies the VDDI voltage that is used to drive the digital/ analog internal circuits. It is equipped with a Power-OnReset (POR) circuit that watches for the right regulation levels. External filtering is needed on the VDDI pin. This block will turn off during the shutdown mode. * Internal bandgap reference voltage: This supplies the reference voltage to some of the internal circuitry. * Bias circuit: This block generates the bias currents necessary to run all of the blocks in the IC.
resistor divider to the FREQ pin, between VDDI and GND pins (See Figure 1).
PROTECTION FUNCTIONS
This block contains the following circuits: * Over-current limit and short-circuit detection: This block monitors the output of the buck converter for over current conditions and short circuit events and alerts the system control for further command. * Thermal limit detection: This block monitors the temperature of the device for overheating events. If the temperature rises above the thermal shutdown threshold, this block will alert the system control for further commands. * Output over-voltage and under-voltage monitoring: This block monitors the buck converter output voltage to ensure it is within regulation boundaries. If not, this block alerts the system control for further commands.
SYSTEM CONTROL AND LOGIC
This block is the brain of the IC where the device processes data and reacts to it. Based on the status of the STBY and SD pins, the system control reacts accordingly and orders the device into the right status. It also takes inputs from all of the monitoring/protection circuits and initiates power up or power down commands. It communicates with the buck converter to manage the switching operation and protects it against any faults.
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It contains the following circuits: * Standby control input: An outside host can put the 34712 device into standby mode (S3 or Suspend-ToRAM mode) by sending a logic "0" to the STBY pin. * Shutdown control input: An outside host can put the 34712 device into shutdown mode (S5 or Suspend-ToDisk mode) by sending a logic "0" to the SD pin. * Power good output signal PG: The 34712 can communicate to an external host that a fault has
OSCILLATOR
This block generates the clock cycles necessary to run the IC digital blocks. It also generates the buck converter switching frequency. The switching frequency has a default value of 1.0 MHz and can be programmed by connecting a
34712
12
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
occurred by releasing the drive on the PG pin high, allowing the signal/pin to be pulled high by the external pull-up resistor.
TRACKING AND SEQUENCING
This block allows the output of the 34712 to track 1/2 the voltage applied at the VREFIN pin. This allows the VREF and VTT voltages to track 1/2 VDDQ and assures that none of them will be higher than VDDQ at any point during normal operating conditions. For power down during a shutdown (S5) mode, the 34712 uses internal discharge MOSFETs (M5 and M6 on Figure 2) to discharge VTT and VREF respectively. These discharge MOSFETs are only active during shutdown mode. Using this block along with controlling the SD and STBY pins can offer the user power sequencing capabilities by controlling when to turn the 34712 outputs on or off.
BUCK CONVERTER
This block provides the main function of the 34712: DC to DC conversion from an un-regulated input voltage to a
regulated output voltage used by the loads for reliable operation. The buck converter is a high performance, fixed frequency (externally adjustable), synchronous buck PWM voltage-mode control. It drives integrated 50 m N-channel power MOSFETs saving board space and enhancing efficiency. The switching regulator output voltage is adjustable with an accuracy of less than 2.0% to meet DDR requirements. Its output has the ability to track 1/2 the voltage applied at the VREFIN pin. The regulator's voltage control loop is compensated using a type III compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. A typical Bootstrap circuit with an internal PMOS switch is used to provide the voltage necessary to properly enhance the high-side MOSFET gate. The 34712 is designed to address DDR memory power supplies. The integrated converter has the ability to both sink and source up to 3.0 A of continuous current, making it suitable for bus termination power supplies.
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SD = 0 & STBY=x Shutdown VTT = Discharge VREF = Discharge PG = 1 SD = 1 & STBY=1
VIN < 3.0 V Power Off VTT=OFF VREF=OFF PG = 1 3.0 V<=VIN<=6.0 V SD = 1 & STBY=1
SD = 1 & STBY=0 Standby VTT = OFF VREF = ON PG = 1
IOUT>=ISHORT VTT>VOV Over-voltage VTT=ON VREF=ON PG = 1 Normal VTT = ON VREF=ON PG = 0 TIMEOUT Expired Short-circuit VTT=OFF VREF=OFF PG = 1
VTTVTT>VUV Under-voltage VTT=ON VREF=ON VTT= 170C
TJ<=145C TIMEOUT Expired Thermal Shutdown VTT=OFF VREF=OFF PG = 1
TIMEOUT Expired Over-current VTT=OFF VREF=ON PG = 1
IOUT1>=ILIM1 For>=10 ms
Figure 6. Operation Modes Diagram
MODES OF OPERATION
The 34712 has three primary modes of operation: Normal Mode In normal mode, all functions and outputs are fully operational. To be in this mode, the VIN needs to be within its operating range, both Shutdown and Standby inputs are high, and no faults are present. This mode consumes the most amount of power. Standby Mode This mode is predominantly used in Desktop memory solutions where the DDR supply is desired to be ACPI compliant (Advanced Configuration and Power Interface). When this mode is activated by pulling the STBY pin low, VTT is put in High Z state, IOUT = 0 A, and VREF stays active. This is the S3 state Suspend-To-Ram or Self Refresh mode and it is the lowest DRAM power state. In this mode, the DRAM will preserve the data. While in this mode, the 34712 consumes less power than in the normal mode, because the buck converter and most of the internal blocks are disabled.
Shutdown Mode In this mode, activated by pulling the SD pin low, the chip is in a shutdown state and the outputs are all disabled and discharged. This is the S4/S5 power state or Suspend-ToDisk state, where the DRAM will loose all of its data content (no power supplied to the DRAM). The reason to discharge the VTT and VREF lines is to ensure upon exiting, the Shutdown Mode that VTT and VREF are lower than VDDQ, otherwise VTT can remain floating high, and be higher than VDDQ upon powering up. In this mode, the 34712 consumes the least amount of power since almost all of the internal blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34712 checks the status of the SD and STBY pins. If the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. If the device is in a standby mode, only the VDDI internal supply voltage and the bias currents are established and no further activities will occur. Once the SD and STBY pins are released to enable the device, the internal VDDI POR signal is also released. The rest of the internal blocks will be enabled
34712
14
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
and the buck converter switching frequency value is determined by reading the FREQ pin. A soft start cycle is then initiated to ramp up the output of the buck converter (VTT). The buck converter error amplifier uses the voltage on the VREFOUT pin (VREF) as its reference voltage. VREF is equal to 1/2 VDDQ, where VDDQ is applied to the VREFIN pin. This way, the 34712 assures that VREF and VTT voltages track 1/2 VDDQ to meet DDR requirements. Soft start is used to prevent the output voltage from overshooting during startup. At initial startup, the output capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage across the inductor will be PVIN during the capacitor charge phase which will create a very sharp di/dt ramp. Allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load current that can result in an undesired voltage spike once the capacitor is fully charged. The soft start is active each time
the IC goes out of standby or shutdown mode, power is recycled, or after a fault retry. To fully take advantage of soft starting, it is recommended not to enable the 34712 output before introducing VDDQ on the VREFIN pin. If this happens after a soft start cycle expires and the VREFIN voltage has a high dv/dt, the output will naturally track it immediately and ramp up with a fast dv/dt itself and that will defeat the purpose of soft starting. For reliable operation, it is best to have the VDDQ voltage available before enabling the output of the 34712. After a successful start-up cycle where the device is enabled, no faults have occurred, and the output voltage has reached its regulation point, the 34712 pulls the power good output signal low after a 10ms reset delay, to indicate to the host that the device is in normal operation.
PROTECTION AND DIAGNOSTIC FEATURES
The 34712 monitors the application for several fault conditions to protect the load from overstress. The reaction of the IC to these faults ranges from turning off the outputs to just alerting the host that something is wrong. In the following paragraphs, each fault condition is explained: Output Over-voltage An over-voltage condition occurs once the output voltage goes higher than the rising over-voltage threshold (VOVR). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the VTT and VREF outputs will stay active. To avoid erroneous over-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage falls below the falling over-voltage threshold (VOVF), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. Output Under-voltage An under-voltage condition occurs once the output voltage falls below the falling under-voltage threshold (VUVF). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the VTT and VREF outputs will stay active. To avoid erroneous under-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage rises above the rising under-voltage threshold (VUVR), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. Output Over-current This block detects over-current in the Power MOSFETs of the buck converter. It is comprised of a sense MOSFET and a comparator. The sense MOSFET acts as a current detecting device by sampling a ratio of the load current. That sample is compared via the comparator with an internal reference to determine if the output is in over-current or not. If the peak current in the output inductor reaches the over current limit (ILIM), the converter will start a cycle-by-cycle operation to limit the current, and a 10 ms over-current limit timer (tLIM) starts. The converter will stay in this mode of operation until one of the following occurs: * The current is reduced back to the normal level before tLIM expires, and in this case normal operation is regained. * tLIM expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. At the end of a timeout period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. * The device reaches the thermal shutdown limit (TSDFET) and turns off the output. The power good output signal is pulled high. Short-circuit Current Limit This block uses the same current detection mechanism as the over-current limit detection block. If the load current reaches the ISHORT value, the device reacts by shutting down the output immediately. This is necessary to prevent damage in case of a permanent short circuit. Then, at the end of a timeout period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. Thermal Shutdown Thermal limit detection block monitors the temperature of the device and protects against excessive heating. If the temperature reaches the thermal shutdown threshold (TSDFET), the converter output switches off and the power good output signal indicates a fault by pulling high. The device will stay in this state until the temperature has decreased by the hysteresis value and then After a timeout period (TTIMEOUT) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. If successful normal operation is regained, the power good output signal is asserted low to indicate that.
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
15
TYPICAL APPLICATIONS PROTECTION AND DIAGNOSTIC FEATURES
TYPICAL APPLICATIONS
Compensation Network
VOUT
INV C18 0.02 pF R15 15 k C19 1.9 nF R14 300 R2 12.7 k_nopop
VIN VDDI R12 10 k_nopop FREQ
BOOT C15 0.1 F SW PVIN PVIN
C14 0.1 F 1 2 x 3 4 5 6
24 VDDI
23 VIN
22 VIN
21 BOOT
20 PVIN
19 PVIN 18 17 16 15 14 13 SW SW
COMP
C20 1.0 nF
R1 20 k
R11 10 k
SGND FREQ NC
PVIN SW SW
MC34712
PG STBY VREFOUT VREFIN COMP VOUT SD SW GND GND GND
PG
VMASTER
VMASTER R8 10 k_nopop VREFIN R9 10 k_nopop
PGOOD LED
VIN R7 1k
STBY SD
GND
7 VREFIN C13 0.1 F
8
9
10 INV
INV
11
12
D1 LED LED
COMP C12 0.1 F
C11 0.1 F VOUT
VREFOUT
VIN Capacitors
VIN C17 10 F C16 0.1 F
I/O Signals
4.7_nopop PVIN VIN GND R16 J2 3 2 1 J3
Jumpers
PVIN VMASTER STBY_nopop LED 1 2 1 SD 2 CON10A 1 3 5 7 9 J1 2 4 6 8 10 VREFIN PG STBY SD
Optional nopop
VDDI
GND VMASTER VOUT
3 2 1
FREQ R6 POT_50 k_nopop
Buck Converter
SW D3 PMEG2010EA _nopop L1 1.5 H VOUT R3 4.7_nopop C7 C6 C8 C9 100 F 100 F 100 F 1 nF_nopop VOUT2 VOUT1
PVIN Capacitors
PVIN
C1 0.1 F
C2 1.0 F
C3 C4 C5 100 F 100 F 100 F
34712
16
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS PROTECTION AND DIAGNOSTIC FEATURES
COMPONENT SELECTION
SWITCHING FREQUENCY SELECTION The switching frequency defaults to a value of 1.0 MHz when the FREQ pin is grounded, and 200 kHz when the FREQ pin is connected to VDDI. Intermediate switching frequencies can be obtained by connecting an external resistor divider to the FREQ pin. The table below shows the resulting switching frequency versus FREQ pin voltage. Table 5. Switching Frequency Adjustment
FREQUENCY 200 253 307 360 413 466 520 573 627 680 733 787 840 893 947 1000 VOLTAGE APPLIED TO PIN FREQ 2.341 - 2.500 2.185 - 2.340 2.029 - 2.184 1.873 - 2.028 1.717 - 1.872 1.561 - 1.716 1.405 - 1.560 1.249 - 1.404 1.093 - 1.248 0.936 - 1.092 0.781 - 0.936 0.625 - 0.780 0.469 - 0.624 0.313 - 0.468 0.157 - 0.312 0.000 - 0.156
SELECTION OF THE INDUCTOR
Inductor calculation is straight forward, being
where,
Maximum OFF time percentage
Switching period.
Drain - to - source resistance of FET
Winding resistance of Inductor
Output current ripple.
OUTPUT FILTER CAPACITOR
For the output capacitor, the following considerations are more important than the actual capacitance value, the physical size, the ESR and the voltage rating: Transient Response percentage, TR_% (Use a recommended value of 2 to 4% to assure a good transient response.) Maximum Transient Voltage, TR_v_dip = Vo*TR_% Maximum current step,
RFQH RFQL
VDDI FREQ
Inductor Current rise time,
GND
Figure 7. Resistor Divider for Frequency Adjustment
where, D_max = Maximum ON time percentage. IO = Rated output current. Vin_min = Minimum input voltage at PVIN
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
17
TYPICAL APPLICATIONS PROTECTION AND DIAGNOSTIC FEATURES
As a result, it is possible to calculate
FSW
PWM Comparitor Gate Driver
SW L VOUT Error Amplifier
+ -
In order to find the maximum allowed ESR,
Ramp Generator
-
RS
INV
RO CO
VREFOUT
CS RF CX
+
COMP
CF
The effects of the ESR is often neglected by the designers and may present a hidden danger to the ultimate supply stability. Poor quality capacitors have widely disparate ESR value, which can make the closed loop response inconsistent.
34712
Figure 9. Type III Compensation Network Consider the crossover frequency, FCROSS, of the open loop gain at one-tenth of the switching frequency, FSW.
Io
Then,
Io_step
10 F CROSS = ---------------------------2 * R O C F
Current response
10 C F = -------------------------------------2 * R O F CROSS
where RO is a user selected resistor. Knowing the LC frequency, it can be obtained the values of RF and CS:
dt_I_rise
Worst case assumption
Figure 8. Transient Parameters
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight regulation output voltages. To accomplish this requires a high DC gain. But with high gain comes the possibility of instability. The purpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the control-to-output transfer function that could jeopardized the stability of the power supply. The Type III compensation network used for 34712 comprises two poles (one integrator and one high frequency pole to cancel the zero generated from the ESR of the output capacitor) and two zeros to cancel the two poles generated from the LC filter as shown in Figure 9.
This gives as a result,
&
Calculate Rs by placing the Pole 1 at the ESR zero frequency:
34712
18
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS PROTECTION AND DIAGNOSTIC FEATURES
stay enhanced. A 0.1 F capacitor is a good value for this bootstrap element.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful consideration. First, there are high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spikes they can create. To do this, an understanding of the major current carrying loops is important. See Figure 10. These loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. Also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. If sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction. Second, small signal components which connect to sensitive nodes need consideration. The critical small signal components are the ones associated with the feedback circuit. The high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. Other critical small signal components include the bypass capacitors for VIN, VREFIN, and VDDI. Locate the bypass capacitors as close to the pin as possible. The use of a multi-layer printed circuit board is recommended. Dedicate one layer, usually the layer under the top layer, as a ground plane. Make all critical component ground connections with vias to this layer. Make sure that the power ground, PGND, is connected directly to the ground plane and not routed through the thermal pad or analog ground. Dedicate another layer as a power plane and split this plane into local areas for common voltage nets. The IC input supply (VIN) should be connected with a dedicated trace to the input supply. This will help prevent noise from the Buck Regulator's power input (PVIN) from injecting switching noise into the IC's analog circuitry. In order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. It is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm.
Equating the Pole 2 to 5 times the Crossover Frequency to achieve a faster response and a proper phase margin, 5 * F CROSS = F 1 ---------------------------------------P2 = CF CX 2 * R F -------------------CF + CX
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate voltage for the high side MOSFET. This N-Channel MOSFET needs a voltage difference between its gate and source to be able to turn on. The high side MOSFET source is the SW node, so it is not ground and it is floating and moving in voltage, so we cannot just apply a voltage directly to the gate of the high side that is referenced to ground, we need a voltage referenced to the SW node. That is why the bootstrap capacitor is needed for. This capacitor charges during the high side off time, since the low side will be on during that time, so the SW node and the bottom of the bootstrap capacitor will be connected to ground and the top of the capacitor will be connected to a voltage source, so the capacitor will charge up to that voltage source (say 5.0 V). Now when the low side MOSFET switches off and the high side MOSFET switches on, the SW nodes rises up to Vin, and the voltage on the boot pin will be Vcap + Vin. So the gate of the high side will have Vcap across it and it will be able to
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
19
TYPICAL APPLICATIONS PROTECTION AND DIAGNOSTIC FEATURES
VIN1
VIN2PVIN and 3 Loop Curr ent HS ON Loop Curr ent HS ON
HS SW1 SD
HS
SW SW2 and 3
Loop Current SD ON LS GND2 and 3 PGND BUCK CONVERTER 1 Loop Current LS ON
Buck Converter BUCK CONVERTER 2 and 3 Figure 10. Current Loops
34712
20
Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX 24 -PIN 98ARL10577D ISSUE B
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
21
PACKAGING PACKAGING DIMENSIONS
EP SUFFIX 24 -PIN 98ARL10577D ISSUE B
34712
22
Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 1.0 2.0
DATE 2/2006 11/2006
DESCRIPTION OF CHANGES * * * * * * * * * * * * * * * * * * * * * * * * * * * Pre-release version Implemented Revision History page Initial release Converted format from Market Assessment to Product Preview Major updates to the data, form, and style Replaced all electrolytic capacitors with ceramic ones in Figure 1 Deleted Deadtime in Dynamic Electrical Characteristics Moved Figures 8 ahead of TYPE III COMPENSATION NETWORK Changed Features fom 2% to 1% Changed 34712 Simplified Application Diagram Removed Machine Model in Maximum Ratings Added minimum limits to Input DC Supply Current(11) Normal mode, Input DC Supply Current(11) Standby mode, and Input DC Supply Current(11) Shutdown mode Added High Side MOSFET Drain Voltage Range Changed Output Voltage Accuracy(12),(13),(14) Changed Short-circuit Current Limit Changed High Side N-CH Power MOSFET (M3) RDS(ON)(12) and Low Side N-CH Power MOSFET (M4) RDS(ON)(12) Changed M2 RDS(ON) Changed PVIN Pin Leakage Current Changed VREFOUT Buffered Reference Voltage Accuracy(17), VREFOUT Buffered Reference Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over-current Limit Changed STBY Pin Internal Pull-up Resistor and SD Pin Internal Pull-up Resistor Changed Soft Start Duration, Over-current Limit Retry Timeout Period, and Output Under-voltage/ Over-voltage Filter Delay Timer Changed Oscillator Default Switching Frequency(18) Changed PG Reset Delay and Thermal Shutdown Retry Time-out Period(19) Changed drawings in Typical Applications Changed drawing in Type III Compensation Network Removed PC34712EP/R2 from the ordering information and added MC34712EP/R2 Changed the data sheet status to Advance Information Made changes to Switching Node (SW) Pin, BOOT Pin (Referenced to SW Pin), Output Undervoltage Threshold, Output Over-voltage Threshold, High Side N-CH Power MOSFET (M3) RDS(ON)(12), Low Side N-CH Power MOSFET (M4) RDS(ON)(12), Device Charge Model (CDM) Added Machine Model (MM), SW Leakage Current (Standby and Shutdown modes), Error Amplifier DC Gain(16), Error Amplifier Unit Gain Bandwidth(16), Error Amplifier Slew Rate(16), Error Amplifier Input Offset(16) Added pin 25 to Figure 3 and the 34712 Pin Definitions Added the section Layout Guidelines
3.0
2/2007
4.0
5/2007
5.0
12/2007
*
*
* *
34712
Analog Integrated Circuit Device Data Freescale Semiconductor
23
How to Reach Us:
Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should a Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007-8. All rights reserved.
MC34712 Rev. 5.0 12/2008

▲Up To Search▲

Price & Availability of MC34712

	To Download MC34712 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .