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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The MC54/74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. * * * * * * Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 162 FETs or 40.5 Equivalent Gates LOGIC DIAGRAM D0 3 D1 4 DATA INPUTS D2 6 D3 11 D4 13 14 D5 2 Q0 5 Q1 7 Q2 10 Q3 12 Q4 15 Q5 MC54/74HC174A J SUFFIX CERAMIC PACKAGE CASE 620-10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD Ceramic Plastic SOIC NONINVERTING OUTPUTS PIN ASSIGNMENT RESET Q0 D0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q5 D5 D4 Q4 D3 Q3 CLOCK CLOCK 9 PIN 16 = VCC PIN 8 = GND D1 Q1 D2 Q2 GND 10/95 (c) Motorola, Inc. 1995 IIIIIIIIIIIIII II III I I IIIIIIIIIIIIII I IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II III I II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIII II IIIIIIIIIIIIII II IIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIII II IIIIIIIIIIIIII II Design Criteria Value 40.5 1.5 5.0 Units ea. ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ .0075 * Equivalent to a two-input NAND gate. 1 REV 6 RESET 1 FUNCTION TABLE Inputs Reset L H H H H Clock X D X H L X X Output Q L H L No Change No Change L IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC174A Symbol Vin, Vout Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin PD TL VOH tr, tf Iin VOL TA VIH VIL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Vin = VIH or VIL |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions - 1.5 to VCC + 1.5 -0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0 2 - 55 Min 2.0 Value 0 0 0 0 50 25 20 260 300 750 500 + 125 1000 500 400 VCC Max 6.0 VCC V 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C ns V V V V V - 55 to 25_C 0.5 1.35 1.8 1.5 3.15 4.2 0.26 0.26 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 1.35 1.8 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 v 0.5 1.35 1.8 1.5 3.15 4.2 0.4 0.4 0.1 0.1 0.1 3.7 5.2 1.9 4.4 5.9 v Unit V V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I III I I I II I I I I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I III I I I II I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I CPD Power Dissipation Capacitance (Per Enabled Output)* pF 62 * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I NOTES: 1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + SICC. High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol Symbol tr, tf trec tsu tw tw th tPLH tPHL tPLH tPHL tTLH tTHL fmax ICC Cin Iin AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Maximum Input Rise and Fall Times Minimum Pulse Width, Reset Minimum Pulse Width, Clock Minimum Recovery Time, Reset Inactive to Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Reset to Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter Parameter Parameter Vin = VCC or GND Iout = 0 A Vin = VCC or GND Test Conditions Fig. 1 2 1 2 3 3 3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C Min 5.0 5.0 5.0 5.0 5.0 5.0 50 10 9.0 75 15 13 75 15 13 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 6.0 6.0 1000 500 400 Max - 55 to 25_C - 55 to 25_C Guaranteed Limit Typical @ 25C, VCC = 5.0 V 0.1 110 21 19 110 22 19 6.0 30 35 4.0 10 75 15 13 Min 5.0 5.0 5.0 5.0 5.0 5.0 95 19 16 95 19 16 65 13 11 v 85_C Guaranteed Limit Guaranteed Limit 1000 500 400 Max v 85_C v 125_C v 85_C v 125_C 1.0 140 28 24 140 28 24 4.8 24 28 10 95 19 16 40 MC54/74HC174A Min 110 22 19 110 22 19 5.0 5.0 5.0 5.0 5.0 5.0 75 15 13 v 125_C 1.0 160 32 27 165 33 28 160 110 22 19 4.0 20 24 10 1000 500 400 Max MOTOROLA MHz Unit Unit Unit A A pF ns ns ns ns ns ns ns ns ns MC54/74HC174A EXPANDED LOGIC DIAGRAM CLOCK D0 RESET 9 3 1 C D1 4 D R C D2 6 D Q R C D3 11 D R C D4 13 D R C D5 14 D Q R D C Q R 2 Q0 Q 5 Q1 7 Q2 Q 10 Q3 Q 12 Q4 15 Q5 SWITCHING WAVEFORMS tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL Q trec 50% CLOCK GND VCC tf VCC RESET GND tPHL tw 50% VCC GND Figure 1. Figure 2. TEST POINT VALID VCC DATA 50% GND tsu CLOCK 50% GND th VCC * Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL* Figure 3. Figure 4. Test Circuit MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC174A OUTLINE DIMENSIONS -A - 16 9 J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -B - C L 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -T SEATING - PLANE N E F G D 16 PL 0.25 (0.010) M K M J 16 PL 0.25 (0.010) M TB S TA S DIM A B C D E F G J K L M N -A - 16 9 N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M -A - 16 9 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -B - 1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC174A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 6 *MC54/74HC174A/D* MC54/74HC174A/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
Price & Availability of MC54HC174A
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