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4.0 Gbps Dual Driver ADATE209
FEATURES
>4.0 Gbps (2 V swings) 120 ps rise time/fall time (2 V swings) <1.0 W for dual driver (<500 mW/channel) -1 V to +3.5 V range Fast termination mode (VTx) Cable loss compensation
FUNCTIONAL BLOCK DIAGRAM
VH1 VL1 VT1 DA1 DB1 TERM1 CLC1EN VH2 DROUT1
APPLICATIONS
Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment High speed memory testing (DDR2/DDR3/DDR4) HDMI testing
DA2 DB2 TERM2
VL2 VT2 DROUT2
07277-001
CLC2EN
Figure 1.
GENERAL DESCRIPTION
The ADATE209 is a dual pin driver designed for testing DDR2, DDR3, and DDR4. It can also be used for high speed SoC applications, such as testing PCI Express 1.0 and HDMITM. The device is a three-level driver capable of high fidelity swings from 200 mV to 4 V over a -1 V to +3.5 V range. It has rise/fall times (20% to 80%) under 120 ps for a 2 V programmed swing and 150 ps for a 3 V programmed swing, and is capable of supporting data rates of 4.4 Gbps and 3.2 Gbps, respectively. The device is capable of high speed transitions into and out of termination mode. It also contains peaking/pre-emphasis circuitry. The ADATE209 is available in an 8 mm x 8 mm, 49-ball CSP_BGA.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADATE209 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Explanation of Test Levels ........................................................... 6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................9 Applications Information .............................................................. 14 Data Inputs .................................................................................. 14 Thermal Diode String ................................................................ 14 Cable Loss Compensation/Peaking Circuitry ........................ 14 Default Test Conditions ............................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
5/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADATE209 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 7.0 V, VEE = -4.5 V, GND = 0.0 V; all test conditions are as defined in Table 7, unless otherwise specified. All specified values are at TJ = 70C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are measured at TJ = 70C 20C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Table 1.
Parameter TOTAL FUNCTION DROUTx Pin Range POWER SUPPLIES Positive Supply, VCC Negative Supply, VEE Data and Termination, VDAx, VDBx, VTERMx Data and Termination, IDAx, IDBx, ITERMx Min -1.0 6.65 -4.73 -1 7.0 -4.5 +1.3 40 Typ Max +3.5 7.35 -4.28 +3.3 Unit V V V V mA Test Level1 I I I I I Defines PSRR conditions Defines PSRR conditions Exceeding 40 mA through any input termination resistor may cause damage to the device or cause long-term reliability concerns Test Conditions/Comments
Positive Supply Current, ICC Negative Supply Current, IEE Total Power Dissipation
50 60 0.5
76 80 0.87 0.97
100 110 1.3
mA mA W W
II II II III
Quiescent; excludes current draw through data input termination resistors VLx = 0.0 V, VHx = 2.0 V; driver toggling into open circuit; excludes current draw through data input termination resistors
TEMPERATURE MONITORS Temperature Sensor Gain Temperature Sensor Offset DRIVER DC SPECIFICATIONS High Speed Differential Logic Input Characteristics (DAx, DBx, TERMx) Input Termination Resistance
-4.7 3.1
mV/C V
III III
Voltage reading at 30C
45
48
55
II
9 mA pushed into DAxB/DBxB/TERMxB signal, 0.6 V forced on DAx/DBx/TERMx signal; DAxT, DBxT, TERMxT open; measure voltage from DAx/DBx/ TERMx signal to DAxB/DBxB/TERMxB signal, calculate resistance (V/I)
Input Voltage Differential Common-Mode Voltage Input Bias Current
0.25 -1.0 -10
+1.2
0.8 +3.3 +10
V V A
IV IV II
Each pin tested at -1.0 V and +3.3 V, while other high speed pins (DAxB, DBx, DBxB, TERMx, TERMxB) are left open, termination pins (DAxT, DBxT, TERMxT) open
Pin Output Characteristics Output High Range, VHx Output Low Range, VLx Output Termination Range, VTx Output High Range, VHx Output Low Range, VLx Output Termination Range, VTx Functional Amplitude (VHx - VLx)
-0.9 -1.0 -1.0 -0.9 -1.0 -1.0 0.2
+3.5 +3.4 +3.5 +4.0 +3.9 +4.0 4.5
V V V V V V V
I I I I I I I
DC Output Current-Limit Source
50
60
70
mA
II
VCC = 7.5 V, this range is not production tested VCC = 7.5 V, this range is not production tested VCC = 7.5 V, this range is not production tested Amplitude can be programmed to VHx = VLx, accuracy specifications apply when VHx - VLx 200 mV Driver high, VHx = 3.5 V, short DROUTx pin to -1.0 V, then measure current
Rev. 0 | Page 3 of 16
ADATE209
Parameter DC Output Current-Limit Sink Output Resistance, 30 mA Min -70 46.5 Typ -60 48.5 Max -50 50.5 Unit mA Test Level1 II II Test Conditions/Comments Driver high, VHx = -1.0 V, short DROUTx pin to 3.5 V, then measure current Source: driver high, VHx = 3.0 V, IDUT = 1 mA and 9 mA; sink: driver low, VLx = 0.0 V, IDUT = -1 mA and -9 mA; VDROUTx/IDROUTx VHx tests conducted with VLx = -1.0 V and VTx = -1.0 V; VLx tests conducted with VHx = 3.5 V and VTx = 3.5 V; VTx tests conducted with VLx = -1.0 V and VHx = 3.5 V Measured at 0.0 V, target: improve offset Measured at calibration points, 0.0 V and 2.0 V Relative to straight line from 0.0 V to 2.0 V After two-point gain/offset calibration, relative to straight line from 0.0 V to 2.0 V VLx = -1.0 V, VHx swept from -0.9 V to +3.5 V, VTx swept from -1.0 V to 3.5 V, VHx = 3.5 V, VLx swept from -1.0 V to +3.4 V, VTx swept from -0.8 V to +3.5 V, VTx = 1.5 V, VLx swept from -1.0 V to +3.5 V, VHx swept from -1.0 V to +3.5 V Change in output voltage as power supplies are moved by 5%; measured at calibration points, 0.0 V and 2.0 V
Absolute Accuracy
VHx, VLx, VTx Offset VHx, VLx, VTx Offset Temperature Coefficient VHx, VLx, VTx Gain VHx, VLx, VTx Linearity VLx, VHx, VTx Interaction
-150
+20 270 1.02 2.4 0.3
+150
mV V/C %FSR mV mV
II III II II III
0.97 -15
1.03 +15
VHx, VLx, VTx DC PSRR
-36
+24
+36
mV/V
II
VHx, VLx, VTx Input Bias Current DRIVER AC SPECIFICATIONS Rise/Fall Times 0.2 V Programmed Swing 0.5 V Programmed Swing 1.0 V Programmed Swing 2.0 V Programmed Swing 3.0 V Programmed Swing 4.0 V Programmed Swing Rise-to-Fall Matching Minimum Pulse Width 0.2 V Programmed Swing 0.5 V Programmed Swing 1.0 V Programmed Swing 2.0 V Programmed Swing 3.0 V Programmed Swing Maximum Toggle Rate
-10
+1
+10
A
II Toggle DAx inputs VHx = 0.2 V, VLx = 0.0 V, terminated, 20% to 80% VHx = 0.5 V, VLx = 0.0 V, terminated, 20% to 80% VHx = 1.0 V, VLx = 0.0 V, terminated, 20% to 80% VHx = 2.0 V, VLx = 0.0 V, terminated, 20% to 80% VHx = 3.0 V, VLx = 0.0 V, terminated, 20% to 80% VHx = 3.5 V, VLx = -0.5 V, terminated, 20% to 80% VHx = 1.0 V, VLx = 0.0 V, terminated; rise to fall within one channel Toggle both DAx and DBx inputs VHx = 0.2 V, VLx = 0.0 V, terminated, timing error less than 25 ps VHx = 0.5 V, VLx = 0.0 V, terminated, timing error less than 25 ps VHx = 1.0 V, VLx = 0.0 V, terminated, timing error less than 25 ps VHx = 2.0 V, VLx = 0.0 V, terminated, timing error less than 25 ps VHx = 3.0 V, VLx = 0.0 V, terminated, timing error less than 25 ps VHx = 1.0 V, VLx = 0.0 V, terminated, 10% amplitude degradation VHx = 2.0 V, VLx = 0.0 V, terminated, 10% amplitude degradation VHx = 3.0 V, VLx = 0.0 V, terminated, 10% amplitude degradation
90
115 90 90 110 150 190 10
130
ps ps ps ps ps ps ps
V V V II/V V V V
200 180 180 200 300 2.5 2.2 1.8
ps ps ps ps ps GHz GHz GHz
V V V V V V V V
Rev. 0 | Page 4 of 16
ADATE209
Parameter Dynamic Performance, Drive (VHx to VLx) Propagation Delay Time Propagation Delay Temperature Coefficient Delay Matching, Edge to Edge Delay Change vs. Duty Cycle Preshoot and Undershoot Settling Time (VHx to VLx) To Within 3% of Final Value To Within 1% of Final Value Rise/Fall Times (VTx to/from VHx/VLx) 1.0 V Programmed Swing 2.0 V Programmed Swing Dynamic Performance, VTERM (VHx or VLx to/from VTx) Propagation Delay Time Cable Loss Compensation Logic Control Inputs, CLCxEN Logic High Logic Low ICLCxEN Compensation Constants Boost Time Constant Boost Peaking Amplifier
1
Min 300
Typ 660 0.7 15 10 10 0.4 2 110 170
Max 1400
Unit ps ps/C ps ps mV ns ns ps ps
Test Level1 II/V III V V V V V V V
Test Conditions/Comments Toggle DAx inputs VHx = 2.0 V, VLx = 0.0 V, terminated VHx = 2.0 V, VLx = 0.0 V, terminated VHx = 2.0 V, VLx = 0.0 V, terminated, rising vs. falling VHx = 2.0 V, VLx = 0.0 V, terminated, 5% to 95% duty cycle VHx = 2.0 V, VLx = 0.0 V, terminated Toggle DAx Inputs VHx = 2.0 V, VLx = 0.0 V, terminated VHx = 2.0 V, VLx = 0.0 V, terminated Toggle DAx inputs VHx = 1.0 V, VTx = 0.5V, VLx = 0.0 V, terminated, 20% to 80% VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V, terminated, 20% to 80% Toggle TERMx inputs VHx = 3.0 V, VTx = 1.5 V, VLx = 0.0 V, terminated
720 0 0.9 0 -10 3.3 3.3 0.7 +10
ns V V V A ps %
V I IV IV II V V
1.2 275 18
VIN = 0.0 V and 3.3 V CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V, terminated CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V, terminated
See the Explanation of Test Levels section.
Rev. 0 | Page 5 of 16
ADATE209 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Supply Voltage Difference (VCC to VEE) Reference Ground (DUTGND to GND) Input Voltages Input Common-Mode Voltage Short-Circuit Voltage (RL = 0 , VDUT Continuous Short-Circuit Condition) High Speed Input Voltage (Data and Termination Inputs, DAx, DBx, and TERMx) High Speed Differential Input Voltage (DAx, DBx, TERMx to Termination Pin DAxT, DBxT, TERMxT) VHx, VLx, VTx CLCxEN DROUTx I/O Pin Current DCL Maximum Short-Circuit Current (RL = 0 , VDUT = -1.5 V to +4 V; DCL Current Limit) Rating -0.5 V to +8.0 V -5.0 V to +0.5 V -1.0 V to +13 V -0.5 V to +0.5 V VEE to VCC -1.5 V to +4.0 V -1.5 V to +3.9 V
THERMAL RESISTANCE
JA is specified for the following conditions: JEDEC 4L PCB, 50C, and 100 LFM forced convection. JC is specified for a 50C cold plate and 50C ambient temperature. Table 3. Thermal Resistance
Package Type 49-Ball CSP_BGA JA 48.4 JC 3.9 Unit C/W
EXPLANATION OF TEST LEVELS
I. II. III. Definition. 100% Production Tested. Characterized on Tester. Functionally Checked During Production Test. Characterized on Bench.
2V
IV.
-2 V to +4.5 V -1 V to +3.5 V 100 mA
V.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 16
ADATE209 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 A GND VEE DROUT2 GND DROUT1 VEE GND
B
TERM2
VCC
VEE
GND
VEE
VCC
TERM1
C
TERM2B
TERM2T
VCC
GND
VCC
TERM1T
TERM1B
D
DA2
DA2T
GND
GND
GND
DA1T
DA1
E
DA2B
GND
VH2
GND
VH1
GND
DA1B
F
DB2
DB2T
VL2
VCCTHERM
VL1
DB1T
DB1
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 Mnemonic GND VEE DROUT2 GND DROUT1 VEE GND TERM2 VCC VEE GND VEE VCC TERM1 TERM2B TERM2T VCC GND VCC TERM1T TERM1B DA2 DA2T GND Description Ground. Negative Power Supply, -4.5 V. Driver Output, Channel 2. Ground. Driver Output, Channel 1. Negative Power Supply, -4.5 V. Ground. Termination Mode Data Input. Noninverting input for Channel 2. Positive Power Supply, 7.0 V. Negative Power Supply, -4.5 V. Ground. Negative Power Supply, - 4.5 V. Positive Power Supply, 7.0 V. Termination Mode Data Input. Noninverting input for Channel 1. Termination Mode Data Input. Inverting input for Channel 2. Termination Pin for Termination Mode Data Input, Channel 2. Positive Power Supply, 7.0 V. Ground. Positive Power Supply, 7.0 V. Termination Pin for Termination Mode Data Input, Channel 1. Termination Mode Data Input. Inverting input for Channel 1. Data Input A. Noninverting input for Channel 2. Termination for Data Input A, Channel 2. Ground.
Rev. 0 | Page 7 of 16
07277-002
G
DB2B
CLC2EN
VT2
THERM
VT1
CLC1EN
DB1B
ADATE209
Pin No. D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Mnemonic GND GND DA1T DA1 DA2B GND VH2 GND VH1 GND DA1B DB2 DB2T VL2 VCCTHERM VL1 DB1T DB1 DB2B CLC2EN VT2 THERM VT1 CLC1EN DB1B Description Ground. Ground. Termination for Data Input A, Channel 1. Data Input A. Noninverting input for Channel 1. Data Input A. Inverting input for Channel 2. Ground. VH Input, Channel 2. Ground. VH Input, Channel 1. Ground. Data Input A. Inverting input for Channel 1. Data Input B. Noninverting input for Channel 2. Termination for Data Input B, Channel 2. VL Input, Channel 2. Positive Power Supply for Thermal Diode String, 7.0 V. VL Input, Channel 1. Termination for Data Input B, Channel 1. Data Input B. Noninverting input for Channel 1. Data Input B. Inverting input for Channel 2. Cable-Loss Compensation Control Pin, Channel 2. VT Input, Channel 2. Thermal Diode Connection. VT Input, Channel 1. Cable-Loss Compensation Control Pin, Channel 1. Data Input B. Inverting input for Channel 1.
Rev. 0 | Page 8 of 16
ADATE209 TYPICAL PERFORMANCE CHARACTERISTICS
0.30 0.25 0.20
VOLTAGE (V)
1.2
0.5V
1.0 0.8
0.15 0.10 0.05 0 0.2V
VOLTAGE (V)
0.6 0.4 0.2 0 -0.2
CLC ENABLED CLC DISABLED
07277-009
07277-008
07277-015
0
0.29
0.58
0.87
1.16
1.45
1.74
2.03
2.32
2.61
2.90
3.19
3.48
3.77
4.06
4.35
4.64
4.93
0
0.116
0.232
0.348
0.464
0.580
0.696
0.812
0.928
1.040
1.160
1.280
1.390
1.510
1.620
1.740
1.860
TIME (ns)
TIME (ns)
Figure 3. Small Signal Response, VHx = 500 mV, 200 mV, VLx = 0.0 V
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
07277-013
Figure 6. VHx = 2.0 V, VLx = 0.0 V, 1.5 GHz Waveform, CLC Disabled and Enabled
1.2 1.0 0.8
VOLTAGE (V)
CLC ENABLED CLC DISABLED
VOLTAGE (V)
0.6 0.4 0.2 0 -0.2
0 0.232 0.058 0.116 0.174 0.290 0.348 0.406 0.464 0.522 0.580 0.638 0.696 0.754 0.812 0.870 0.928 0.986
1.970
TIME (ns)
TIME (ns)
Figure 4. Large Signal Response, VHx = 3.0 V, 2.0 V, 1.0 V, VLx = 0.0 V
2.0
Figure 7. VHx = 2.0 V, VLx = 0.0 V, 2.0 GHz Waveform, CLC Disabled And Enabled
1.4 1.2 1.0 CLC ENABLED CLC DISABLED
CLC ENABLED CLC DISABLED
1.5
VOLTAGE (V)
1.0
VOLTAGE (V)
0.8 0.6 0.4 0.2
0.5
0
0
07277-014
0
0.29
0.58
0.87
1.16
1.45
1.74
2.03
2.32
2.61
2.90
3.19
3.48
3.77
4.06
4.35
4.64
4.93
0
0.116
0.232
0.348
0.464
0.580
0.696
0.812
0.928
1.040
1.160
1.280
1.390
1.510
1.620
1.740
TIME (ns)
TIME (ns)
Figure 5. Large Signal Response, VHx = 3.0 V, 2.0 V, 1.0 V, VLx = 0.0 V, CLC Disabled and Enabled
Figure 8. VHx = 2.0 V, VLx = 0.0 V, 1.0 GHz Waveform, CLC Disabled and Enabled
Rev. 0 | Page 9 of 16
1.860
-0.5
-0.2
07277-010
0
0.29
0.58
0.87
1.16
1.45
1.74
2.03
2.32
2.61
2.90
3.19
3.48
3.77
4.06
4.35
4.64
4.93
-0.2
1.970
-0.05
ADATE209
1.2 1.0 0.8
VOLTAGE (V)
0.7 0.6 0.5 0.4
CLC ENABLED CLC DISABLED
VOLTAGE (V)
CLC ENABLED CLC DISABLED
07277-011
0.6 0.4 0.2 0 -0.2 -0.4
0.3 0.2 0.1 0 -0.1
07277-003 07277-007 07277-004
0
0.385
0.770
1.160
1.540
1.930
2.310
2.700
3.080
3.470
3.850
4.240
4.620
0
0.116
0.232
0.348
0.464
0.580
0.696
0.812
0.928
1.040
1.160
1.280
1.390
1.510
1.620
1.740
1.740
1.860
1.860
TIME (ns)
TIME (ns)
Figure 9. VHx = 2.0 V, VLx = 0.0 V, 500 MHz Waveform, CLC Disabled and Enabled
0.6 0.5 0.4
Figure 12. VHx = 1.0 V, VLx = 0.0 V, 1.0 GHz Waveform, CLC Disabled and Enabled
0.6 0.5 0.4 VOLTAGE (V) 0.3 0.2 0.1 0 -0.1 -0.2 CLC ENABLED CLC DISABLED 0.116 0.232 0.348 0.464 0.580 0.696 0.812 0.928 1.040 1.160 1.280 1.390 1.510 1.620 1.970
VOLTAGE (V)
0.3 0.2 0.1 0 -0.1 -0.2
CLC ENABLED CLC DISABLED
07277-006
0
0.29
0.58
0.87
1.16
1.45
1.74
2.03
2.32
2.61
2.90
3.19
3.48
3.77
4.06
4.35
4.64
TIME (ns)
4.93
0
TIME (ns)
Figure 10. VHx = 1.0 V, VLx = 0.0 V, 500 MHz Waveform, CLC Disabled and Enabled
0.6 0.5 0.4
Figure 13. VHx = 1.0 V, VLx = 0.0 V, 1.5 GHz Waveform, CLC Disabled and Enabled
0.6 0.5 0.4
VOLTAGE (V)
0.3 0.2 0.1 0 -0.1 CLC ENABLED CLC DISABLED
07277-005
VOLTAGE (V)
0.3 0.2 0.1 0 -0.1
0
0.058
0.116
0.174
0.232
0.290
0.348
0.406
0.464
0.522
0.580
0.638
0.696
0.754
0.812
0.870
0.928
0.986
0
0.116
0.232
0.348
0.464
0.580
0.696
0.812
0.928
1.040
1.160
1.280
1.390
1.510
1.620
1.740
1.860
TIME (ns)
TIME (ns)
Figure 11. VHx = 1.0 V, VLx = 0.0 V, 2.0 GHz Waveform, CLC Disabled and Enabled
Figure 14. VHx = 1.0 V, VTx = 0.5 V, VLx = 0.0 V, Transitions Between VHx/VLx and VTx
Rev. 0 | Page 10 of 16
1.970
1.970
-0.2
ADATE209
1.2 1.0 0.8
VOLTAGE (V)
TRAILING EDGE ERROR (ps)
30
20 NEGATIVE PULSE 10
0.6 0.4 0.2 0 -0.2
0 POSITIVE PULSE -10
-20
07277-012
0.116
0.232
0.348
0.464
0.580
0.696
0.812
0.928
1.040
1.160
1.280
1.390
1.510
1.620
1.740
1.860
1.970
1 PULSE WIDTH (ns)
10
TIME (ns)
Figure 15. VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V, Transitions Between VHx/VLx and VTx
30
Figure 18. 3 V Minimum Pulse Width (VHx = 3.0 V, VLx = 0.0 V), CLC Disabled
5
20 TRAILING EDGE ERROR (ps)
0
10
LINEARITY ERROR (mV)
NEGATIVE PULSE
-5
0
-10 50C -15 70C -20 90C
-10
POSITIVE PULSE
-20
07277-016
1 PULSE WIDTH (ns)
10
-2
-1
0
1 VHx (V)
2
3
4
Figure 16. 1 V Minimum Pulse Width (VHx = 1.0 V, VLx = 0.0 V), CLC Disabled
30
Figure 19. Driver Linearity (VHx), VLx = -1.1 V, VTx = 1.0 V
4 3
LINEARITY ERROR (mV)
20 TRAILING EDGE ERROR (ps) NEGATIVE PULSE 10 POSITIVE PULSE
90C 70C 50C
2 1 0 -1 -2 -3
0
-10
-20
07277-017
1 PULSE WIDTH (ns)
10
-2
-1
0
1 VLx (V)
2
3
4
Figure 17. 2 V Minimum Pulse Width (VHx = 2.0 V, VLx = 0.0 V), CLC Disabled
Figure 20. Driver Linearity (VLx), VHx = 3.6 V, VTx = 1.0 V
Rev. 0 | Page 11 of 16
07277-020
-30 0.1
07277-019
-30 0.1
-25
07277-018
-30 0.1
0
ADATE209
1.5 1.0 0.5
LINEARITY ERROR (mV) THERM VOLTAGE (V)
3.10 90C 3.05 3.00 2.95 2.90 2.85 2.80 2.75 2.70
0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -2 -1 0 1 VTx (V) 2 50C
70C
TEMPERATURE (C)
Figure 21. Driver Linearity (VTx), VHx = 2.0 V, VLx = 0.0 V
1.040 GAIN VHx CH1 GAIN VHx CH2 1.035
Figure 24. Temperature Sensor Output Voltage vs. Temperature
1.030
GAIN (%FSR)
1.020
1.015
TEMPERATURE (C)
07277-022
50
60
70
80
90
100
200ps/DIV
Figure 22. Gain of VHx
10 5 0 -5 -10 CH1 OFFSET -15 -20 -25 40 CH2 OFFSET
Figure 25. VHx = 1.8 V, VLx = 0.0 V, PRBS31, 1.6 Gbps, CLC Disabled
DRIVER OFFSET (V)
100mV/DIV
TEMPERATURE (C)
07277-023
50
60
70
80
90
100
200ps/DIV
Figure 23. Driver Offset vs. Temperature
Figure 26. VHx = 1.8 V, VLx = 0.0 V, PRBS31, 2.1 Gbps, CLC Disabled
Rev. 0 | Page 12 of 16
07277-026
07277-025
1.010 40
61.18mV/DIV
1.025
07277-024
3
4
07277-021
-3.5
0
20
40
60
80
100
120
ADATE209
100mV/DIV
07277-027
50mV/DIV
100ps/DIV
50ps/DIV
Figure 27. VHx = 1.5 V, VLx = 0.0 V, PRBS31, 3.2 Gbps, CLC Disabled
Figure 29. VHx = 0.5 V, VLx = 0.0 V, PRBS31, 5.0 Gbps, CLC Disabled
100mV/DIV
50mV/DIV
100ps/DIV
07277-028
50ps/DIV
Figure 28. VHx = 1.5 V, VLx = 0.0 V, PRBS31, 4.0 Gbps, CLC Disabled
Figure 30. VHx = 0.5 V, VLx = 0.0 V, PRBS31, 5.0 Gbps, CLC Enabled
Rev. 0 | Page 13 of 16
07277-030
07277-029
ADATE209 APPLICATIONS INFORMATION
DATA INPUTS
The ADATE209 contains three high speed differential inputs for each channel. Two of the inputs, combined in an on-chip exclusive-OR gate, control the VHx/VLx transitions. The exclusive-OR gate can be used as a data mux or for data inversion. The third input is used to control the transitions to the VTx level. Table 5. Logic Truth Table
DAx Low High Low High X1
1
VCCTHERM 40 THERM
GND ADATE209
Figure 32. Thermal Diode String Schematic
DBx Low Low High High X1
TERMx Low Low Low Low High
DROUTx VL VH VH VL VT
CABLE LOSS COMPENSATION/PEAKING CIRCUITRY
The ADATE209 has two different CLC/peaking modes: nominal and boost. In nominal mode, a small amount of high frequency energy is injected in the driver output signal to compensate for high frequency losses in the test interface. In boost mode, a much larger percentage of high frequency energy is injected in the driver output signal. The two modes are controlled through the CLCxEN signal. Table 6.
CLCxEN Logic low Logic high CLC/Peaking Mode Nominal Boost
X = don't care.
The high speed inputs are designed to be compatible with most types of differential inputs. Each side of the differential inputs is terminated through 50 to a common point. For connection to PECL inputs, connect the DAxT/DBxT/TERMxT input termination to VCC - 2.0 V (VCC of the input signal, not of the ADATE209) or to an appropriate resistor to ground. For connection to LVDS, do not connect DAxT/DBxT/TERMxT. For connection to CML signals, either leave DAxT/DBxT/TERMxT open or connect DAxT/DBxT/TERMxT to the appropriate VCC/VDD level.
DAxT, DBxT, TERMxT
For applications using very short path lengths, very high fidelity cables and connectors, and/or lower data rates, nominal mode should be used. For applications using lower fidelity cables and connectors (and often lower cost) and/or at higher data rates, use boost mode.
DEFAULT TEST CONDITIONS
50 DAx, DBx, TERMx DAxB, DBxB, TERMxB 50
07277-031
Table 7 lists the default test conditions. Table 7.
Name DB1/DB1B DB2/DB2B DA1T/DA2T/DB1T/DB2T VHx VLx VTx Default Test Condition Logic high Logic high 1.3 V 2.0 V 0.0 V 1.0 V
Figure 31. Input Termination Schematic Diagram
THERMAL DIODE STRING
Figure 32 shows a simplified schematic of the thermal diode string. To use the diode string, connect VCCTHERM to 7.0 V and measure the voltage at THERM. The nominal gain of the thermal diode string is -4.7 mV/C.
Rev. 0 | Page 14 of 16
07277-032
ADATE209 OUTLINE DIMENSIONS
8.10 8.00 SQ 7.90 A1 BALL CORNER 3.275 REF
7 6 5 4 3 2 1 A B
A1 BALL CORNER
3.225 REF
6.00 BSC SQ 1.00 BSC
C D E F G
TOP VIEW
BOTTOM VIEW
DETAIL A *1.60 MAX 1.21 NOM 0.60 0.56 0.52 0.55 0.50 0.45 SEATING PLANE
DETAIL A
0.305 REF
0.100 REF
0.68 0.63 0.58 BALL DIAMETER
COPLANARITY 0.10
*COMPLIANT TO JEDEC STANDARDS MO-192-ABB-1 WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 33. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-49-4) Dimensions shown in millimeters
ORDERING GUIDE
Model ADATE209BBCZ1
1
Temperature Range -40C to +85C
Package Description 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Package Option BC-49-4
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
030408-A
ADATE209 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07277-0-5/08(0)
Rev. 0 | Page 16 of 16

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