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PRELIMINARY DATA SHEET - Rev 1.0
Integrated Digital Tuner with RF and IF Gain Control
AIT1042
FEATURES
* CompleteIntegratedRFTuner:Includes UpconverterwithRFGainControl, Downconverter,DigitalIFAmplifierwithGain Control,DualPLL,andVCOswithintegrated tanks
*
IFOutput-35to50MHz
* 54to1002MHzOperation * OperatesfromaSingle+5VSupply * IntegratedOscillatorTankCircuits * 78dBGain(includingexternalfilterlosses) throughDigitalOutput
*
5dBRFGainControlRange 3
* 45dBIFGainControlRange * 2-WireSerialProgrammingwith4Addressesfor MultipleTunerApplications
*
S38 Package 48 Pin QFN 7 mm x 7 mm x 1 mm PRODUCT DESCRIPTION
ProgrammablePower-DownMode TheAIT1042IntegratedDigitalTunerwithRFandIF GainControlisacomplete1GHzbandwidthtunerIC specificallydesignedtosupportdigitalvideoanddata applications.ItcombinesGaAsandSilicontechnology to integrate the upconverter, downconverter, VCO, synthesizer,IFamplifier,RFgaincontrolandIFgain control functions of a double-conversion tuner into onesmallpackage.
* ProgrammableChargePumpCurrents * MaterialssetconsistentwithRoHSdirectives
APPLICATIONS
* CATVTuners * HDTVTuners * Set-TopBoxes * PCTVTunerCardsorTuner-on-Board
Figure 1: Functional Block Diagram
02/2009
AIT1042
Theexceptionallinearityandlownoisefigureofthe AIT1042areidealforusewithtoday'sCATVsystems withdenselyloadedspectrum.Withintegratedoscillator tank circuits, theAIT1042's high level of integration minimizesboardlayoutsensitivitiesandtheamount ofexternalcircuitryrequiredforacompletereceiver solution. The integrated IF output further enables system solutions that minimize board layout space.
Thedeviceoperatesfromasingle+5Vsupply,and incorporatesaprogrammablepower-downmode. TheAIT1042isofferedinasmall7mmx7mmx1mm, 48pin,RoHScompliant,surfacemountpackageideal forspace-sensitiveapplicationssuchasPCcardsand multiple-tunerset-topboxes.
ACGND
VREGBYP4
VREGBYP3
Figure 2: Pinout (X-ray Top View)
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042 Table 1: Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME VDDU1 ACGND ACGND RFUIN GND GND GND VRFAGC VDDU2 GND GND GND VREGBYP3 VUFC GND CPU DESCRIPTION UpconverterSupply ACGround ACGround UpconverterRFInput Ground Ground Ground RFGainControlVoltage UpconverterSupply Ground Ground Ground RegulatorBypass UpconverterOscillatorFrequency ControlVoltage Ground UpconverterSynthesizerCharge PumpOutput UpconverterSynthesizerSupply PIN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NAME IFOUT+ IFOUTGND GND RFDNRFDN+ IFDIGOUT+ IFDIGOUTDESCRIPTION UpconverterDifferentialIFOutput (Inputto1stIFFilter) UpconverterDifferentialIFOutput (Inputto1stIFFilter) Ground Ground DownconverterDiff.RFInput DownconverterDiff.RFInput DigitalIFDifferentialOutput DigitalIFDifferentialOutput RegulatorBypass IFGainControlVoltage Ground Ground DigitalIFAMPSupply IFAmplifierDifferentialInput IFAmplifierDifferentialInput DownconverterSupply DownconverterDifferentialIFOutput (Inputto2ndIFFilter)Inductively CoupledtoVDD DownconverterDifferentialIFOutput (Inputto2ndIFFilter)Inductively CoupledtoVDD RegulatorBypass Ground Ground Downconv.OscillatorFrequency ControlVoltage DownconverterSynthesizerCharge PumpOutput 2-WireInterfaceAddressSelect Voltage
VREGBYP2
VIFAGC GND GND VDDDIGIF IFINIFIN+ VDDDN
17
VDDSYNU1
32
IFDOUT+
18 19 20 21 22 23 24
VREGBYP1 REFIN REFOUT VDDSYND1 VDDSYND2 CLK DATA
RegulatorBypass CrystalReferenceInput CrystalReferenceOutput DownconverterSynthesizerSupply DownconverterSynthesizerSupply 2-WireInterfaceCLK 2-WireInterfaceData
31 30 29 28 27 26 25
IFDOUTVREGBYP4 GND GND VDFC CPD VAS
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
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AIT1042
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER SupplyVoltage(VCC) RFGainControlVoltage(VRFAGC) IFGainControlVoltage(VIFAGC) RFInputPower ElectrostaticDischarge (HumanBodyModel) StorageTemperature MIN 0 0 0 -55 MAX +6 +6 +6 +60 250 +150 UNIT V V V dBmV at RFUIN and RFDIN V C Class1A COMMENTS
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability.
Table 3: Operating Ranges
PARAMETER SupplyVoltage(VCC) RFGainControlVoltage(VRFAGC) IFGainControlVoltage(VIFAGC) UpconverterRFInputCenter Frequency(fRF) FirstIFCenterFrequency(fIF1) IFOutputCenterFrequency(fIF2) CaseTemperature MIN 4.75 0 0 54 1680 35 0 TYP 5.00 1690 45 MAX 5.25 +3 +3 1002 1700 50 +85 UNIT V V V MHz MHz MHz C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications.
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042 Table 4: DC Electrical Specifications (TC = +55 C, VDD = +5.0 V)
PARAMETER RF Gain Control Current IF Gain Control Current TotalSupplyCurrent TotalPowerConsumption StandbyCurrent MIN TYP 100 100 320 1600 125 MAX UNIT A A mA mW mA
Table 5: AC Electrical Specifications (TC = +55 C, VDD = +5.0 V, fIF1 = 1690 MHz, fIF2 = 45.75 MHz)
PARAMETER ConversionGain(2),(3),(4) ChannelFlatness SSBNoiseFigure InputReturnLoss CompositeLOPhaseNoise RF Gain Control Range Digital IF Gain Control Range FinalIFOutputVoltage(4) CSO CTB XMOD PowerSupplyRejectionto1MHz MIN 3 20 TYP 78 0.5 8 -85 40 45 1000 -55 -63 -57 MAX UNIT dB dB dB dB dBc/Hz dB dB mVP-P dBc dBc dBc dB COMMENTS IFOutput(pins41&42) 6MHzBandwidth Measuredatmaxgain 75Impedancewithoutmatch 10kHzOffset maxgainatVRFAGC=+3V mingainatVRFAGC=+0.5V maxgainatVIFAGC=+3V mingainatVIFAGC=+0.5V IFOutput(pins41&42) 129Channels,+3dBmVeach 129Channels,+3dBmVeach 129Channels,+3dBmVeach 15.75kHzAM-modulated
Notes: 1. All specifications as measured in ANADIGICS test fixture with a 1st IF filter loss of 4 dB and a 2nd IF filter loss of 15 dB. (2) At maximum RF and IF AGC gain settings, where applicable. (3) Including nominal 1st and 2nd IF filter losses of 4 dB and 15 dB, respectively. (4) IF output measured with a 1 k differential load across pins 41 and 42.
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
5
AIT1042 Table 6: Digital 2-Wire Interface Specifications (TC = +55 C, VDD = +5.0 V, ref. Figure 3)
PARAMETER CLKFrequency LogicHighInput(pins23,24) LogicLowInput(pins23,24) LogicInputCurrentConsumption(pins23,24) AddressSelectInputCurrentConsumtion(pin25) DataSinkCurrent(2) BusFreeTimebetweenaSTOPandSTART Condition HoldTime(repeated)STARTCondition.Afterthis period,thefirstclockpulseisgenerated. LOWperiodofCLK HIGHperiodofCLK Set-upTimeforaRepeatedSTARTCondition DataHoldTime(for2-wirebusdevices) DataSet-upTime RiseTimeofDATAandCLKsignals FallTimeofDataandCLKsignals Set-upTimeforSTOPCondition CapacitiveLoadforEachBusLine SYMBOL fCLK VH VL ILOG IAS IAK tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Cb MIN 1 2.0 1.3 0.6 1.3 0.6 0.6 0.0 100 20+0.1Cb(1) 20+0.1Cb(1) 0.6 MAX 400 0.8 10 10 4.0 0.9 300 300 400 UNIT kHz V V A A mA s s s s s s ns ns ns s pF
Notes: (1) Cb is the total capacitance of one bus line in pF. (2) For maximum 0.8 V level during Acknowledge Pulse. 3. All timing values are referred to minimum VH and maximum VL levels.
DATA tF CLK
S
tLOW
tR
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Figure 3: Serial 2-Wire Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
Sr
tSU;STO
P
S
6
AIT1042 Figure 4: CSO vs. Frequency Figure ?: Frequency vs. CSO (+3dBmV input power, 129 channels - flat, TC = +558C) o
0 -10 -20
(+3dBmV input power, 129 digital channels, 25 C)
-1.25mHz -0.75mHz +0.75mHz +1.25mHz
CSO (dBc)
-30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
Figure ?: CSO vs. Frequency Figure 5: Frequency vs. CSO o (dBmV input power, +3dBmV Attack, 129129 flat channels, +25 C ) +15dBmV input power, +3dBmV Attack, channels - flat, TC = +558C) (+15
0 -10 -20
-1.25mHz -0.75mHz +0.75mHz +1.25mHz
CSO (dBc)
-30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
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AIT1042
( dBmV input power, +3 +3dBmV Attack / 129 flat channels, +25 +558C) (+20 +20dBmV input power, dBmV Attack / 129 channels - flat, TC = C )
0 -10 -20
-1.25mHz -0.75mHz +0.75mHz +1.25mHz
Figure ?:6:Frequency vs. CSO Figure CSO vs. Frequency
o
CSO (dBc)
-30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
Figure Frequency vs. CTB Figure ?: 7: CTB vs. Frequency (129 channels - flat, TC = +558C) o
(129 digital flat channels, +25 C)
-50 -52 -54 -56
+3dBmV Input +15dBmV Input, +3dBmV Attack +20dBmV Input, +3dBmV Attack
CTB (dBc)
-58 -60 -62 -64 -66 -68 -70 0 100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
Figure ?: 8: XMOD vs. Frequency Frequency vs. XMOD Figure
(129 digital flat channels, +558C) (129 channels - flat, TC = +25 C)
o
AIT1042
-45 -50 -55
XMOD (dBc)
-60 -65
+3dBmV Input
-70 -75 -80 -85 0 100 200 300 400 500 600
+15dBmV Input, +3dBmV Attack +20dBmV Input, +3dBmV Attack
700
800
900
1000
Frequency (MHz)
Figure Gain NF vs. vs. Frequency Figure ?:9: Gain && NF Frequency (TC = +558C)
Gain(dB) NoiseFigure(dB)
85 84 83 82
16 15 14 13 12 11 10 9 8 7 0 100 200 300 400 500 600 700 800 6 900 1000 1100
81 80 79 78 77 76 75
Frequency (MHz)
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
Noise Figure (dB)
9
Gain (dB)
AIT1042 FigureFigure ?: Internal Oscillator Phase Noise 10 KHz Offset 10: Composite Oscillator Phase Noise @ (10kHz) (TC = +558C)
-70 -72
Phase Noise (-dBc/Hz)
-74 -76 -78 -80 -82 -84 -86 -88 -90 50 150 250 350 450 550 650 750 850 950
Input Frequency (MHz)
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042
LOGIC PROGRAMMING
Thissectiondescribestheprogramminginterfacefor theANADIGICSAIT1042integratedtuner. PHYSICAL INTERFACE Hosts that conform to the I 2C-Bus Specification standardcanbeusedtoprogramtheAIT1042.The physicallayerinterfaceisatwo-wireserialbususing CLOCKandDATAdigitallines.Thenominalbitrateof theinterfaceis400kbits/sec.Fordatatransmission, the signal on the DATA line must be stable when theCLOCKsignalishigh,andthestateofthedata mustchangeonlywhiletheCLOCKsignalislow.A logicleveltransitionontheDATAlineduringahigh CLOCKsignalindicatesthebeginningorendofadata transmission,asspecifiedinthefollowingsectionsand showninFigure 4.
Start Indicator:
CLOCK
Table 7: Address Select Decoding (VDD = +5 V)
Pin 25 VAS Voltage 1.1to1.7V 0to0.8V 2.1to2.7V 4.2VtoVDD Address (Hex) C0 C2 C4 C6
DATA
Sending Data Ifthereceivedaddressbytematchestheaddressset bytheVASvoltage,theAIT1042willacknowledgeby pullingthedatalowbeforethe9thpositiveclockedge. Thehostcanthenbeginsendingprogrammingdatain 8-bitwords.TheMSBissentfirstandtheLSBlast. TheAIT1042 acknowledges receipt by pulling the DATAlinelowforoneclockpulseaftereachreceived byte.Thedataacknowledgementtellsthehostitmay sendthenextdataword.Eachgroupofthreedata words(24bitstotal)isusedtoprogramoneofseven registersdescribedbelow. Completing Data Transmission Aftersendingthefinaldataword,thehostsendsaStop indicatortomarktheendofdatatransmission.AStopis indicatedbyalow-to-hightransitionoftheDATAsignal whiletheCLOCKsignalisheldhigh.Afterreceiving the Stopindicator,theAIT1042ceasestosendfurther acknowledgementsandbeginstomonitortheCLOCK andDATAsignalsforthenextStartindicator. Note: The Stop indicator does not directly control when the programming data is latched or takes effect; the data takes effect immediately following the receipt of each three-word block of data, which represents a complete 24-bit divider register. Re-sending Data If,forsomereason,thedatatransmissionfailsoris interrupted,thehostcanresendthedata.Toresend data,anewStartindicatorandaddresswordmustbe sentpriortoanydatawords.
Stop Indicator:
CLOCK
DATA
Figure 4: Transmission Indicators
ADDRESSING THE AIT1042 TheAIT1042monitorstheCLOCKand DATAsignals foraStartindicationfromthehost.AStartisindicated byahigh-to-lowtransitionoftheDATAsignalwhilethe CLOCKsignalishigh.ImmediatelyfollowingtheStart indicator,thehostsendsan8-bitaddresswordtothe AIT1042.Addresswordsdependonthevoltageon Pin25(VAS),asshowninTable 7(theMSBissent first,LSBlast).OncetheAIT1042hasrecognizedthe Startindicatorandavalidaddressword,itsendsan addressacknowledgementtothehostbypullingthe DATAlinelowforoneclockpulse.Thehostcanthen begintosenddatatoprogramtheAIT1042.
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
11
AIT1042 PROGRAMMING THE AIT1042 ThissectiondescribeshowtoprogramtheregistersoftheAIT1042tocontrolitsoperation.The24-bitregisters thatcontrolthedividersandotherfunctionsareeachsegmentedintothree8-bitdatawords.Somebitshave requiredfixedvalues(reservedbitsandaddressing),whileothersareusedforcontrolandsynthesizeroperation. ThegrayedareasoftheaddressesandcontrolregistersarefixedvaluesandmustbesetasindicatedinTable 8. Control Register I Controlregister Ihastwouserprogrammablefunctions:
* *
Wake-up(Bit19) Chargepumpcurrentsettings(Bits8-10andbits12-14)inthesynthesizers
Table 9showshowtheWake-upbitisusedtocontrolpowerupoftheAIT1042.Whenthedeviceisinitially poweredupthewakeupbit(19)issetto0andthedevicewilldrawminimumcurrent.Settingbit19to1will turnthedeviceonfornormaloperation. Thechargepumpcurrentsettingsfortheupconverter(CPI1)anddownconverter(CPI2)synthesizersare setbyBits8-10andBits12-14,respectively.RefertoTable 10. Table 8: Control Register I
PLL_CtrlI (Control Register I) Firstdatabyte 23 0 22 1 21 0 20 0 19 W 18 0 17 0 16 0 15 0 14 Seconddatabyte 13 CPI2 12 11 0 10 9 CPI1 8 7 1 6 0 Thirddatabyte 5 0 4 0 3 0 2 0 1 0 0 1
MSB
LSB
Table 9: Wake-up Mode Bit
Bit 19 0 1 Wake-up mode Powerdown(default) Normaloperation
Table 10: Charge Pump Current Bits
CPIx Bits 0000 0001 0010 0011 0100 0101 0110 0111 Charge Pump Current (reserved) 0.7mA 1.3mA 1.9mA 2.5mA 3.1mA 3.6mA 4.1mA
Note: 1000 thru 1111 are Reserved.
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042 Control Register II ControlregisterIIcontainsonlyfixedvaluesofaddressandreservebitsthatmustbeprogrammedasindicated in Table 11. MSB
Firstdatabyte 23 0 22 1 21 0 20 1 19 1 18 0 17 0 16 0 15 0 14 0
Table 11: Control Register II
PLL_CtrlII (Control Register II) Seconddatabyte 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 Thirddatabyte 5 0 4 0 3 1 2 0 1 0
LSB
0 1
Control Register III ControlregisterIIIcontainsonlyfixedvaluesofaddressandreservedbitsthatmustbeprogrammedasindicated in Table 12.Therearenouserprogrammablebitsandthiscontrolregistermustbetransmittedlast.
MSB
Firstdatabyte 23 0 22 1 21 1 20 0 19 0 18 0 17 0 16 1 15 0
Table 12: Control Register III
PLL_CtrlIII (Control Register III) Seconddatabyte 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 0 6 1 Thirddatabyte 5 0 4 0 3 0 2 1 1 1
LSB
0 1
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
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AIT1042
Upconverter Main and Reference Divider Registers
TheupconvertermainandreferencedividerregistersareusedtosettheA,BandRcountersintheupconverter synthesizer.Theoutputfrequencyforthesynthesizeriscomputedusingthefollowingequation: where:
fosc = [(16)(B) + A] fxtal
R

fOSCistheupconverterlocaloscillator(LO1) frequency BisthedivideratiooftheBcounter(2to2047inclusive) AisthedivideratiooftheAcounter(0Inthemaindividerregister,theAcounterissetviaBits2-8andtheBcounterissetwithBits9-19.Inthe referencedividerregister,theRcounterissetwithBits2-11.Theremainingbitsmustusethefixedvalues indicatedinTables13and14.
MSB
Firstdatabyte 23 0 22 0 21 0 20 0 19 18
Table 13: Upconverter Main Divider Register
PLL1_Main (Upconverter Main Divider Register) Seconddatabyte 17 16 15 14 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 1
LSB
0 1
Bcounter
Acounter
MSB
Firstdatabyte 23 0 22 0 21 0 20 1 19 0 18 0
Table 14: Upconverter Reference Divider Register
PLL1_Ref (Upconverter Reference Divider Register) Seconddatabyte 17 1 16 0 15 0 14 0 13 0 12 0 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 1
LSB
0 0
Rcounter
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042
Downconverter Main and Reference Divider Registers
The downconverter main and reference divider registers are used to set theA, B and R counters in the downconverter synthesizer. The output frequency for the synthesizer is computed using the following equation:
fosc = [(64)(B) + A] fxtal
R
where:
fOSCisthedownconverterlocaloscillator(LO2)frequency BisthedivideratiooftheBcounter(2to2047inclusive) AisthedivideratiooftheAcounter(0Inthemaindividerregister,theAcounterissetviaBits2-8andtheBcounterissetwithBits9-19.Inthe referencedividerregister,theRcounterissetwithBits2-13.Theremainingbitsmustusethefixedvalues indicatedinTables 15 and 16. MSB
Firstdatabyte 23 0 22 0 21 0 20 0 19 18 17 16 15 14
Table 15: Downconverter Main Divider Register
PLL2_Main (Downconverter Main Divider Register) Seconddatabyte 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 0
LSB
0 1
Bcounter
Acounter
MSB
Firstdatabyte 23 0 22 0 21 0 20 1 19 0
Table 16: Downconverter Reference Divider Register
PLL2_Ref (Downconverter Reference Divider Register) Seconddatabyte 17 1 16 0 15 0 14 0 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 0
LSB
18 0
0 0
Rcounter
PRELIMINARY DATA SHEET - Rev 1.0 02/2009
15
AIT1042
Synthesizer Programming Example
ThefollowingisanexampleforprogrammingthetwosynthesizersintheAIT1042device.Thecalculations willdeterminethevaluesrequiredtoinputintothefourmainregisters: *Maindividerandreferencedividerfortheupconverter *Maindividerandreferencedividerforthedownconverter. Conditions ThedesiredCATVfrequencytoreceiveis55.25MHz(picturecarrier). The1stIF(HIF)is1690.75MHzandthe2ndIFis45.75MHz. Phasedetectorcomparisonfrequencyfortheupconverteris2000KHz(2MHz). Phasedetectorcomparisonfrequencyforthedownconverteris62.5KHz. Thecrystal(xtal)referenceoscillatorfrequencyis16MHz Thepresetmodulusoftheprescalarfor:Upconverter-P=16andforDownconveter-P=64. Calculation of the Reference Divider Values Thevalueforeachreferencedividercanbecalculatedbydividingthereferenceoscillatorfrequencybythe desiredphasedetectorcomparisonfrequency: R=Fref.osc./FPD Fortheupconverter,the16MHzcrystaloscillatorfrequencyandthe2000KHzphasedetectorcomparison frequencyareusedtoget: RPLL1=16MHz/2000KHz(2MHz)=8.Therefore,thebitvaluesfortheupconverterreferencedividerregisterwouldbe:0000001000 Forthedownconverter,the16MHzcrystaloscillatorfrequencyandthe62.5KHzphasedetectorcomparison frequencyareusedtoget:RPLL2=16MHz/62.5KHz(0.625MHz)=256.Therefore,thebitvaluesforthe downconverterreferencedividerregisterwouldbe: 0100000000 Main Divider Register Calculations ThevaluesoftheAandBcountersaredeterminedbythedesiredVCOoutputfrequencyoftheon-chiplocal oscillatorsandthephasedetectorcomparisonfrequency: N=FVCO/FPDB=trunc(N/P)A=N-(BxP) Theupconverterlocaloscillatorfrequencywillbe1690.75MHz+55.25MHz=1746MHzforthisexample. Therefore,theNvalueforPLL1willbe=1746MHz/2MHz=873,theBvalueforPLL1willbe=(873/16)= 54,andtheAvalueforPLL1willbe=873-(54x16)=9.Theupconvertermaindividerregistervaluewill be:B=00000110110,A=0001001 Thedownconverterlocaloscillatorfrequencywillbe1690.75-45.75MHz=1645MHz. Therefore,theNvaluesforPLL2willbe1645MHz/62.5KHz=26320,theBvalueforPLL2willbe= (26320/64)=411,andtheAvalueforPLL2willbe=26320-(411x64)=16.Thedownconvertermain registervaluewillbe:B=00110011011,A=0010000
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042 MSB
Firstdatabyte 23 0 22 0 21 0 20 1 19 0 18 0 17 1 16 0 15 0 14 0
Table 17: Complete Register Map
PLL2_Ref (Downconverter Reference Divider Register) Seconddatabyte 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 0
LSB
0 0
Rcounter
PLL2_Main (Downconverter Main Divider Register) Firstdatabyte 23 0 22 0 21 0 20 0 19 18 17 16 15 14 Seconddatabyte 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 0 0 1
Bcounter PLL1_Ref (Upconverter Reference Divider Register)
Acounter
Firstdatabyte 23 0 22 0 21 0 20 1 19 0 18 0 17 1 16 0 15 0 14 0
Seconddatabyte 13 0 12 0 11 10 9 8 7 6
Thirddatabyte 5 4 3 2 1 1 0 0
Rcounter
PLL1_Main (Upconverter Main Divider Register) Firstdatabyte 23 0 22 0 21 0 20 0 19 18 17 16 15 14 Seconddatabyte 13 12 11 10 9 8 7 6 Thirddatabyte 5 4 3 2 1 1 0 1
Bcounter
PLL_CtrlI (Control Register I)
Acounter
Firstdatabyte 23 0 22 1 21 0 20 0 19 W 18 0 17 0 16 0 15 0 14
Seconddatabyte 13 CPI2 12 11 0 10 9 CPI1 8 7 1 6 0
Thirddatabyte 5 0 4 0 3 0 2 0 1 0 0 1
PLL_CtrlII (Control Register II) Firstdatabyte 23 0 22 1 21 0 20 1 19 1 18 0 17 0 16 0 15 0 14 0 Seconddatabyte 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 Thirddatabyte 5 0 4 0 3 1 2 0 1 0 0 1
PLL_CtrlIII (Control Register III) Firstdatabyte 23 0 22 1 21 1 20 0 19 0 18 0 17 0 16 1 15 0 14 0 Seconddatabyte 13 0 12 0 11 0 10 0 9 1 8 0 7 0 6 1 Thirddatabyte 5 0 4 0 3 0 2 1 1 1 0 1
Reminder: Program Control Register III last. PRELIMINARY DATA SHEET - Rev 1.0 02/2009
17
AIT1042
PACKAGE OUTLINE
Figure 12: S38 Package Outline - 48 Pin 7 mm x 7 mm x 1 mm QFN
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009
AIT1042
ORDERING INFORMATION
ORDER NUMBER AIT1042RS38P8 TEMPERATURE RANGE O8Cto+858C PACKAGE DESCRIPTION RoHS-Compliant 48pinQFNPackage 7mmx7mmx1mm RoHS-Compliant 48pinQFNPackage 7mmx7mmx1mm COMPONENT PACKAGING
Tape&Reel,2500piecesperReel
AIT1042RS38P9
O8Cto+858C
SpecialHandling
ANADIGICS, Inc.
141MountBethelRoad Warren,NewJersey07059,U.S.A. Tel:+1(908)668-5000 Fax:+1(908)668-5132 URL:http://www.anadigics.com E-mail:Mktg@anadigics.com IMPORTANT NOTICE
ANADIGICS,Inc.reservestherighttomakechangestoitsproductsortodiscontinueanyproductatanytimewithoutnotice. TheproductspecificationscontainedinAdvancedProductInformationsheetsandPreliminaryDataSheetsaresubjectto changepriortoaproduct'sformalintroduction.InformationinDataSheetshavebeencarefullycheckedandareassumed tobereliable;however,ANADIGICSassumesnoresponsibilitiesforinaccuracies.ANADIGICSstronglyurgescustomers toverifythattheinformationtheyareusingiscurrentbeforeplacingorders.
ANADIGICSproductsarenotintendedforuseinlifesupportappliances,devicesorsystems.UseofanANADIGICSproduct inanysuchapplicationwithoutwrittenconsentisprohibited.
WARNING
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PRELIMINARY DATA SHEET - Rev 1.0 02/2009

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