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FD7T Series Multi-Output CMOS Clock Oscillator May 2008 * Pletronics' FD7T Series is a quartz crystal controlled precision square wave generator with multiple independent CMOS outputs * Output frequencies from 12 KHz to 230 MHZ * Selectable low jitter or spread spectrum outputs. * Device characteristics may be either factory or field programmable * 1.8V, 2.5 or 3.3V LVCMOS outputs * 5 x 7 mm LCC Ceramic Package * Low power * This is a low cost, mass produced oscillator. * Tape and Reel or cut tape packaging is available. * The package is designed for high density surface mount designs Model Number FD77xxT FD75xxT FD74xxT FD73xxT PLLs 4 3 2 1 Outputs 7 5 4 3 Pletronics Inc. certifies this device is in accordance with the RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives. Pletronics Inc. guarantees the device does not contain the following: Cadmium, Hexavalent Chromium, Lead, Mercury, PBB's, PBDE's Weight of the Device: 0.17 grams Moisture Sensitivity Level: 1 As defined in J-STD-020C Second Level Interconnect code: e4 Absolute Maximum Ratings: Parameter VDD VDDOUT Vi Vo Io Input Voltage Output Voltage Continuous Output Current Unit -0.5V to +2.5V -0.5V to +4.6V -0.5V to VDD+ 0.5V -0.5V to VDDOUT + 0.5V _ 50 mA + 125oC 50oC/Watt Tj Maximum Junction Temperature Thermal Resistance, Junction to Case Product information is current as of publication date. The product conforms to specifications per the terms of the Pletronics standard warranty. Production processsing does not necessarily include testing of all parameters. Copyright (c) 2007, 2008, Pletronics Inc. FD7T Series Multi-Output CMOS Clock Oscillator May 2008 BLOCK DIAGRAMS OF THE FD7T SERIES FD73xxT Vdd 1.8V (1) Vddout (5) Reference oscillator optional Voltage controlled PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Vcontrol (2) MUX #1 Divider #1 /1 to /1023 Y1 (11) Out1 Divider #2 /1 to /127 Divider #3 /1 to /127 MUX #2 Y2 (10) Out2 S0 (14) Programming control eePROM SDA/SCL Registers S1/SDA (13) S2/SCL (12) MUX #3 Y3 (9) Out3 Ground (3) Sx Control FD74xxT Vdd 1.8V (1) Vddout (5) Reference oscillator optional Voltage controlled MUX #1 Divider #1 /1 to /1023 Y1 (11) Out1 Vcontrol (2) PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Divider #2 /1 to /127 Divider #3 /1 to /127 MUX #2 Y2 (10) Out2 S0 (14) Programming control eePROM SDA/SCL Registers PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode MUX #3 Divider #4 /1 to /127 Divider #5 /1 to /127 MUX #4 Y3 (9) Out3 S1/SDA (13) S2/SCL (12) Y5 (4) Out4 Ground (3) Sx Control www.pletronics.com 425-776-1880 2 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 FD75xxT Vdd 1.8V (1) MUX #1 Vddout (5) Reference oscillator optional Voltage controlled Divider #1 /1 to /1023 (11) Out1 Y1 Vcontrol (2) PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Divider #2 /1 to /127 Divider #3 /1 to /127 MUX #2 Y2 (10) Out2 MUX #3 S0 (14) Programming control eePROM SDA/SCL Registers Sx Control Ground (3) PLL Multiplier #3 optional Spread Spectrum optional Bypass Mode PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode Divider #4 /1 to /127 Divider #5 /1 to /127 MUX #4 Y3 (9) Out3 S1/SDA (13) S2/SCL (12) Y5 (4) Out4 Divider #6 /1 to /127 Divider #7 /1 to /127 MUX #5 Y7 (8) Out5 FD77xxT (11) Out1 Vdd 1.8V (1) Vddout (5) PLL Multiplier #1 optional Spread Spectrum optional Bypass Mode Reference oscillator optional Voltage controlled MUX #1 Divider #1 /1 to /1023 Y1 Divider #2 /1 to /127 Divider #3 /1 to /127 MUX #2 Y2 (10) Out2 MUX #3 PLL Multiplier #2 optional Spread Spectrum optional Bypass Mode Divider #4 /1 to /127 Divider #5 /1 to /127 MUX #4 Y3 (9) Out3 Vcontrol (2) Y5 (4) Out4 S0 (14) Programming control eePROM SDA/SCL Registers Sx Control S1/SDA (13) S2/SCL (12) PLL Multiplier #3 optional Spread Spectrum optional Bypass Mode Divider #6 /1 to /127 Divider #7 /1 to /127 MUX #5 Y7 (8) Out5 MUX #6 PLL Multiplier #4 optional Spread Spectrum optional Bypass Mode Divider #8 /1 to /127 Divider #9 /1 to /127 MUX #7 Y8 (6) Out6 Ground (3) Y9 (7) Out7 www.pletronics.com 425-776-1880 3 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Description: The FD7T series Multi-Output CMOS Clock Oscillator is a modular PLL-based low cost, high-performance, programmable oscillator. The FD7T generates up to seven output frequencies, OUT1 through OUT7. Frequencies are mutually independent and may be programmed to any frequency from 100KHz to 230MHZ and one output can be as low as 12KHz. There are versions including 1 to 4 PLLs, the number of PLLs impacts the cost. The FD7T base frequency, as noted in the device part number, is established during manufacture and is permanently fixed. For convenience, the divider for output OUT1 and the remaining seven output frequencies, and their characteristics may be pre-programmed at the factory, or field programmed. The FD7T has a separate output supply pin, VDDOUT, for either 1.8, 2.5 or 3.3V output logic levels. The device supply, VDD which provides power to all the internal circuits, is nominally 1.8V. The FD7xxxTL version has increased output drive for then 1.8V output levels. This version can be used at 1.8V VDDOUT only. The deep M/N PLL divider ratio allows the generation of zero-ppm clocks for applications such as WLAN, BlueTooth, Ethernet, GPS, USB, IEEE1394, etc. from the base frequency. Each of the independent PLLs supports Spread Spectrum Clocking (SSC). SSC may be programmed to be either center-spread or down-spread. This is an important technique to reduce electro-magnetic interference (EMI). The device supports non-volatile eePROM programming for easy customization of the device. As shipped, the device is pre-programmed. Standard combinations are denoted by three characters in the device part number. However, the FD7T may be reprogrammed to a different configuration. Reprogramming may be either prior to assembly, or in-circuit via a 2-wire SDA/SCL I2C bus. Three programmable control inputs, S0, S1 and S2, may be used to control various aspects of FD7T operation including selection of alternative frequency set(s), selection of SSC functionality, output tri-state and power-down. Reference Oscillator The Reference Oscillator is an AT cut quartz crystal based oscillator. This oscillator is very similar to the Pletronics SM77xxH product oscillator. This signal is the lowest jitter and can be an output on Out1, Out2 or Out3 and can be divided down by the Divider #1. The user may specify any frequency between 12MHz and 32MHz for this reference. All output frequencies are derived from (referenced to) this Reference Oscillator. Reference Oscillator - VCXO The reference oscillator frequency can be modulated by the Vcontrol input, if the VCXO option is selected. As this Reference Signal is the reference for all other parts of this circuit, all PLLs will be modulated also. The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range that changes the frequency will still be limited but the larger voltages swings will not cause problems. www.pletronics.com 425-776-1880 4 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 PLL Multipliers There are up to 4 each independent PLL Multipliers and these can multiply the Reference Oscillator frequency from 1 (bypass mode) to any value that is <=230MHz (the lowest frequency is the Reference Oscillator frequency). Each of the PLL Multipliers can have two setup options, 0 or 1, depending on which option is chosen and set by the Sx control signals and the user's definitions are stored in eePROM. Spread Spectrum Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the modulation of the output frequency by a user-set amount. The modulation can be centered on the output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input and the user definition. The value is a percentage of the output frequency that will be modulated. SS Option 0 1 2 3 4 5 6 7 Down Side Modulation No SS -0.25% -0.50% -0.75% -1.00% -1.25% -1.50% -2.00% Centered Modulation No SS +0.25% _ +0.50% _ +0.75% _ +1.00% _ +1.25% _ +1.50% _ +2.00% _ Divider Section The dividers operate on the output of the PLLs. There are two dividers on each PLL that divide by 1 through 127, the value is user defined. There is only 1 setting allowed per divider. These are not set by the Sx input state. The dividers add very little jitter to the output signals. Multiplexers MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from PLL Multiplier #1. MUX #2 through MUX #7 connect various divider outputs to the output buffers. The device can make only one of the setting of connections shown in the block diagram (only one pattern stored in eePROM). www.pletronics.com 425-776-1880 5 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Output Buffers Each output buffer can have 3 modes of operation: 1) Tri State 2) Active Low 3) The signal output of the Multiplexer The output buffers for Out2 and Out3 and the output buffers Out6 and Out7 function as pairs. When selecting on the function both outputs in the pair function the same. There can be two options stored for the Output Buffers, State 0 and State 1. The eight Sx input settings can have assigned one of the two Output Buffer states for each of Output Buffer sets. This permits wired `OR' of tri-state outputs, this permits setting total enable and disable functions of all outputs. Control Inputs The three inputs, S0, S1/SDA and S2/SCL can be configured in two ways. 1) Used as 3 user inputs to permit up to 8 states, Sx input setting. 2) S0 used as an input to permit up to 2 states, S0 input setting. The SDA and SCL become clock and data inputs to write to the FD7T internal setting memory. The interface follows the I2C protocol. If the SDA and SCL are not set then the internal eePROM sets the operation. The S0, S1 and S2 input signals control and variations states allowed: Inputs S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 PLL #1 SS 0/7 0/7 0/7 0/7 0/7 0/7 0/7 0/7 PLL 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 PLL #2 SS 0/7 0/7 0/7 0/7 0/7 0/7 0/7 0/7 PLL 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 PLL #3 SS 0/7 0/7 0/7 0/7 0/7 0/7 0/7 0/7 PLL 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 PLL #4 SS 0/7 0/7 0/7 0/7 0/7 0/7 0/7 0/7 PLL 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 3 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Output 4 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 5 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 6 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 7 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 The MUX inputs are fixed independent of the Sx setting. The Divider Values are fixed independent of the Sx setting Specifying The FD7T Device For A Specific Application Pletronics provides an EXCEL spreadsheet based program that assists in defining the FD77T functions. The program only permits setting of parameters that will properly function. After defining the desired functions, this spreadsheet is sent to Pletronics and the Configuration Part Number will then be assigned. Pletronics uses the values in the spreadsheet to program the devices for shipment. www.pletronics.com 425-776-1880 6 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 PART NUMBER: FD7 7 45 T L E -25.0M -YYY -XX Packaging code or blank T250 = 250 per Tape and Reel T500 = 500 per Tape and Reel T1K = 1000 per Tape and Reel Configuration Number This is a 3 character alpha-numeric code issued by Pletronics that defines the FD77T function (the output pin functions, the available frequencies and the pin number assignments). Each configuration is given a unique value. Base Frequency (Crystal oscillator frequency) in MHZ Optional Enhanced Operating temperature Range Blank = Temp. range -20oC to +70oC E = Temp. range -40oC to +85oC Blank = VDDOUT 3.3V, 2.5V and 1.8V device L = VDDOUT 1.8V only high output drive level device Series Model Frequency Stability for fixed frequency oscillator 45 = + 50 ppm _ 15 = + 15 ppm _ 44 = + 25 ppm _ 10 = + 10 ppm _ 20 = + 20 ppm _ Frequency Pull Ability for VCXO option enabled 99 = + 100 ppm Absolute Pull Range (APR) _ 75 = _ 25 ppm Absolute Pull Range (APR) + 50 = _ 50 ppm Absolute Pull Range (APR) + 7 = 7 outputs 5 = 5 outputs 4 = 4 outputs 3 = 3 outputs Series Model 4 PLL version 3 PLL version 2 PLL version 1 PLL version Part Marking: PLE FD7x ZZZ YMD PLE = Pletronics ZZZ = configuration All other marking is internal factory codes Marking Legend: X YMD = = Model type Date of Manufacture (year-month-day) Codes for Date Code YMD Code 8 9 0 1 2 Code A B C D E F G H J K L M Year 2008 2009 2010 2011 2012 Month JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC Code Day Code Day 1 1 H 17 2 2 J 18 3 3 K 19 4 4 L 20 5 5 M 21 6 6 N 22 7 7 P 23 8 8 R 24 9 9 T 25 A 10 U 26 B 11 V 27 C 12 W 28 D 13 X 29 E 14 Y 30 F 15 Z 31 G 16 www.pletronics.com 425-776-1880 7 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Electrical Specification over the specified temperature range Item Base Frequency Frequency Range OUT1 Frequency Range OUT2 - 7 Frequency Accuracy "45" "44" "20" Recommended Operating Conditions Device Supply Voltage VDD Output Supply Voltage VDDOUT Output Supply Voltage "L" VDDOUT Low Level Input voltage High Level Input voltage Input Voltage Range, S0 If 1K ohm in series with S0 pad Input Voltage Range, S1, S2 Input current for: S0 with 1K ohm in series S0, S1, S2 1.7 1.7 1.7 -70 0 -1 0 0 0 -4 Output Current, VDDOUT = 3.3V Output Current, VDDOUT = 2.5V Output Current, VDDOUT = 1.8V Output Current "L", VDDOUT = 1.8V Output Load, LVCMOS -12 -10 -5 -8 -1.9 3.6 1.9 30 -1.9 4.0 3.6 3 5 0 +12 +10 +5 +8 10 V V V % % V V mA A A mA mA mA mA pf Higher loads can be used of VDD of VDD VTH is 0.5 * VDD VTH is 0.5 * VDD VIN = 4V; VDD = 1.8V VIN = VDD; VDD = 1.9V VIN = 0.0VD; VDD = 1.9V Min 12 0.0117 0.0945 -50 -25 -20 Max 32 230 230 +50 +25 +20 Unit MHZ MHZ MHZ ppm For all supply voltages, load changes, aging for 1 year, shock, vibration and temperatures Base Frequency / (1 to 1023) -or- PLL1 Condition LVCMOS Output Parameters for VDDOUT = 3.3v Output High, VDDOUT = 3.3V 2.9 2.4 2.2 Output Low, VDDOUT = 3.3V ---Rise & Fall Time Output Symmetry -45 ---0.1 0.5 0.8 0.6 55 V V V V V V nS % IOH = -0.1 mA IOH = -8.0 mA IOH = -12.0 mA IOH = +0.1 mA IOH = +8.0 mA IOH = +12.0 mA VDDOUT = 3.3v, 20 - 80%, 10pF Load at 50% point of VDDOUT www.pletronics.com 425-776-1880 8 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Item Peak-to-Peak Jitter (1)(2) Min --- Max 100 180 90 170 60 160 Unit pS pS pS pS pS pS Condition 1 PLL Switching 4 PLLs Switching 1 PLL Switching 4 PLLs Switching OUT1 to OUT2 OUT3 to OUT7 Cycle-to-Cycle Jitter (1)(2) --- Output Skew --- LVCMOS Output Parameters for VDDOUT = 2.5v Output High, VDDOUT = 2.5V 2.2 1.7 1.6 Output Low, VDDOUT = 2.5V ---Rise & Fall Time Output Symmetry Peak-to-Peak Jitter (1)(2) ---0.1 0.5 0.7 0.6 55 100 180 90 170 60 160 V V V V V V nS % pS pS pS pS pS pS IOH = -0.1 mA IOH = -6.0 mA IOH = -10.0 mA IOH = +0.1 mA IOH = +6.0 mA IOH = +10.0 mA VDDOUT = 2.5v, 20 - 80%, 10pF Load at 50% point of VDDOUT 1 PLL Switching 4 PLLs Switching 1 PLL Switching 4 PLLs Switching OUT1 to OUT2 OUT3 to OUT7 -45 --- Cycle-to-Cycle Jitter (1)(2) --- Output Skew --- LVCMOS Output Parameters for VDDOUT = 1.8v Output High, VDDOUT = 1.8V 1.6 1.4 1.1 Output Low, VDDOUT = 1.8V ---Rise & Fall Time Output Symmetry Peak-to-Peak Jitter (1)(2) ---0.1 0.3 0.6 0.9 55 140 190 120 170 V V V V V V nS % pS pS pS pS IOH = -0.1 mA IOH = -3.0 mA IOH = -6.0 mA IOH = +0.1 mA IOH = +3.0 mA IOH = +6.0 mA VDDOUT = 1.8v, 20 - 80%, 10pF Load at 50% point of VDDOUT 1 PLL Switching 4 PLLs Switching 1 PLL Switching 4 PLLs Switching -45 --- Cycle-to-Cycle Jitter (1)(2) --- www.pletronics.com 425-776-1880 9 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Item Output Skew Min --LVCMOS Output Parameters for VDDOUT = 1.8v Output High, VDDOUT = 1.8V 1.6 1.4 1.1 Output Low, VDDOUT = 1.8V ---Rise & Fall Time Output Symmetry Peak-to-Peak Jitter (1)(2) Max 60 160 "L" Version ---0.1 0.3 0.6 0.7 Unit pS pS Condition OUT1 to OUT2 OUT3 to OUT7 V V V V V V nS % pS pS pS pS pS pS IOH = -0.1 mA IOH = -4.0 mA IOH = -8.0 mA IOH = +0.1 mA IOH = +4.0 mA IOH = +8.0 mA VDDOUT = 1.8v, 20 - 80%, 10pF Load at 50% point of VDDOUT 1 PLL Switching 4 PLLs Switching 1 PLL Switching 4 PLLs Switching OUT1 to OUT2 OUT3 to OUT7 45 --- 55 140 190 120 170 60 160 Cycle-to-Cycle Jitter (1)(2) --- Output Skew --- VCXO Function Vcontrol Input Range Usable Vcontrol Input Range Allowed - Direct connect to Vcontrol - Limit current to + 3mA _ Pull Ability specified in the P.N. Linearity -10 +10 % 0.5 0.0 -1.0 VDD - 0.5V VDD 4.0 V V The slope is positive The slope is positive Recommend >=1K ohm to Vcontrol (1) 10,000 cycles (2) Jitter depends on the device configuration. Data is taken under the following conditions: 1-PLL; 27MHz Crystal, Out2 and Out3 are 27MHz (measured at Out2). 4-PLL; 27MHz Crystal, Out2 and Out3 are 27MHz (measured at Out2). Out4 is 16.384MHz, Out5 is 74.25MHz, Out6 and Out7 are 48MHz. Frequency Tolerance: For the FD7x15T and the FD7x10T devices, Pletronics recommends that the tight tolerance be required on the PLL outputs only. In this case the reference frequency output would only achieve 25ppm tolerance. This will reduce the cost of the device. www.pletronics.com 425-776-1880 10 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 FD7xxxT VDDOUT=3.3V 30 25 IDDOUT Current for Various Number of Outputs On No Load VDDOUT=2.5V 20 18 16 VDD=1.8V VDDOUT=1.8V 14 12 Idd out (mA) 10 8 6 4 2 0 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off Idd out (mA) Idd out (mA) 20 15 10 5 0 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 14 12 10 8 6 4 2 0 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) FD7xxxTL VDD = VDDOUT=1.8V No Load 10 9 8 Idd out (mA) 7 6 5 4 3 2 1 0 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off Idd Current (mA) 90 80 70 60 50 40 30 20 10 0 10 FD7 Series IDD versus PLLs Used VDD=1.8V 4 PLLs On 3 PLLs On 2 PLLs On 1 PLL On All PLLs Off 30 50 70 90 110 130 150 170 190 210 230 PLL Frequency (MHz) Phase noise of the reference signal, Out1. 25MHz Reference Frequency RMS jitter is 1.4pS from 10Hz to 2MHz Example of the PLL synthesizing a frequency. 25MHz Reference Frequency Multiply by 8 to 200MHz Divide the 200MHz PLL output by 8 Phase noise plot of the resulting 25MHz on Out 2 www.pletronics.com 425-776-1880 11 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Load Circuit and Test Waveform Symmetry Vhigh 90% * Vcc 50% * Vcc 10% * Vcc Vlow Ground Trise Tfall Reliability: Environmental Compliance Parameter Mechanical Shock Vibration Solderability Thermal Shock Condition MIL-STD-883 Method 2002, Condition B MIL-STD-883 Method 2007, Condition A MIL-STD-883 Method 2003 MIL-STD-883 Method 1011, Condition A ESD Rating Model Human Body Model Charged Device Model Minimum Voltage 1500 1000 Conditions MIL-STD-883 Method 3115 JESD 22-C101 www.pletronics.com 425-776-1880 12 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Mechanical: Inches 14 1 13 1 12 mm 7.00 +0.15 _ 5.00 +0.15 _ 1.70 max 1.27 1.27 0.10 1.00 0.63 0.50 0.10r 0.20r A B C D 1 0.276 +0.006 _ 0.197 +0.006 _ 0.067 max 0.050 0.050 0.004 0.039 0.025 0.020 0.004r 0.008r 2 3 11 10 E1 F1 G1 4 8 5 6 7 8 H1 I1 1 Contacts: Gold 11.8 inches 0.3 m minimum over Nickel 50 to 350 inches 1.27 to 8.89 m Typical dimensions J1 K1 Not to Scale Package Labeling Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Courier New Bar code is 39-Full ASCII Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Arial www.pletronics.com 425-776-1880 13 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD73xxT: Pad Function Note Output Function O t h e r S S C S S D 1 2 3 4 5 6 7 8 9 Vsupply1 Vcontrol Ground (GND) n.c. Vsupply2 n.c. n.c. n.c. Out3 (Y3) 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. Frequency control input when the VCXO function is enabled No connection or connect to ground (do not connect to a signal lead) 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. No connection or connect to ground (do not connect to a signal lead) No connection or connect to ground (do not connect to a signal lead) No connection or connect to ground (do not connect to a signal lead) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 PLL1 frequency divider 3 and divided by 1 through 127 X X X X X X X X X X X X X X X X X 10 Out2 (Y2) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 11 Out1 (Y1) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 1 and divided by 1 through 1023 12 13 14 S2 / SCL S1 / SDA S0 Serial Data Clock Serial Data S2 S1 S0 Input to select 1 of 8 preprogrammed functions of the outputs Other Logic "0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 14 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD74xxT: Pad Function Note Output Function O t h e r S S C S S D 1 2 3 4 Vsupply1 Vcontrol Ground (GND) 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. Frequency control input when the VCXO function is enabled PLL1 frequency divider 2 and divided by 1 through 127 Out4 (Y5) PLL2 frequency divider 4 and divided by 1 through 127 PLL2 frequency divider 5 and divided by 1 through 127 5 6 7 8 9 Vsupply2 n.c. n.c. n.c. Out3 (Y3) 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. No connection or connect to ground (do not connect to a signal lead) No connection or connect to ground (do not connect to a signal lead) No connection or connect to ground (do not connect to a signal lead) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 PLL1 frequency divider 3 and divided by 1 through 127 10 Out2 (Y2) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 11 Out1 (Y1) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 1 and divided by 1 through 1023 12 13 14 S2 / SCL S1 / SDA S0 Serial Data Clock Serial Data S2 S1 S0 X X X X X X X X X X X X X X X X X X X X Input to select 1 of 8 preprogrammed functions of the outputs Other Logic "0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 15 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD75xxT: Pad Function Note Output Function O t h e r S S C S S D 1 2 3 4 Vsupply1 Vcontrol Ground (GND) 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. Frequency control input when the VCXO function is enabled PLL1 frequency divider 2 and divided by 1 through 127 Out4 (Y5) PLL2 frequency divider 4 and divided by 1 through 127 PLL2 frequency divider 5 and divided by 1 through 127 5 6 7 8 Vsupply2 n.c. n.c. Out5 (Y7) 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. No connection or connect to ground (do not connect to a signal lead) No connection or connect to ground (do not connect to a signal lead) PLL2 frequency divider 4 and divided by 1 through 127 PLL3 frequency divider 6 and divided by 1 through 127 PLL3 frequency divider 7 and divided by 1 through 127 9 Out3 (Y3) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 PLL1 frequency divider 3 and divided by 1 through 127 10 Out2 (Y2) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 11 Out1 (Y1) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 1 and divided by 1 through 1023 12 13 14 S2 / SCL S1 / SDA S0 Serial Data Clock Serial Data S2 S1 S0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Input to select 1 of 8 preprogrammed functions of the outputs Other Logic "0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 16 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Pad Functions FD77xxT: Pad Function Note Output Function O t h e r S S C S S D 1 2 3 4 Vsupply1 Vcontrol Ground (GND) 1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the package pin. Frequency control input when the VCXO function is enabled PLL1 frequency divider 2 and divided by 1 through 127 Out4 (Y5) PLL2 frequency divider 4 and divided by 1 through 127 PLL2 frequency divider 5 and divided by 1 through 127 5 6 Vsupply2 Out6 (Y8) 1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass capacitor required near the package pin. PLL3 frequency divider 6 and divided by 1 through 127 PLL4 frequency divider 8 and divided by 1 through 127 7 Out7 (Y9) PLL3 frequency divider 6 and divided by 1 through 127 PLL4 frequency divider 8 and divided by 1 through 127 PLL4 frequency divider 9 and divided by 1 through 127 8 Out5 (Y7) PLL2 frequency divider 4 and divided by 1 through 127 PLL3 frequency divider 6 and divided by 1 through 127 PLL3 frequency divider 7 and divided by 1 through 127 9 Out3 (Y3) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 PLL1 frequency divider 3 and divided by 1 through 127 10 Out2 (Y2) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 2 and divided by 1 through 127 11 Out1 (Y1) Crystal reference frequency divider 1 and divided by 1 through 1023 PLL1 frequency divider 1 and divided by 1 through 1023 12 13 14 S2 / SCL S1 / SDA S0 Serial Data Clock Serial Data S2 S1 S0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Input to select 1 of 8 preprogrammed functions of the outputs Other Logic "0" or tri-stated (off) SSC The output can have a spread spectrum centered about the output frequency. SSD The output can have a spread spectrum from the output frequency downward. All unused inputs should be pulled high. www.pletronics.com 425-776-1880 17 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 Reflow Cycle (typical for lead free-processing) Temperature (C) 250 200 150 100 175C10C 260C Maximum 10 Seconds Maximum 215C10C 120 to 160 Seconds Approximately 50 Seconds Allowed rate of temperature change Maximum 4C per second The part may be reflowed 2 times without degradation. Tape and Reel: available for quantities of 250 to 1000 per reel, cut tape for < 250 Constant Dimensions Table 1 Tape Size 8mm 12mm 16mm 24mm 1.5 +0.1 -0.0 D1 Min 1.0 1.75 1.5 _0.1 + 1.5 1.5 _ +0.1 2.0 _0.1 + 4.0 0.6 0.6 0.1 S1 Min T Max T1 Max D0 E1 P0 P2 2.0 _ +0.05 Variable Dimensions Table 2 Tape Size 16 mm B1 Max 12.1 E2 Min F P1 T2 Max 8.0 W Max 16.3 Ao, Bo & Ko Note 1 Not to scale 14.25 7.5 _0.1 + 8.0 +0.1 _ Note 1: Embossed cavity to conform to EIA-481-B REEL DIMENSIONS A inches mm B inches mm C D mm mm 16.4 +2.0 -0.0 7.0 177.8 2.50 63.5 10.0 254.0 4.00 101.6 13.0 +0.5 / -0.2 16.4 +2.0 -0.0 16.4 +2.0 -0.0 16.0 13.0 330.2 3.75 95.3 Tape Width Reel dimensions may vary from the above www.pletronics.com 425-776-1880 18 FD7T Series Multi-Output CMOS Clock Oscillator May 2008 IMPORTANT NOTICE Pletronics Incorporated (PLE) reserves the right to make corrections, improvements, modifications and other changes to this product at any time. PLE reserves the right to discontinue any product or service without notice. Customers are responsible for obtaining the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to PLE's terms and conditions of sale supplied at the time of order acknowledgment. PLE warrants performance of this product to the specifications applicable at the time of sale in accordance with PLE's limited warranty. Testing and other quality control techniques are used to the extent PLE deems necessary to support this warranty. Except where mandated by specific contractual documents, testing of all parameters of each product is not necessarily performed. PLE assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using PLE components. To minimize the risks associated with the customer products and applications, customers should provide adequate design and operating safeguards. PLE products are not designed, intended, authorized or warranted to be suitable for use in life support applications, devices or systems or other critical applications that may involve potential risks of death, personal injury or severe property or environmental damage. Inclusion of PLE products in such applications is understood to be fully at the risk of the customer. Use of PLE products in such applications requires the written approval of an appropriate PLE officer. Questions concerning potential risk applications should be directed to PLE. PLE does not warrant or represent that any license, either express or implied, is granted under any PLE patent right, copyright, artwork or other intellectual property right relating to any combination, machine or process which PLE product or services are used. Information published by PLE regarding third-party products or services does not constitute a license from PLE to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from PLE under the patents or other intellectual property of PLE. Reproduction of information in PLE data sheets or web site is permissible only if the reproduction is without alteration and is accompanied by associated warranties, conditions, limitations and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. PLE is not responsible or liable for such altered documents. Resale of PLE products or services with statements different from or beyond the parameters stated by PLE for that product or service voids all express and implied warranties for the associated PLE product or service and is an unfair or deceptive business practice. PLE is not responsible for any such statements. Contacting Pletronics Inc. Pletronics Inc. 19013 36th Ave. West Lynnwood, WA 98036-5761 USA Tel: 425-776-1880 Fax: 425-776-2760 E-mail: ple-sales@pletronics.com URL: www.pletronics.com Copyright (c) 2007, 2008 Pletronics Inc. www.pletronics.com 425-776-1880 19 |
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