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| HD74LV4040A 12-stage Binary Counter REJ03D0337-0200Z (Previous ADE-205-282 (Z)) Rev.2.00 Jul. 20, 2004 Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and highspeed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features * * * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Package Type SOP-16 pin (JEITA) SOP-16 pin (JEDEC) TSSOP-16 pin Package Code FP-16DAV FP-16DNV TTP-16DAV Package Abbreviation FP RP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Part Name HD74LV4040AFPEL HD74LV4040ARPEL HD74LV4040ATELL Note: Please consult the sales office for the above package availability. Function Table Inputs CLK X Note: H: L: X: : : High level Low level Immaterial Low to high transition High to low transition CLR L L H Output Qn Remains unchanged Changed All outputs low Rev.2.00 Jul. 20, 2004 page 1 of 10 HD74LV4040A Pin Arrangement Q12 1 Q6 Q5 Q7 Q4 Q3 Q2 2 3 4 5 6 7 16 VCC 15 Q11 14 Q10 13 Q8 12 Q9 11 CLR 10 9 Q1 GND 8 (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at 3 Ta = 25C (in still air)* Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 785 500 -65 to 150 Unit V V V mA mA mA mA mW C Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C. Rev.2.00 Jul. 20, 2004 page 2 of 10 HD74LV4040A Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions IOL A mA Input transition rise or fall rate t /v ns/V H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Operating free-air temperature Ta C Note: Unused or floating inputs must be held high or low. Rev.2.00 Jul. 20, 2004 page 3 of 10 HD74LV4040A Logic Diagram CLR (11) (10) R T (9) R Q1 T (4) Q7 R T (7) R Q2 T (13) Q8 R T (6) R Q3 T (12) Q9 R T (5) R Q4 T (14) Q 10 R T (3) R Q5 T (15) Q 11 R T (2) R Q6 T (1) Q 12 Rev.2.00 Jul. 20, 2004 page 4 of 10 HD74LV4040A Timing Diagram 1 2 3 4 8 16 32 64 128 256 512 1024 2048 4096 CLR Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 CLEAR COUNT CLEAR DC Electrical Characteristics Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCCx0.7 VCCx0.7 VCCx0.7 -- -- -- -- VCC-0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.7 Max -- -- -- -- 0.5 VCCx0.3 VCCx0.3 VCCx0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions VIL Output voltage VOH V IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND VOL Input current Quiescent supply current Output leakage current Input capacitance IIN ICC IOFF CIN A A A pF Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Jul. 20, 2004 page 5 of 10 HD74LV4040A Switching Characteristics VCC = 2.5 0.2 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Propagation delay time skew Setup time Pulse width tpd tSU tw Min 50 30 -- -- -- -- -- 7.0 7.0 7.0 Typ 90 60 10.0 12.7 9.9 11.8 3.0 -- -- -- Max -- -- 16.0 19.6 15.4 18.0 5.5 -- -- -- Ta = -40 to 85C Min 40 25 1.0 1.0 1.0 1.0 -- 7.0 7.0 7.0 Max -- -- 18.3 22.2 17.5 20.4 6.3 -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK CLR Qn Q1 ns ns ns Qn+1 CLR inactive before CLK CLK high or low CLR high VCC = 3.3 0.3 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Propagation delay time skew Setup time Pulse width tpd tSU tw Min 75 55 -- -- -- -- -- 5.0 5.0 5.0 Typ 140 80 7.5 10.0 8.3 10.8 2.4 -- -- -- Max -- -- 11.9 15.4 12.8 16.3 4.4 -- -- -- Ta = -40 to 85C Min 70 50 1.0 1.0 1.0 1.0 -- 5.0 5.0 5.0 Max -- -- 14.0 17.5 15.0 18.5 5.0 -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK CLR Qn Q1 ns ns ns Qn+1 CLR inactive before CLK CLK high or low CLR high Rev.2.00 Jul. 20, 2004 page 6 of 10 HD74LV4040A Switching Characteristics (Cont.) VCC = 5.0 0.5 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Propagation delay time skew Setup time Pulse width tpd tSU tw Min 150 95 -- -- -- -- -- 5.0 5.0 5.0 Typ 210 125 4.8 6.3 5.6 7.1 1.6 -- -- -- Max -- -- 7.3 9.3 8.6 10.6 3.1 -- -- -- Ta = -40 to 85C Min 125 80 1.0 1.0 1.0 1.0 -- 5.0 5.0 5.0 Max -- -- 8.5 10.5 10.0 12.0 3.5 -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK CLR Qn Q1 ns ns ns Qn + 1 CLR inactive before CLK CLK high or low CLR high Operating Characteristics CL = 50 pF Ta = 25C Item Power dissipation capacitance Symbol CPD VCC = (V) 3.3 5.0 Min -- -- Typ 17.3 19.0 Max -- -- Unit pF Test Conditions f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC = (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.4 -0.5 3.0 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions Rev.2.00 Jul. 20, 2004 page 7 of 10 HD74LV4040A Test Circuit Measurement point CL * Note: C L includes the probe and jig capacitance. Waveform - 1 tf 90% 50% VCC 10% tr VCC GND tW 1/fmax tPLH tPHL tW Q1 50% VCC Waveform - 2 VCC 50% VCC GND tsu tW CLR 50% VCC VCC GND tPHL Any Q 50% VCC Rev.2.00 Jul. 20, 2004 page 8 of 10 HD74LV4040A Package Dimensions As of January, 2003 10.06 10.5 Max 16 9 Unit: mm 1 *0.20 0.05 8 0.80 Max 5.5 0.20 7.80 + 0.30 - 2.20 Max 1.15 1.27 0.10 0.10 0 - 8 0.70 0.20 *0.40 0.06 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g *Ni/Pd/Au plating As of January, 2003 Unit: mm 9.9 10.3 Max 16 9 1 1.27 0.635 Max 8 0.11 0.14 + 0.04 - 1.75 Max 3.95 *0.20 0.05 0.10 6.10 + 0.30 - 1.08 0 - 8 0.67 0.60 + 0.20 - *0.40 0.06 0.15 0.25 M *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Rev.2.00 Jul. 20, 2004 page 9 of 10 HD74LV4040A As of January, 2003 Unit: mm 5.00 5.30 Max 16 9 1 *0.20 0.05 8 0.65 0.13 M 0.65 Max 6.40 0.20 0 - 8 0.50 0.10 1.0 4.40 *0.15 0.05 1.10 Max 0.10 0.07 +0.03 -0.04 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-16DAV -- -- 0.05 g Rev.2.00 Jul. 20, 2004 page 10 of 10 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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