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| HV2303 Low Charge Injection, 8-Channel High Voltage Analog Switch with Bleed Resistors Features HVCMOS technology for high performance Integrated bleed resistors on the outputs 3.3V or 5.0V CMOS input logic level 20MHz data shift clock frequency Very low quiescent power dissipation - 10A Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5.0MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages General Description The Supertex HV2303 is a low charge injection 8-channel high voltage analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Data is input into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-140V, +90V/-90V, and +140V/-40V. Applications Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules Block Diagram LATCHES D LE CLR LEVEL OUTPUT SHIFTERS & SWITCHES CHARGE CONTROL SW0 CLK D LE CLR SW1 DIN 8-BIT SHIFT REGISTER D LE CLR SW2 DOUT D LE CLR SW6 D LE CLR SW7 VDD GND LE CLR VNN VPP RGND HV2303 Ordering Information Package Options Device 48-Lead LQFP 7x7mm body, 1.6mm height (max), 0.50mm pitch Pin Configurations 28-Lead PLCC .453x.453in body, .180in height (max.), .050in pitch HV2303 HV2303FG-G HV2303PJ-G 48 1 -G indicates package is RoHS compliant (`Green') 48-Lead LQFP (FG) 4 1 28 26 Absolute Maximum Ratings Parameter VDD logic supply VPP-VNN differential supply VPP positive supply VNN negative supply Logic input voltage Analog signal range Peak analog signal current/channel Storage temperature Thermal resistance (ja): 48-Lead LQFP (FG) Value -0.5V to +7.0V 200V -0.5V to VNN+200V +0.5V to -180V -0.5V to VDD +0.3V VNN to VPP 1.0A -65C to 150C 61OC/W 28-Lead PLCC (PJ) Product Marking Top Marking YYWW HV2303FG LLLLLLLLL Bottom Marking CCCCCCCC AAA Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking Operating Conditions Sym VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input voltage Low-level input voltage Analog signal voltage peak-to-peak Operating free air temperature Value 3.0V to 5.5V 40V to VNN +180V -40V to -140V 0.9VDD to VDD 0V to 0.1VDD VNN +10V to VPP -10V 0OC to 70OC YYWW 48-Lead LQFP (FG) Top Marking HV2303PJ LLLLLLLLLL Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging *May be part of top marking 28-Lead PLCC (PJ) Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 HV2303 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) Sym Parameter 0OC Min Max Min 5.0 300 500 4.0 10 10 20 1.0 1.0 1.0 1.0 1.0 1.0 - +25OC +70OC Typ Max Min Max 50 42 40 32 38 29 5.0 30 35 1.0 100 100 10 -10 10 -10 1.2 1.2 1.2 1.2 1.2 1.2 50 10 300 500 50 -50 50 -50 1.0 50 1.5 1.5 1.5 1.5 1.5 1.5 4.0 10 10 0.40 0.40 15 300 500 4.0 10 10 Units Conditions VPP = +40V VNN = -120V ISIG = 200mA VPP = +80V VNN = -80V ISIG = 200mA ISIG = 5.0mA VPP = +120V VNN = -40V ISIG = 200mA % K A mV mV A A A A A kHz ISIG = 5.0mA, VPP = +80V, VNN = -80V VSIG = VPP -10V, ISIG = 0.5A Output switch to RGND IRINT = 0.5mA VSIG = VPP -10V, VNN +10V No load All switches off All switches off All switches on, ISW = 5.0mA All switches on, ISW = 5.0mA VSIG duty cycle <0.1%, 1.0s Duty cycle = 50% VPP = +40V VNN = -120V mA VPP = +80V VNN = -80V VPP = +120V VNN = -40V VPP = +40V VNN = -120V mA VPP = +80V VNN = -80V VPP = +120V VNN = -40V mA A mA mA pF fCLK = 5.0MHz, VDD = 5.0V All logic inputs are static VOUT = VDD -0.7V VOUT = 0.7V --All output switches are turning on and off at 50kHz with no load ISIG = 5.0mA ISIG = 5.0mA RONS Small signal switch on-resistance - RONS RONL RINT ISOL VOS IPPQ INNQ IPPQ INNQ ISW fSW Small signal switch on-resistance matching Large signal switch on-resistance Value of output bleed resistance Switch off leakage per switch DC offset switch off DC offset switch on Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switching frequency - IPP Average VPP supply current - INN Average VNN supply current - IDD IDDQ ISOR ISINK CIN Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Logic input capacitance 0.45 0.45 - 0.45 0.70 0.45 0.70 - 3 HV2303 AC Electrical Characteristics (Over recommended operating conditions: VDD = 5.0V, tR = tF 5ns, 50% duty cycle, CLOAD = 20pF unless otherwise specified) Sym tSD tWLE tDO tWCL tSU tH fCLK tR, tF tON tOFF Parameter Set up time before LE rises Time width of LE Clock delay time to data out Time width of CLR Set up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn on time Turn off time 0OC Min 25 56 12 50 15 55 21 7.0 2.0 Max 100 40 8.0 20 50 5.0 5.0 20 20 20 300 -30 -58 -60 Min 25 50 15 55 2.0 - +25OC Typ 56 12 78 30 21 7.0 -33 -70 6.5 21.7 18 60 30 60 33 60 270 220 152 Max 100 40 8.0 20 50 5.0 5.0 20 20 20 300 - +70OC Min 25 56 12 50 15 55 21 7.0 2.0 -30 -58 -60 Max 100 40 8.0 20 50 5.0 5.0 20 20 20 300 - Units Conditions ns ns ns ns ns ns MHz ns s s --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V --VDD = 3.0V VDD = 5.0V VDD = 3.0 or 5.0V VDD = 3.0V VDD = 5.0V --VSIG = VPP -10V, RLOAD = 10k VSIG = VPP -10V, RLOAD = 10k VPP = +40V, VNN = -120V V/ns VPP = +80V, VNN = -80V VPP = +120V, VNN = -40V dB dB mA pF pF f = 5.0MHz, 1k/15pF load f = 5.0MHz, 50 load f = 5.0MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, f = 1.0MHz 0V, f = 1.0MHz VPP = +40V, VNN = -120V, RLOAD = 50 mV VPP = +80V, VNN = -80V, RLOAD = 50 VPP = +120V, VNN = -40V, RLOAD = 50 VPP = +40V, VNN = -120V, VSIG = 0V pC VPP = +80V, VNN = -80V, VSIG = 0V VPP = +120V, VNN = -40V, VSIG = 0V dv/dt Maximum VSIG slew rate - KO KCR IID Off isolation Switch crosstalk Output switch isolation diode current On capacitance SW to GND -30 -58 -60 - CSG(OFF) Off capacitance SW to GND CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK Output voltage spike QC Charge injection - 4 HV2303 Truth Table D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L L L L H Hold Previous State All Switches Off Off On Off On Off On Off On Off On Off On Off On Off On Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. 5 HV2303 Test Circuits VPP-10V VPP-10V RGND RGND RGND VDD GND VPP VNN VDD GND VPP VNN VDD GND PP VPP VNN PP PP RGND RGND PP PP RGND VPP VNN GND VDD PP VPP VNN VDD GND VPP VNN VDD GND RGND RGND PP VPP VNN VDD GND PP VPP VNN VDD GND 6 HV2303 Pin Configuration - 48-Lead LQFP (FG) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name SW5 NC SW4 NC SW4 NC NC SW3 NC SW3 NC SW2 NC SW2 NC SW1 NC SW1 NC SW0 NC SW0 NC VPP Pin # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D N+1 DATA IN 5 0% Pin Configuration - 28-Lead PLCC (PJ) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name SW3 SW3 SW2 SW2 SW1 SW1 SW0 SW0 NC VPP RGND VNN GND VDD Pin # 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name NC DIN CLK LE CLR DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 VNN NC Pin Name RGND GND VDD NC NC NC DIN CLK LE CLR DOUT NC SW7 NC SW7 NC SW6 NC SW6 NC SW5 NC DN 50% Typical Waveforms DN - 1 LE 50% 50% t WLE t SD 50% 50% th t DO CLOCK t SU DATA O UT 50% t OFF t ON VOUT OFF (TYP ) ON 90% 1 0% CLR 5 0% t WCL 5 0% 7 HV2303 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.6mm height (max.), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane Top View View B A A2 Seating Plane A1 View B Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A 1.40* 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 D 8.80 9.00 9.20 D1 6.80 7.00 7.20 E 8.80 9.00 9.20 E1 6.80 7.00 7.20 e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. 8 HV2303 28-Lead PLCC Package Outline (PJ) .453x.453in body, .180in height (max.), .050in pitch .048/.042 x 45O 4 D D1 1 .056/.042 x 45O 28 26 .150 MAX Note 1 (Index Area) .075 MAX E1 E .020 MAX 3 Places Top View View B b1 A A1 A2 e Base Plane .020 MIN Seating Plane b Side View View B Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (inches) NOM MAX A .165 .172 .180 A1 .090 .105 .120 A2 .062 .083 b .013 .021 b1 .026 .032 D .485 .490 .495 D1 .450 .453 .456 E .485 .490 .495 E1 .450 .453 .456 e .050 BSC JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. (The package drawing (s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP - HV2303 NR042308 9 |
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