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| ML2724 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet GENERAL DESCRIPTION The ML2724 is a fully integrated 1.5Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed 2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all the frequency generation, receive and transmit functions. Automatically adjusted filters eliminate mechanical tuning. Closed loop modulation eliminates frequency drift and permits practically unlimited TX duration. The transmitter generates a 3dBm FSK output signal. The 1.5Mbps data rate permits data spreading, such as Direct Sequence Spread Spectrum (DSSS) modulation, which improves range. The dual conversion Low-IF receiver has all of the sensitivity and selectivity advantages of a traditional super-heterodyne without requiring costly, bulky external filters, while providing the integration advantages of direct conversion. The phase locked loop (PLL) synthesizer is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. This allows the ML2724 to be used in frequency hopped spread spectrum (FHSS) applications. The ML2724 contains internal voltage regulation. It also contains PLL and transmitter configuration registers. The device can be placed in a low power standby mode for current sensitive applications. It is packaged in a "Green" Pb-Free 32TQFP. FEATURES Complete 2.4GHz FSK Transceiver - High data rate (1.5Mbps) - -81dBm sensitivity @ 0.1% BER (typ) - 3dBm Output Power (differential, typ) Closed Loop TX Modulation Low IF Receiver: No external IF filters required. Fully Integrated frequency synthesizer: - No external resonator required. Sigma-Delta Fractional-N two-port modulator Automatic Filter Alignment - No manufacturing adjustments required. No external data slicer components required Control outputs correctly sequence and control PA 3-wire control interface Analog RSSI output APPLICATIONS 2.4GHz FSK Data Transceivers - Digital Cordless Telephones - Wireless PC Peripherals - Wireless Game Controllers - Wireless Streaming Media PIN CONFIGURATION GNDDMD RVQMIF RVDMD DOUT RSSI VBG VDD DIN XCEN RXON PAON EN DATA CLK AOUT VSS 32 31 30 1 2 3 4 5 6 7 8 9 10 11 29 28 27 26 25 24 23 22 21 20 19 18 VCCA RVLO TXOB TXO GNDRXMX2 GNDRXMX GNDRF RXI BLOCK DIAGRAM AOUT RXI 2.4 GHz Receive Input Quadrature Downmixers F to V DOUT Receive Data Out RSSI Test Mux 12 13 14 17 15 16 Filter Alignment RSSI Divide by 2 Quadrature Divider Transmit Mixer TXO/TXOB 2.4 GHz Output Two-port Modulator ORDERING INFORMATION 2 FREF RVPLL QPO GNDPLL VVREG VTUNE RVVCO GND Mode Control TPC PAON RXON XCEN Parallel control lines DIN Transmit Data In Control Registers DATA Serial CLK Control Bus EN FREF Frequency Reference PART # ML2724DH TEMP RANGE o o PACKAGE PACK (QTY) 1.6 GHz VCO Bandgap PLL Divider P.D. -10 C to +60 C 32TQFP 7x7x1mm Antistatic Tray (250) Tape & Reel (2500) VTUNE Ref. Divider ML2724DH-T -10oC to +60 oC 32TQFP 7x7x1mm QPO PLL Loop Filter DS2724-F-03 DECEMBER 2005 ML2724 TABLE OF CONTENTS GENERAL DESCRIPTION ........................................................................................................................................... 1 PIN CONFIGURATION................................................................................................................................................. 1 ORDERING INFORMATION ........................................................................................................................................ 1 FEATURES................................................................................................................................................................... 1 APPLICATIONS............................................................................................................................................................ 1 BLOCK DIAGRAM ........................................................................................................................................................ 1 TABLE OF CONTENTS................................................................................................................................................ 2 SIMPLIFIED APPLICATIONS DIAGRAM..................................................................................................................... 3 ELECTRICAL CHARACTERISTICS............................................................................................................................. 4 PIN DESCRIPTIONS.................................................................................................................................................... 7 FUNCTIONAL DESCRIPTION ................................................................................................................................... 12 MODES OF OPERATION .......................................................................................................................................... 13 DATA INTERFACE ..................................................................................................................................................... 15 CONTROL INTERFACES AND REGISTER DESCRIPTIONS .................................................................................. 17 DATA INTERFACES .................................................................................................................................................. 22 PERFORMANCE GRAPHS........................................................................................................................................ 24 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) ................................................................................................ 25 WARRANTY ............................................................................................................................................................... 26 DS2724-F-03 FINAL DATASHEET DECEMBER 2005 2 ML2724 SIMPLIFIED APPLICATIONS DIAGRAM DOUT PAON 3 ANTENNA PAON DOUT AOUT 32 7 RSSI FREF CLK, DATA, EN 3 BASEBAND IC XCEN, RXON 2 AOUT RSSI 28 LNA RXI 17 RXI FREF DATA 9 5 CLK 6 EN 4 T/R SWITCH RXON 2 XCEN 1 ML2724 TXOB TXO 22 TXOB 21 TXO VTUNE 15 QPO 11 DIN VBG 26 30 DIN VCCA BATTERY AND PROTECTION CIRCUITS PA VTUNE QPO 220nF 150. 220nF 33nF 14 RVVCO Figure 1: Typical ML2724 Application Diagram DS2724-F-03 FINAL DATASHEET DECEMBER 2005 3 ML2724 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. maximum ratings are stress ratings only and functional device operation is not implied. Absolute VCCA, VDD ................................................................................................................................................................. 5.5V Junction Temperature .............................................................................................................................................. 150C Storage Temperature Range...................................................................................................................... -65C to 150C Lead Temperature (Soldering, 10s) ......................................................................................................................... 260C OPERATING CONDITIONS Normal Temperature Range......................................................................................................................... -10C to 60C VCCA Range ...................................................................................................................................................2.7V to 4.5V VDD Range .....................................................................................................................................................2.7V to 3.3V Thermal Resistance (JA)....................................................................................................................................... 70C/W Unless otherwise specified, VCCA=VDD=3.3V, TA=25C, fREF=6.144MHz, Data Rate=1.536Mbps, 13kHz Loop Filter as shown in Figure 1. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS POWER CONSUMPTION VCCA VDD VBG ISTBY IRX ITX Analog supply (VCCA) Digital Supply voltage Bandgap Voltage Supply current, STANDBY mode Supply current, RECEIVE mode Supply current, TRANSMIT mode VDD pin (VCCA VDD always) VBG pin 26, IO=0A DC supply connected, XCEN low RX chain active, data being received POUT=3dBm 2.7 2.7 1.23 10 55 50 120 76 76 3.3 4.5 3.3 V V V A mA mA SYNTHESIZER fC f IP N Carrier frequency range Channel Spacing Charge Pump sink/source current Phase noise at TXO 1.2MHz 3MHz >7MHz Lock time for channel switch Closed loop, loop filter bandwidth 13KHz (See Figure 1) 2.4 2048 +/-5.5 -95 -115 -125 2.485 GHz kHz mA dBc/Hz tFH From EN asserted to RX valid data(RX), or PAON high (TX) 1 Channel 5 Channels Full Range RXON High to Valid RX data RXON Low to PAON high XCEN high to Valid RX data, XCEN low period >120 seconds 110 185 250 70 63 240 125 220 300 120 75 325 s s s s s s tTX2RX tRX2TX tWAKE Lock time for TX/RX Lock time for RX/TX Lock up time from standby DS2724-F-03 FINAL DATASHEET DECEMBER 2005 4 ML2724 SYMBOL fFREF VFREF RECEIVER ZIN NF DRRX S BWRX PIMAX IIP3 IRR Receiver input impedance Receiver noise figure Data Rate Input Sensitivity Bandwidth Maximum RX RF input Receiver Input IP3 LO leakage at RXI Mixer Image Rejection Ratio Adjacent channel rejection Measured at 3.5MHz offset -80dBm wanted signal <10 BER Single 2GFSK modulated interferer with a 1.5MHz -20dBc bandwidth 1 channel away 2 channels away 3 or more channels away -3 PARAMETER Reference signal frequency Reference signal input level CONDITIONS MIN TYP 6.144 12.288 MAX UNITS MHz MHz 6.144MHz or 12.288MHz sine wave, capacitively coupled 2.0 VCCA VPP fc=2445MHz fc=2445MHz FSK modulation, fdev=+/-512kHz <12.5% CER at 1.536Mchip/s <0.1% BER at 1.536Mbps 3dB Bandwidth <12.5% CER at 1.536Mchip/s <0.1% BER at 1.536Mb/s Test tones 2 and 4 channels away +5 -4 -82 2.2+j0 16.5 1.536 -90 -81 770 dB Mbps dBm dBm kHz dBm dBm -15 -60 35 dBm dBm dB 6 31 36 dB dB dB IF FILTERS fIFC BWIF IF filter center frequency IF filter 3dB bandwidth After Automatic Filter Alignment After Automatic Filter Alignment 1.024 1405 MHz kHz LIMITER, AGC, AND FM DEMODULATOR tOVLD Recovery from overload Eb/No Co-Channel rejection, 0.1% BER From +15dBm at input For 0.1% BER -80 dBm, modulated with 1.536Mbps GFSK, BT=0.5, PRBS data 0.55 IO=100A, TPC Mode 5 10.5 10.5 12 s dB dB VODC VOPK VOL Quiescent voltage @ AOUT Output voltage swing AOUT AOUT open-drain voltage 1.1 1.1 0.4 V VPP V RSSI PERFORMANCE tRRSSI tFRSSI GRSMID VRSMX VRSMD RSSI rise time No Signal to -15dBm into the IF mixer RSSI fall time, < -15dBm to No Signal into the IF mixer RSSI sensitivity RSSI maximum voltage RSSI midrange voltage 20pF load, 20% to 80% 20pF load, 20% to 80% (V-40dBm - V-60dBm)/20dB See Figure 3 -40dBm into RXI 28 1.8 1.4 4.5 3.0 36 2.3 1.7 2.0 42 s s mV/dB V V DS2724-F-03 FINAL DATASHEET DECEMBER 2005 5 ML2724 SYMBOL VRSMN VRSMXC PARAMETER RSSI minimum voltage RSSI maximum voltage (clipped) CONDITIONS No signal into RXI -10dBm into RXI 1.6 MIN TYP 75 1.95 MAX UNITS mV V TRANSMIT RF MIXER POSE PODIF ZOUT Output power, single ended Output power, differential Output impedance TRXO or TRXOB, fC=2.445GHz P(TRXO,TRXOB), fC=2.445GHz TRXO or TRXOB, fC=2.445GHz -3 -1 1 3 12+j0 5 6 dBm dBm TRANSMIT MODULATION fDEV fOS Modulation Deviation, @2.4GHz Modulation center frequency offset 200us of consecutive `1's or `0's 50us after RXON low 500 -50 512 524 +50 kHz kHz TRANSMIT DATA FILTER BWTX Transmit Data Filter Bandwidth TX spurious Image INTERFACE LOGIC LEVELS INPUTS (DIN, XCEN, RXON, DATA, CLK, EN) VIH VIL IB CIN Input high voltage Input low voltage Input bias current Input capacitance (measured at 1MHz) (never exceed VDD) 0.75*VDD 0 -5 0 4 VDD 0.25*VDD 5 V V A pF 3dB Bandwidth 1.4 -25 -20 MHz dBc dBc OUTPUTS (DOUT, PAON) VOH VOL Io VOH VOL Io DOUT high voltage DOUT low voltage DOUT sink/source current PAON output high voltage PAON output low voltage PAON source/sink current Sourcing 0.5mA Sinking 0.5mA 0.5 Io=0.1mA Io=-0.1mA 0.1 VDD-0.4 0.4 VDD-0.4 0.4 V V mA V V mA 3 WIRE SERIAL BUS TIMING tr tf tck tew tl tse ts th CLK input rise time CLK input fall time CLK period CLK pulse width Delay from last CLK falling edge EN setup time to ignore next rising CLK DATA-to-CLK setup time DATA-to-CLK hold time 50 100 15 15 15 15 See Figure 4 15 15 ns ns ns ns ns ns ns ns DS2724-F-03 FINAL DATASHEET DECEMBER 2005 6 ML2724 PIN DESCRIPTIONS PIN SIGNAL NAME I/O FUNCTION DIAGRAM POWER & GROUND 8 10 VSS RVPLL GND PWR Digital Ground. Ground for digital I/O circuits and control logic. PLL Supply. DC power supply decoupling point for the PLL dividers, phase detector, and charge pump. This pin is connected to the output of the regulator and to the PLL supplies. There must be a 220nF capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator. Ground for the PLL dividers, phase detector, and charge pump. DC Power Supply Input to the VCO voltage regulator. Must be connected to RVQMIF (pin 27) or RVDMD (pin 29) via decoupling network. DC power supply decoupling point for the VCO. Connected to the output of the VCO regulator. A 220nF capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. DC ground for VCO and LO circuits. Ground return for the Receive RF input and Transmit RF output. N/A See Pin 11 below. 12 13 GNDPLL VVREG GND PWR N/A N/A 14 RVVCO PWR N/A 16 18 GND GNDRF GND GND N/A VCCA 24 0.7V RXI 17 4k VSS (PIN 8) VCCA (PIN 24) GNDRF 18 8 VSS 19 20 23 GNDRXMX GNDRXMX2 RVLO GND GND PWR Signal ground for the Receive mixers. Signal ground for the Receive mixers. DC power supply decoupling point for the LO Chain. Connected to the output of a regulator. A 220nF capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. N/A N/A N/A DS2724-F-03 FINAL DATASHEET DECEMBER 2005 7 ML2724 PIN 24 SIGNAL NAME VCCA I/O PWR FUNCTION DC power supply Input to Voltage Regulators and unregulated loads: 2.7 to 3.8V. VCCA is the main (or master) analog VCC pin. There must be capacitors to ground from this pin to decouple (bypass) supply noise. DC ground to IF, Demodulator, and Data Slicer circuits. DC power supply decoupling point for Quadrature Mixer and IF filter circuits. A 220nF capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. DC power supply decoupling point for IF, Demodulator, and Data Slicer circuits. A 220nF capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. DC power supply input to the interface logic and control registers. This supply is not connected internally to any other supply pin, but its voltage must be less than or equal to the VCCA supply and greater than 2.7V. A capacitor must be tied between this pin and ground to decouple (bypass) noise. N/A DIAGRAM 25 27 GNDDMD RVQMIF GND PWR N/A N/A 29 RVDMD PWR N/A 31 VDD PWR N/A TRANSMIT/RECEIVE 17 RXI I (Analog) Receive RF Input. Nominal impedance at 2445MHz is 2.6-j2.6 with a simple matching network required for optimum noise figure. This input connects to the base of an NPN transistor and should be AC coupled. VCCA 24 0.7V RXI 17 4k VSS (PIN 8) VCCA (PIN 24) GNDRF 18 8 VSS DS2724-F-03 FINAL DATASHEET DECEMBER 2005 8 ML2724 21 22 TXO TXOB O (Analog) O (Analog) TX RF open-collector output. This output requires a DC path to VCCA. Complementary TX RF open-collector output. This output requires a DC path to VCCA. For single-ended output applications, this pin should be connected to a dummy load that includes a DC path to VCCA. TXO 21 TXOB 22 18 GNDRF DATA 7 AOUT A (Analog) Multi-function Output. In Analog output mode this is output drives an off chip data slicer. In Transmit power control mode this is an open drain output, which is pulled low when the TPC bit is serial register #1, is clear. Transitions on TPC are synchronized to the falling edge of RXON. In analog test modes this pin and the RSSI output become test access points controlled by the serial control bus. TPQ MUX VDD 31 TPC TPC MUX 7 AOUT 100 8 VSS 8 VSS AOUT MUX 30 DIN I (CMOS) Transmit Data Input. Drives the transmit pulse shaping circuits. Serial digital data on this pin becomes FSK modulation on the Transmit RF output. The logic timing on this pin controls data timing. Internal circuits determine the modulation deviation. This is a standard CMOS input referenced to VDD and VSS. Serial digital output after demodulation, chip rate filtering and center data slicing. A CMOS level output (VSS to VDD) with controlled slew rates. A low drive output designed to drive a PCB trace and a CMOS logic input while generating minimal RFI. In digital test modes this pin becomes a test access port controlled by the serial control bus. See Pin 1 below. 32 DOUT O (CMOS) VDD 31 250 32 DOUT 8 VSS DS2724-F-03 FINAL DATASHEET DECEMBER 2005 9 ML2724 MODE CONTROL AND INTERFACE LINES 1 XCEN I (CMOS) Enables the bandgap reference and voltage regulators when high. Consumes only leakage current in STANDBY mode when low. This is a CMOS input, and the thresholds are referenced to VDD and VSS. XCEN 1 VDD 31 2 RXON I (CMOS) TX/RX Control Input. Switches the transceiver between TRANSMIT and RECEIVE modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VDD and VSS. RXON 2 DIN 30 8 VSS 3 PAON O (CMOS) PA Control Output. Enables the off-chip PA at the correct times in a Transmit slot. Goes high when transmit RF is present at TXO; goes low 5s before transmit RF is removed from TXO. Has interlock logic to shut down the PA if the PLL does not lock. VDD 31 3 PAON 8 VSS 9 FREF I Input for the 12.288MHz or 6.144MHz reference frequency. This input is used as the reference frequency for the PLL and as a calibration frequency for the onchip filters. An AC-coupled sine or square wave source drives this selfbiased input. VCCA 24 9 FREF 40k 40k 8 VSS 11 QPO O Charge Pump Output of the phase detector. This is connected to the external PLL loop filter. RVPLL 10 11 QPO 8 VSS DS2724-F-03 FINAL DATASHEET DECEMBER 2005 10 ML2724 15 VTUNE I VCO Tuning Voltage input from the PLL loop filter. This pin is very sensitive to noise coupling and leakage currents. VCCA 24 1.25V VTUNE 15 3.7k 8 VSS 26 28 VBG RSSI O O Bandgap Decouple Voltage. Decoupled to ground with a 220nF capacitor. Buffered Analog RSSI output with a nominal sensitivity of 35mV/dB. In analog test modes, this pin and the AOUT output become test access points controlled by the serial control bus. N/A TPI MUX VCCA 24 RSSI RSSI MUX 28 RSSI OP AMP 100 8 VSS SERIAL BUS SIGNALS 4 EN I (CMOS) Control Bus Enable. Enable pin for the three-wire serial control bus that sets the operating frequency and programmable options. The control registers are loaded on a low-to-high transition of the signal. Serial control bus data is ignored when this signal is high. This is a CMOS input, and the thresholds are referenced to VDD and VSS. Serial Control Bus Data. 16-bit words, which include programming data and the two-bit address of a control, register. This is a CMOS input, and the thresholds are referenced to VDD and VSS. Serial control bus data is clocked in on the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS. VDD 31 EN 4 5.5k DATA 5 CLK 6 8 VSS 1.7p 5 DATA I (CMOS) 6 CLK I (CMOS) DS2724-F-03 FINAL DATASHEET DECEMBER 2005 11 ML2724 FUNCTIONAL DESCRIPTION The ML2724 is a fully integrated 1.5Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed 2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all the frequency generation, receive and transmit functions for a raw data rate of 1.5Mbps. This high data rate allows for data spreading, such as Direct Sequence Spread Spectrum (DSSS) modulation, which improves range. The ML2724 receiver architecture is a dual conversion Low IF, which has all of the sensitivity and selectivity advantages of a traditional super-heterodyne receiver without requiring costly, bulky external filters. The RF mixer down-converts the 2.4GHz RF input signal to the first intermediate frequency (IF), where it is filtered to remove adjacent channel signals. An active image reject mixer converts this signal down to a Low IF frequency, where the data is limited, filtered, and demodulated. This architecture provides all the benefits of direct conversion to baseband while maintaining the stability and robustness of a traditional super-heterodyne. A single synthesizer is used for both the receiver and the FSK transmitter. The phase locked loop (PLL) is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. In RECEIVE MODE, the ML2724 is a dual conversion Low IF receiver. No external SAW filters are required. The integrated image reject mixer gives sufficient rejection in this channel. All channel filtering and demodulation is performed using active filters, which are automatically aligned. A matched bit rate filter and a data slicer follow the demodulator. The sliced data is provided at the DOUT pin, and the analog data is available at AOUT. In TRANSMIT MODE, the ML2724 generates a 2.4GHz output using the transmit mixer. An auto-aligned transmit data filter and modulation compensation circuit results in an adjustment-free transmitter. The VCO is modulated by the transmit data, which is put through a sigma-delta fractional-N PLL ensuring modulation accuracy. This modulation occurs while the phase locked loop is closed, thus allowing practically infinite transmit or receive times with excellent frequency accuracy and stability. A 3dBm FSK-modulated differential signal is output at the TXO/TXOB pins at the 2.4GHz carrier frequency. The integrated PLL frequency synthesizer includes a fully integrated VCO, prescaler, phase detector and charge pump. The reference frequency is generated from the incoming signal at the FREF pin, which can be either 6.144MHz or 12.288MHz. The loop filter is external to allow customers to optimize their loop bandwidth to their system's lock time and in-band phase noise requirements. This frequency-agile synthesizer allows the ML2724 to be used in frequency hopped spread spectrum (FHSS) applications with nominal channel spacing of 2.048MHz. Carrier frequency is programmed via the configuration registers and 3-wire serial interface. The VCO tank circuit (inductor and varactor) is fully integrated. AOUT RXI 2.4 GHz Receive Input Quadrature Downmixers F to V DOUT Receive Data Out RSSI Test Mux Filter Alignment RSSI Divide by 2 Quadrature Divider Transmit Mixer TXO/TXOB 2.4 GHz Output Two-port Modulator Mode Control TPC PAON RXON XCEN Parallel control lines 2 DIN Transmit Data In Control Registers DATA Serial CLK Control Bus EN FREF Frequency Reference 1.6 GHz VCO Bandgap PLL Divider P.D. Ref. Divider VTUNE QPO PLL Loop Filter Figure 2: ML2724 Internal Block Diagram DS2724-F-03 FINAL DATASHEET DECEMBER 2005 12 ML2724 RVVCO 150 33nF 220nF QPO VTUNE Example 13kHz Loop Filter MODES OF OPERATION There are three key modes of operation: STANDBY: RECEIVE: TRANSMIT: All circuits powered down, except the control interface (Static CMOS) Receiver circuits active Modulated RF output from IC The two operational modes are RECEIVE and TRANSMIT, controlled by RXON. XCEN is the chip enable/disable control pin, which sets the part in operational or STANDBY modes. The relationship between the parallel control lines and the mode of operation of the IC is given in Table 1. XCEN 0 1 1 RXON X 1 0 MODE STANDBY RECEIVE TRANSMIT FUNCTION Control interfaces active, all other circuits powered down Receiver time slot Transmit time slot Table 1: Modes of Operation MODE CONTROL The ML2724 is intended for use in TDD and TDMA radios in battery-powered equipment. To minimize power consumption it is designed to switch rapidly from a low power mode (STANDBY) to an active mode. The ML2724 can also make a quick transition from receive to transmit for TDD operation. Prior to transmitting or receiving, time should be allowed for the PLL to lock and for the filters to align. When the ML2724 is operated in single-carrier TDD mode, the LO is automatically shifted by the second (low) IF frequency when the device is switched between RECEIVE and TRANSMIT modes. ML2724 carrier frequency can be changed (hopped) at any time, but is usually changed between transmissions. Carrier frequency (channel) is modified in the ML2724 by writing a corresponding new value to the PLL frequency register (Register 1) RECEIVE The ML2724 uses a double-conversion super-heterodyne receiver with a nominal second IF of 1.024MHz. The signal flow in RECEIVE mode is from the RF input, through an RF down-conversion mixer and integrated IF filter, image reject quadrature mixer, integrated Low IF filter, hard limiter, frequency to voltage converter, and data filter to the AOUT pin and data slicer where the digital NRZ data is available at the DOUT pin. A 20dB step AGC extends the dynamic range of the receiver. The ML2724 receive chain is a Low IF receiver using advanced integrated radio techniques to eliminate external IF filters and minimize external RF filter requirements. The precision filtering and demodulation circuits give improved performance over conventional radio designs using external filters while providing integration comparable to advanced direct conversion radio designs. DS2724-F-03 FINAL DATASHEET DECEMBER 2005 13 ML2724 Receive Signal Strength Indication (RSSI) RSSI is an indication of field strength. It can be used to control transmit power to conserve battery life or it may be used to determine if a given channel is occupied. See Figure 3. Figure 3: RSSI Voltage vs. Input Signal Level Automatic Filter Alignment When the ML2724 is placed in RECEIVE mode, it automatically tunes all the internal filters using the reference frequency from the FREF pin. When the chip is powered up (VDD first applied), the tuning information is reset to midrange. This self-calibration sets: Discriminator center frequency IF filter center frequency and bandwidth Receiver data low-pass filter bandwidth Transmit data low-pass filter bandwidth TRANSMIT MODE In TRANSMIT mode, the PLL is closed to eliminate frequency drift. A two-port modulator modulates both the VCO and the fractional-N PLL. The VCO is directly modulated with filtered FSK transmit data. The PLL is driven by a sigma-delta modulator, which ensures that the PLL follows the mean frequency of the modulated VCO. The transmit modulation filter is automatically tuned during every RECEIVE time, alleviating the need for production alignment. Asserting RXON enables the ML2724. The rising edge of XCEN triggers a complete calibration of all the onchip filters, which takes up to 256s, which ensures the modulation filters are aligned to prevent unwanted spurious emissions. PLL PROGRAMMING & CHANNEL SELECTION The ML2724 PLL is programmed via control register 2 to the set RF center frequency of operation of the radio. The PLL does not need to be (though it can be) reprogrammed between RECEIVE and TRANSMIT modes. Nominal channel separation is 2.048MHz, allowing for over 40 non-overlapping channels in any given location. With careful planning, channels can be programmed in 1024kHz steps as long as care is exercised to insure that two radio links will not share spectrum at any one time. The equation to determine channel center frequency from the ML2724 control register word is: fC = CHQ<0:11>*1.024MHz DS2724-F-03 FINAL DATASHEET DECEMBER 2005 14 ML2724 STANDBY MODE In STANDBY mode, the ML2724 transceiver is powered down. The only circuits active are the control interfaces, which are digital CMOS to minimize power consumption. The serial control interface and control registers remain powered up and will accept and retain programming data as long as the digital supply is present. When exiting STANDBY mode, the device may need to be kept in RECEIVE mode for up to 256s to allow for filter self-calibration. TEST MODE The RF to digital functionality of the ML2724 requires special test mode circuitry for IC production test and radio debugging. A test register, accessible via the 3-wire serial interface, controls the test multiplexers. (See Table 15). DATA INTERFACE There are two control interfaces: CONTROL and SERIAL. CONTROL INTERFACE The control interface provides immediate control and monitoring of the ML2724. Input signals include: XCEN: RXON: FREF: Transceiver enable. Places the ML2724 in Standby or Active (when asserted) modes. Receive On. Places an Active ML2724 in Receive mode when asserted. Reference frequency input Received Signal Strength Indicator: indicates the power of the received signal External Power Amplifier Control Pin Output signals include: RSSI: PAON: SERIAL INTERFACE A 3-wire serial interface (EN, DATA, CLK) is used for programming the ML2724 configuration registers, which control device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are entered beginning with the MSB ("big-endian"). The word is divided into a leading 14-bit data field followed by a 2-bit address field. When the address field has been decoded the destination register is loaded on the rising edge of EN. Providing less than 16 bits of data will result in unpredictable behavior when EN goes high. Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift register on the rising edge of the CLK pin. This information is loaded into the target control register when EN goes high. This serial interface bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either byte or 16-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal power when the bus is inactive. Refer to Figure 4 and Table 2: 3-Wire Bus Timing Characteristics for timing and register programming illustrations. SYMBOL PARAMETER MIN TYP MAX UNIT BUS CLOCK (CLK) tr tf tck CLK input rise time CLK input fall time CLK period 50 15 15 ns ns ns ENABLE (EN) tew tl tse Minimum pulse width Delay from last CLK rising edge Set up time to ignore next rising CLK 100 15 15 ns ns ns DS2724-F-03 FINAL DATASHEET DECEMBER 2005 15 ML2724 BUS DATA (DATA) ts th data to clock set up time data to clock hold time 15 15 Ns Ns Table 2: 3-Wire Bus Timing Characteristics tF tS tH tR t CK tL CLK DATA MSB LSB tEW DATA ADDRESS EN Figure 4: Serial Bus Timing for Address and Data Programming DS2724-F-03 FINAL DATASHEET DECEMBER 2005 16 ML2724 CONTROL INTERFACES AND REGISTER DESCRIPTIONS REGISTER INFORMATION A 3-wire serial data input bus sets the ML2724's transceiver parameters and programs the PLL circuits. Entering 16-bit words into the ML2724 serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. The contents of these registers cannot be read back via this bus. The three registers are: Register 0: Register 1: Register 2: PLL Configuration Channel Frequency Data Internal Test Access Figure 5 shows a register map. Table 3 through Table 5 provide detailed diagrams of the register organization: Table 3 and Table 4 outline the PLL configuration and channel frequency registers, and Table 5 displays the filter tuning and test mode register. MSB DB13 Res. B15 DB12 Res. B14 DB11 Res. B13 DB10 Res. B12 DB9 RCLP B11 DB8 LVLO B10 DB7 Res. B9 DB6 TXM B8 DB5 TPC B7 DB4 TXCW B6 DB3 Res. B5 DB2 AOUT B4 DB1 RD0 B3 DB0 QPP B2 ADR1 0 B1 ADR0 0 B0 MSB DB13 Res. DB12 Res. B14 DB9 DB11 DB10 CHQ11 CHQ10 CHQ9 B13 B12 DB8 DB7 DB6 DB5 CHQ8 CHQ7 CHQ6 CHQ5 B10 B9 B8 DB4 CHQ4 DB3 CHQ3 DB2 DB1 DB0 CHQ2 CHQ1 CHQ0 B4 B3 ADR1 0 ADR0 1 B1 B0 B15 B11 B7 B6 B5 B2 MSB DB13 Res. B15 DB12 Res. B14 DB11 Res. B13 DB10 Res. B12 DB9 Res. B11 DB8 Res. B10 DB7 Res. B9 DB6 Res. B8 DB5 DTM2 B7 DB4 DTM1 B6 DB3 DTM0 B5 DB2 ATM2 B4 DB1 ATM1 B3 DB0 ATM0 B2 ADR1 1 B1 ADR0 0 B0 Figure 5: Configuration Register Map DS2724-F-03 FINAL DATASHEET DECEMBER 2005 17 ML2724 NAME Reserved Reserved Reserved Reserved RCLP LVLO Reserved TXM TPC TXCW Reserved AOUT RD0 QPP ADR1 ADR0 DESCRIPTION Reserved Reserved Reserved Reserved RSSI Clip Disable Low Voltage Lockout Reserved TX RF Output Mode Transmit Power Control Transmit Test Mode Reserved Analog Output Reference Frequency Select PLL Charge Pump Polarity MSB Address Bit LSB Address Bit DEFINITION Set all bits to 0 (zero) 0: RSSI clipped to 1.9V at -15dBm 1: RSSI not clipped 0: PAON Undisturbed 1: PAON De-asserted for VCCA<2.65V. Reset on RXON high Set to 0 0: TX RF Output always on in TX mode 1: TX RF Output follows PAON signal 0: AOUT pin pulled to ground 1: AOUT pin high impedance 0: FSK modulation in Transmit mode 1: CW (no modulation in Transmit mode) Set to 0 0: AOUT pin is Transmit Power Control 1: AOUT pin is Analog Data Out 0: 6.144MHz nominal reference frequency 1: 12.288MHz nominal reference frequency (preferred) 0: For fc < fref, charge pump sources current 1: For fc < fref, charge pump sinks current ADR1=0 ADR0=0 Table 3: Register 0 -- PLL Configuration Register NAME Reserved Reserved CHQ11 CHQ10 CHQ9 CHQ8 CHQ7 CHQ6 CHQ5 CHQ4 CHQ3 CHQ2 CHQ1 CHQ0 ADR1 ADR0 MSB Address Bit LSB Address Bit ADR1=0 ADR0=1 Channel Frequency select bits Divide ratio=fc/1.024 DESCRIPTION DEFINITION Set all bits to 0 (zero) Table 4: Register 1 - Channel Frequency Register DS2724-F-03 FINAL DATASHEET DECEMBER 2005 18 ML2724 NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DTM2 DTM1 DTM0 ATM2 ATM 1 ATM 0 ADR1 ADR0 MSB Address Bit LSB Address Bit ADR1=0 ADR0=1 Analog Test Control Bits See Table 15 Digital Test Control Bits See Table 16 Reserved Set all bits to 0 (zero) DESCRIPTION DEFINITION Table 5: Register 2 - Test Mode Register Power-On State On Power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when VDD>2.0V. The register default values are valid upon power up. CONTROL REGISTER BIT DESCRIPTIONS ADR<1:0>, All Registers, Bits 0-1 Address Bits: The ADR<1:0> bits are the least-significant bits of each register. Each register is divided into a data field and an address field. The data field is the leading field, while the last two bits clocked into the register are always the address field. When EN goes high, the address field is decoded and the addressed destination register is loaded. The last 16 bits clocked into the serial bus are loaded into the register. Clocking in less than 16 bits results in a potentially incorrect entry into the register. RES (Reserved), All Registers Reserved Bits: These bits are reserved. These bits must be cleared to 0s (zeros) for normal operation. When power is reset, all of the registers' data fields are cleared to 0s (zeros). QPP - Register 0, Bit 2 Charge Pump Polarity: This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is cleared (QPP=0). For applications where an external inverting amplifier is used in the loop filter, this bit is set to change the charge pump polarity (see Table 6). QPP 0 1 PLL CHARGE PUMP POLARITY fc > fref Charge pump sinks current. fc > fref Charge pump sources current. Table 6: PLL Charge Pump Polarity DS2724-F-03 FINAL DATASHEET DECEMBER 2005 19 ML2724 RD0 - Register 0, Bit 3 Reference Divide: This bit sets the reference divider from the FREF pin to the reference input of the PLL phase/frequency detector to either 9 or 18 (see Table 7). RD0 REFERENCE DIVISION 0 1 9 18 FREF XTAL FREQ 6.144MHz 12.288MHz PLL REF FREQ 682.67kHz 682.67kHz Table 7: Reference Frequency Select AOUT - Register 0, Bit 4 Analog Output Mode: This bit changes the function of the AOUT pin between an analog data output to transmit power control (see Table 8). AOUT 0 1 AOUT PIN FUNCTION Transmit Power Control Data Filter Analog Output Table 8: AOUT Function Select TXCW - Register 0, Bit 6 Transmit Continuous Wave: This bit produces a continuous wave (CW) transmitter output for product test when RXON is low (see Table 9). TXCW 0 1 TRANSMIT MODULATION FSK Modulation CW - No Modulation Table 9: Transmit Modulation Mode TPC - Register 0, Bit 7 Transmit Power Control: When the AOUT bit is low, this bit controls the state of the open-drain output pin. Although this bit can be changed at any time, the AOUT pin only changes state at the falling edge of RXON (see Table 10). TPC 0 1 TPC PIN STATE High Impedance Pulled to Ground Table 10: TPC Pin State TXM - Register 0, Bit 8 Transmit Mode: This bit controls the TX RF buffer state timing mode. It must be reset to 0 for normal operation (see Table 11). TXM 0 1 TXRF BUFFER BEHAVIOR RF Output Always On in TX Mode RF Output Follows PAON Table 11: TXM Mode DS2724-F-03 FINAL DATASHEET DECEMBER 2005 20 ML2724 LVLO - Register 0, Bit 10 Low Voltage Lock Out: The LVLO bit enables a transmit low voltage lockout latch, which shuts off the transmitter by de-asserting the PAON output. This latch is set if the supply voltage drops below 2.65V and is reset when the RXON control input goes high (see Table 12). LVLO 0 1 PAON BEHAVIOR PAON Undisturbed PAON de-asserted when VCCA<2.65V, Reset by RXON high. Table 12: LVLO Operation RCLP - Register 0, Bit 11 RSSI Clip Enable: The RCLP bit disables the RSSI clipping circuitry. With RCLP low, the RSSI output voltage is clipped to a maximum of about 2.0V at -10dBm. With RCLP high, the RSSI is not clipped. (see Table 13). RCLP 0 1 RSSI BEHAVIOR RSSI output clipped to a maximum of ~1.9V at -15dBm RSSI output not clipped Table 13: RCLP Operation CHQ <11:0> - Register 1, Bits 2-13 Channel Frequency Selection: These bits set the RF carrier frequency for the transceiver (see Table 14). With a 6.144MHz or 12.288MHz clock at the FREF pin, the channel frequency value is calculated by multiplying the CHQ value by 1.024. The recommended operating range value of the CHQ is from 2,346 to 2,424. These bits must be programmed to a valid channel frequency before XCEN is asserted. B15 0 B14 0 B13 TO B2 CHQ - PLL Divide Ratio Table 14: Main Divider B1 0 B0 1 The divide ratio is calculated as fC /1.024 where fC is the channel frequency in MHz. fC=1.024 * CHQ DS2724-F-03 FINAL DATASHEET DECEMBER 2005 21 ML2724 ATM<2:0> - Register 2, Bits 2-4 Analog Test Mode: The test mode selected is described in Table 15. The performance of the ML2724 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is ATM<2:0>=<0,0,0>. When a non-zero value is written to the field, the RSSI and AOUT pins become analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. During normal operation, ATM<2:0> must be set to all zeros. ATM2 0 0 0 0 1 1 1 1 ATM1 0 0 1 1 0 0 1 1 ATM0 0 1 0 1 0 1 0 1 RSSI RSSI No Connect I IF Filter Output Q IF Filter - ve Output I IF Filter - ve Output Data Filter + ve Output I IF Limiter Outputs 1.67V Voltage Reference AOUT Set by AOUT bit No Connect Q IF Filter Output Q IF Filter + ve Output I IF Filter + ve Output Data Filter - ve Output Q IF Limiter Outputs VCO Modulation Port Input Table 15: Analog Test Control Bits DTM <2:0> - Register 2, Bits 5-7 Digital Test Mode: The DTM<2:0> bit functions are described in Table 16. The performance of the ML2724 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power up) state of these bits is DTM<2:0>=<0,0,0>. When a non-zero value is written to these fields, the DOUT and PAON pins become a digital test access port for key digital signals in the transceiver. During normal operation, DTM<2:0> must be set to all zeros. DTM2 0 0 0 0 1 DTM1 0 0 1 1 0 DTM0 0 1 0 1 0 PAON PA Control PA Control PA Control PA Control S - D Modulation LSB DOUT Data Out AGC Switch State PLL Main Divider Output PLL Reference Divider Output Sigma - Delta Modulation MSB Table 16: Digital Test Control Bits DATA INTERFACES BASEBAND INTERFACE: DIN & DOUT The DIN and DOUT pins are digital CMOS signals that correspond to FSK modulation of the carrier frequency. The ML2724 is designed to operate as an FSK transceiver in the 2.4GHz ISM band. The frequency deviation and transmit filtering is determined in the transceiver. Data on the DIN pin is filtered and presented to the transmit two-port modulator. There is no re-timing of the bits, so the transmitted FSK data takes its timing from the input data. In the receive chain, FSK demodulation, data filtering, and data slicing take place in the ML2724, and the digital data is output on the DOUT pin. Bit and word rate timing recovery are performed off chip. The data filter output is available on the AOUT pin for use with an optional external data slicer. DS2724-F-03 FINAL DATASHEET DECEMBER 2005 22 ML2724 RSSI & FREF FREF (pin 9) is the master reference frequency for the transceiver. It supplies the frequency reference for the RF channel frequency and the filter tuning. The FREF pin is a CMOS input with internal biasing resistors. It can be AC coupled to sine or square wave source. The FREF input can also be driven by a CMOS logic output. The frequency of the FREF input is limited to one of: 6.144MHz or 12.288MHz. The Received Signal Strength Indicator (RSSI) pin supplies a voltage proportional to the logarithm of the received power level. It is normally connected to the input of a low speed ADC and is used during channel scanning to detect clear channels on which the radio may transmit. It can also be used to set transmit power to optimize power consumption while maintaining an acceptable bit error rate (BER). PA CONTROL OUTPUTS (PAON & AOUT) The PAON (PA control) is a CMOS output that controls an optional off-chip RF PA. It outputs a logic high when the PA should be enabled and a logic low at all other times. This output is inhibited when the PLL fails to lock. AOUT (pin 7) normally supplies the analog (not data-sliced) data output, but it can also be configured as an open-drain output for transmit power control. This mode is controlled by the TPC bit in Register 0. This bit can be changed at any time, but the AOUT pin will not change mode until the beginning of the next transmit slot, triggered by a falling edge on Table 17 for details). RXON (see Figure 6 and In analog test modes the RSSI and AOUT pins become analog test access ports that allow the user to observe internal signals in the ML2724. RXON SYMBOL T1 PAON Output from TRFO t1 t4 t2 t3 PARAMETER RXON falling edge to PAON rising edge RXON rising edge to PLL frequency shift RXON rising edge to RECEIVE mode RXON rising edge to PAON falling edge TIME/S 62.5 6.5 70 < 0.1 T2 T3 T4 Figure 6: Power Amplifier Interface Table 17: Power Amplifier Timing RF INTERFACE: RXI & TXO/TXOB The RXI receive input (pin 17) and the TXO/TXOB differential transmit outputs (pins 21 and 22) are the only RF I/O pins. The RXI pin requires a simple impedance matching network for optimum input noise figure. The TXO/TXOB pins require a matching network for maximum power output into the RF power amp. If a single ended output is preferred, the signal from the TXO pin can be matched to the power amp and the TXOB output can be shunted to a power supply through a dummy load. The RF input and output ground (pin 18) must have a direct connection to the RF ground plane, and the RF power supply pins must be decoupled to the same ground plane as close to the device as possible. DS2724-F-03 FINAL DATASHEET DECEMBER 2005 23 ML2724 PERFORMANCE GRAPHS Figure 7: Output Power (Single Ended) vs. Frequency Figure 8: RX Sensitivity (12.5% BER) vs. Frequency 0 -2 -4 -6 0 2.7V 3.3V 4.5V -5 2.7V 3.3V 4.5V -10 dB -8 -10 dB -15 -20 -12 -14 2401.00 2417.80 2434.60 2451.40 2468.20 2485.00 -25 2401.00 2417.80 2434.60 2451.40 2468.20 2485.00 MHz MHz Figure 9: Input Return Loss vs. Frequency and Voltage Figure 10: Output Match (SE) vs. Frequency and Voltage 1000 800 600 400 Deviation (kHz) 200 0 -200 -400 -600 -800 -1000 0 1.800 1.600 1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.2 0.4 0.6 0.8 1 1.2 Time-Symbols 1.4 1.6 1.8 2 0.000 1570 1577 1584 1591 1597 1604 1611 1618 1625 1632 1638 1645 1652 1659 1666 1673 1679 1686 1693 1700 Figure 11: TX Eye Diagram Figure 12: VCO Tuning Voltage vs. Frequency DS2724-F-03 FINAL DATASHEET DECEMBER 2005 24 ML2724 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) 0.354 BSC (9.00 BSC) 0.276 BSC (7.00 BSC) 0 - 8 25 0.003 - 0.008 (0.09 - 0.20) 1 PIN 1 ID 0.276 BSC (7.00 BSC) 0.354 BSC (9.00 BSC) 17 0.018 - 0.030 (0.45 - 0.75) 9 0.032 BSC (0.8 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05) SEATING PLANE Note: This package meets "Green" Pb-Free requirements and is compliant with the European Union directives WEEE (Waste Electrical and Electronic Equipment) and RoHS (Restriction of the use of certain Hazardous Substances in electrical and electronic equipment). The package pins are finished with 100% matte tin. DS2724-F-03 FINAL DATASHEET DECEMBER 2005 25 ML2724 WARRANTY Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. If this document is "Advance", its contents describe a Micro Linear product that is currently under development. All detailed specifications including pinouts and electrical specifications may be changed without notice. If this document is "Preliminary", its contents are based on early silicon measurements. Typical data is representative of the product but is subject to change without notice. Pin out and mechanical dimensions are final. Preliminary documents supersede all Advance documents and all previous Preliminary versions. If this document is "Final", its contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all previously published versions. (c) 2005 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear Corporation 2050 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS2724-F-03 FINAL DATASHEET DECEMBER 2005 26 |
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