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R8A66174SP
PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO
REJ03F0278-0101 Rev. 1.01 Oct.06.2008
DESCRIPTION
The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands or up to 63bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request signal. R8A66174 has 2-bit output pins (/OE, LATCH) which can set/reset outside devices by the command, R8A66174 can be connected to peripheral circuits that have a serial latch structure. R8A66174 is the succession product of M66300.
FEATURES
General-purpose 8-bit CPU bus compatible Built-in 63-byte FIFO High-speed output (10Mbps) It's able to connect to LED array driver such as R8A66160 or R8A66161 directly Low-noise, high-output circuit IOL=16mA, IOH=-16mA (IOL=4mA, IOH=-4mA for /INT) Schmitt input (/RESET) Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V) o Wide operating temperature range (Ta=-40~85 C)
APPLICATION
General digital equipment for industrial and home use, panel display controllers, and eraser unit controller for copying machine.
PIN CONFIGURATION (TOP VIEW)
WRITE INPUT
WR D0 D1 D2 D3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc C/D CS RESET INT OE LATCH SDATA SCLK COMMAND/DATA INPUT CHIP SELECT INPUT RESET INPUT INTERRUPT REQUEST OUTPUT OUTPUT ENABLE OUTPUT LATCH OUTPUT SHIFT DATA OUTPUT SHIFT CLOCK OUTPUT CLOCK INPUT
DATA BUS D4 D5 D6 D7 GND
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 1 of 11
R8A66174SP BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8 9 WR CK 8 SELECTOR 13
SDATA
DATA BUS
63 X 8-BIT SRAM
SHIFT DATA OUTPUT
LOAD
8-BIT SHIFT REGISTER
DECODER
SELECTOR
S
COMMAND/ DATA INPUT CHIP SELECT INPUT WRITE INPUT
C/D 19 CS 18 WR 1
CK
INPUT CONTROL CIRCUIT
MATCHING DETECTION CIRCUIT WRITE COUNTER READ COUNTER
RD RD CK
CK
COMMAND REGISTER
BIT/BYTE CONVERTER F/F GATE
12
CLOCK INPUT INTERRUPT REQUEST OUTPUT RESET INPUT
11 INT 16
DIVIDER
SCLK
SHIFT CLOCK OUTPUT
14
RESET
17
15
OE
LATCH LATCH OUTPUT OUTPUT ENABLE OUTPUT
FUNCTIONAL DESCRIPTION
The information on data bus D0~D7 is loaded as command when C//D=1, and as data when C//D=0. There are four kinds of commands. (1) Command 1. Five kinds of division ratios of the clock input are set up. (2) Command 2. R8A66174 is set as write mode. The CPU is capable of writing 8-bit parallel data of up to 63 bytes into the internal memory (FIFO) of the R8A66174. (3) Command 3. R8A66174 is set as serial output mode. All data written in the internal memory (FIFO) is outputted as serial data in sync with the shift clock which is set by command 1. Then, each data is outputted from LSB. When all stored data has outputted, R8A66174 will output the interrupt request /INT to CPU. (4) Command 4. cancels the /INT and sets/resets the two control ports (LATCH, /OE). After command4, if command3 is executed immediately, the data which is already written will be re-outputted.
FUNCTION TABLE
Command
Input Control inputs /R 0 1 1 /CS C//D /WR D7 x 1 0 x x 1 x x x x 1 1 1 1 1 1 0 1 *5 *5 0 x x 1 x x 0 x 0 x x 0 D6 x x 0 0 0 0 1 x x x x x x D5 x x 0 0 1 1 0 x x x x x x Data inputs D4 x x 0 1 0 1 0 x x x x x x 0 x 0 x x 1 x x x x x D2 x x x x x D1 0 x 1 x x x D3 x x x D2 x x x D1 x x x D0 x x x 0 *1 0 0 0 0 0 0 0 *3 *3 0 0 0 *1 0 0 0 0 0 0 0 *4 *4 0 0
Outputs
SCLK SDATA /INT /OE LATCH
Remark Initialize 1/2 division of 1/4 division of 1/8 division of 1/16 division of WRITE MODE setting WRITE operation
SERIAL OUT MODE setting

1 *1 1 1 1 1 1 1 1 1 1 0 1
1 *2
0
* 2 Memory contents not changed Valid when D7 is high-level
1
2
WRITE MODE
3
SERIAL OUT SERIAL OUT end D2
SERI. OUT MODE
4
D1 set/reset the /OE and LATCH, cancel /INT
Note1 *1 : The same operation as *3 and *4 in the SERIAL OUT mode. The output is not changed in other modes. *2 : The output is not changed. *3 : The division pulse which is set by command 1 is outputted on /WR rise. *4 : SDATA (n) is output on SCLK fall (n-1). *5 : Indicates 1 when /WR is 0, don't care when /WR is 1. X : Don't care
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 2 of 11
R8A66174SP BASIC OPERATION
Fig. 1 shows the basic operation flowchart. Data inputs D0~D7 are switched among four commands and 8-bit parallel data by the C//D signal. When C//D is 1, the command is stored in sync with the rise of /WR. For initiate to work this IC, at first command 1 should be stored. Command 1 sets the division ratio for clock input as 5 divisions of 1, 1/2, 1/4, 1/8 and 1/16. (The default ratio is 1.) Then command 2 should be stored. When it is stored, 8-bit parallel data is written into the internal memory (FIFO) on the write cycle of the CPU. The maximum capacity of its FIFO is 63 bytes. When the write operation has done, command 3 should be stored. For this action, all data in the internal memory is outputted as serial data (SDATA) in sync with the shift clock (SCLK output) which is set by command 1. Then, each data is outputted from LSB. The SDATA changes on the fall of SCLK. When it finishes to output data, an interrupt request /INT is outputted to the CPU. /INT is canceled by command 4 or command 2 and command 3. The command 4 sets/resets two control ports (LATCH, /OE) as well as canceling /INT. If command 3 is executed without executing command 2 after command 4, the already written-in data can be re-outputted. If it is not required to re-output the previous data, please execute command 2 before command 3 will be executed.
Reset
C/D=1
Command 1 store
Division ratio setting
C/D=1
Command 2 store
C/D=0
Write operation 1 w rite cycle/byte
End? Repeat output YES
NO (MAX : 63 Byte)
C/D=1
Command 3 store
SERIAL OUTPUT
End? YES
NO
Interrupt request out
In spite of having stored write mode by command 2, when serial out mode is stored by command 3, without writing any parallel data to an internal memory (FIFO), an incorrect output appears in SDATA, SCLK, and /INT. Please be careful. (command 2 store data is not written Please avoid such usage. )
command 3 store :
C/D=1
Command 4 store
(Cancel interrupt request) LATCH output
C/D=1
Command 4 store
Interrupt from others C/D=1
OE output
Command 4 store
Cancel LATCH, OE
YES
Repeat data output? NO
Fig. 1 Flowchart (Basic operation)
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 3 of 11
R8A66174SP PIN DESCRIPTION
INSTRUCTION SET
Four commands can be set by the 8-bit command words from the CPU. Table 2 Command setting
Fig. 2 shows the method for determining the command word for the instruction set. When D7 is 1, D3~D0 are masked and when D3 is 1, D0 is masked. Table 3 Division ratio setting 1 Table 4 /OE, LATCH setting
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 4 of 11
R8A66174SP
1
Division ratio setting D6 D5 0 0 1 1 0 D1 0 1 0 1 D4 0 1 0 1 0 1/2 of 1/4 of 1/8 of 1/16 of /OE 0 0 1 1 LATCH 0 1 0 1 Division ratio
When D7 =
1
0 0 0 0 1 Set/Reset LATCH and /OE, and cancel /INT 1 D2 0 When D3 = 1 0 1 1 When D7 = D3 = 0 D0
Mode setting WRITE SERIAL OUT
D7
D6
D5
D4
D3
D2
D1
D0
0 1
Fig. 2 Instruction set
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 5 of 11
R8A66174SP
EXAMPLE OF TIME CHART
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 6 of 11
R8A66174SP ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI Vo Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Ratings -0.5~+7.0 -0.5~Vcc+0.5 -0.5~Vcc+0.5 500 -65~150 Unit V V V mW
RECOMMENDED OPERATING CONDITIONSTa=-40~85oC
Symbol Vcc GND VI Vo Topr Supply voltage Supply voltage Input voltage Output voltage Operating temperature range Parameter 5.0V 3.3V Min 4.5 3.0 0 0 -40 Limits Typ 5.0 3.3 0 Max 5.5 3.6 Vcc Vcc 85 Unit V V V V V
ELECTRICAL CHARACTERISTICS
5.0V version support specifications (Ta=-40~85oC, Vcc=4.5~5.5V)
Symbol VIH VIL VT+ VTVH VOH VOL Icc IIH IIL Parameter High-level input voltage Low-level input voltage Positive input threshold voltage Negative input threshold voltage Hysteresis width High-level output /INT voltage Outputs except /INT Low-level output /INT voltage Outputs except /INT Supply current High-level input current Low-level input current Test conditions Inputs except /RESET /RESET IOH=-4mA IOH=-16mA IOL=4mA IOL=16mA VI=Vcc or GND VI=Vcc VI=0V Min 0.75XVcc 0.35XVcc 0.2XVcc 0.4 Vcc-0.8 Vcc-0.8 Limits Typ Max 0.25XVcc 0.8XVcc 0.65XVcc Unit V V V V V V V V V mA A A
0.53 0.53 50 +1 -1
3.3V version support specifications(Ta=-40~85oC, Vcc=3.0~3.6V)
Symbol VIH VIL VT+ VTVH Parameter Test conditions Inputs except /RESET /RESET IOH=-2mA IOH=-8mA IOL=2mA IOL=8mA VI=Vcc or GND VI=Vcc VI=0V High-level input voltage Low-level input voltage Positive input threshold voltage Negative input threshold voltage Hysteresis width High-level output /INT VOH voltage Outputs except /INT Low-level output /INT VOL voltage Outputs except /INT Supply current Icc High-level input current IIH Low-level input current IIL Note 9 : The current flowing into the IC is positive (no sign). Min 0.75XVcc 0.35XVcc 0.2XVcc 0.4 Vcc-0.4 Vcc-0.6 Limits Typ Max 0.25XVcc 0.8XVcc 0.65XVcc Unit V V V V V V V V V mA A A
0.4 0.5 50 +1 -1
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 7 of 11
R8A66174SP TIMING REQUIREMENTS (Ta=-40~85oC, Vcc=4.5~5.5V or 3.0~3.6V)
Limits for 5.0V Min Typ Max Clock pulse width tw() 50 Write pulse width tw(/W) 100 Reset pulse width tw(/R) 100 Data setup time before write tsu(D-/W) 50 Data hold time after write th(/W-D) 0 Address setup time before write tsu(A-/W) 0 Address hold time after write th(/W-A) 0 Write recovery time trec(/W) 100 trec(/INT-/W) Write recovery time after /INT 100 Write recovery time after reset trec(/R-/W) 100 Note 10 : Increase of the input rise time (tr) and fall time (tf) of clock input may cause misoperation. tr, tf : These are recommended to be 20ns or less. Symbol Parameter Test condition Min 60 120 120 60 0 0 0 120 120 120 Limits for 3.3V Typ Max Unit ns ns ns ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS(Ta=-40~85oC, Vcc=4.5~5.5V or 3.0~3.6V)
Symbol tc() tPLH(/W-/INT) tPLH(/R-/INT) tPLH(/W-/OE) tPHL(/W-/OE) tPLH(/W-LA) tPHL(/W-LA) tPLH(/W-SC) tPLH(-SC) tPLH(-SD) tPHL(-SD) tPHL(-/INT) tPLH(/R-/OE) tPHL(/R-LA) tTLH tTHL Parameter Clock Cycle Propagation time between write and /INT Propagation time between /RESET and /INT Propagation time between write and /OE Propagation time between write and LATCH Propagation time between write and SCLK Propagation time between and SCLK Propagation time between and SDATA 1xT CL=150pF Test condition Min 100 Limits for 5.0V Typ Max 100 100 100 100 100 100 2xT+100 100 100 100 100 100 100 25 25 25 CL=150pF 25 30 ns Min 120 Limits for 3.3V Typ Max 120 120 120 120 120 120 2xT+120 120 120 120 120 120 120 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CL=50pF
1xT
Propagation time between and /INT Propagation time between /RESET and /OE Propagation time between /RESET and LATCH Low to high level output transition time (/INT) High to low level output transition time (/INT) Low to high level output transition time tTLH (SCLK, SDATA, /OE, LATCH) High to low level output transition time tTHL (SCLK, SDATA, /OE, LATCH) Note 11 : T=(1/)x(1/division ratio) [ns] 12 : AC test waveform 0~Vcc Input pulse level Input pulse rise time 6ns Input pulse fall time 6ns Reference voltage Input voltage 0.5XVcc Output voltage 0.5XVcc
CL=50pF
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 8 of 11
R8A66174SP TIMING DIAGRAM
Instruction set 1~4
tc() tw() (Note 13) Note 14 : Output when command 3 is set. Note 15 : Output when command 4 is set.
C/D, CS INPUTS WR tsu(A-/W) tw(/W) th(/W-A) th(/W-D)
tsu(D-/W) D0~D7
tPLH(-SC) SCLK (Note 14) tPLH(/W-SC) tPLH(-SD) tPHL(-SD) SDATA (Note 14) OUTPUTS First byte LSB Last byte MSB
tPLH(/W-/OE), (/W-LA) tPHL(/W-/OE), (/W-LA)
OE, LATCH (Note 15) tPHL(-/INT) trec(/INT-/W) INT (Note 15) tPLH(/W-/INT)
Note 13 : The timing diagram when division ratio is set (1/2, 1/4, 1/8, 1/16) is regarded as the waveform as divided by . There are specific inputs for switching from each state.
Timing diagram when RESET
tw(/R)
RESET INPUTS
WR
trec(/R-/W)
tPLH(/R-/OE) OE
tPHL(/R-LA) OUTPUTS LATCH
INT
tPLH(/R-/INT)
WR recovery time other than data reading
trec(/W) INPUT WR
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 9 of 11
R8A66174SP
Control unit
HC373 : D type latch circuit(8 bit) HC138 : 3 to 8 decoder R8A66160 : LED driver(-24mA, cathode common) (R8A66161 : LED driver(+24mA, anode common) A12~A15 A0 A1 A2
Control unit
A12~A15 A0 A1 A2
HC138 Y Y Y Y XIN A8~A15 XOUT CE A0~A12 ROM D0~D7 A0 OE CS A0~A12 Microcomputer RAM D0~D7 WR A0~A15 Y Y
HC138 Y Y
XIN A8~A15 XOUT ALE Microcomputer LE HC373 AD0~AD7 D Q
A0~A15
ALE
LE HC373
CE A0~A12 ROM D0~D7 A0 OE Q
CS A0~A12 RAM D0~D7 WR
AD0~AD7
D
RD WR C/D RESET INT INT Interrupt control circuit D0~D7 WR CS Power-on reset circuit R8A66174SP SDATA SCLK OE LATCH
RD WR RESET INT INT Interrupt control circuit C/D D0~D7 WR CS R8A66174SP SDATA SCLK OE LATCH
Power-on reset circuit
RESET
RESET
LED illuminating unit
7-segment display unit
CKS OE CKL SQP R8A66160 A R8A66160 CKS OE CKL SQP
A
CKS
OE
CKL SQP
R8A66160
....
CKS A
OE
CKL
A
R8A66160
.... ....
Fig. 3 Application example 1(PPC copying machine eraser circuit)
Fig. 4 Application example 2(Panel display circuit)
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 10 of 11
R8A66174SP PACKAGE OUTLINE
Package 20pin SOP RENESAS Code PRSP0020DG-A Previous Code 20P2X-C
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 11 of 11

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