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HD74LS194A
4-bit Bidirectional Universal Shift Register
REJ03D0456-0300 Rev.3.00 Jul.15.2005 The bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and leftshift serial inputs. Operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely; * * * * Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are low. * Ordering Information
Part Name HD74LS194AP HD74LS194AFPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.
Pin Arrangement
Clear Shift Right Serial Input A Parallel Inputs B C D Shift Left Serial Input GND
1 CLR 2 3 4 5 6 7 8 R A B C D L S0 QA QB QC QD CK S1
16 15 14 13 12 11 10 9
VCC QA QB QC QD Clock S1 S0 Mode Control Parallel Outputs
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7
HD74LS194A
Function Table
Clear L H H H H H H H Notes: 1. 2. 3. 4. Mode S1 X X H L L H H L S0 X X H H H L L L Clock X L X Inputs Serial Left Right X X X X X X X H X L H X L X X X Outputs A X X a X X X X X Parallel B C X X X X b c X X X X X X X X X X D X X d X X X X X QA L QA0 a H L QBn QBn QAo QB L QB0 b QAn QAn QCn QCn QBo QC L QC0 c QBn QBn QDn QDn QCo QD L QD0 d QCn QCn H L QDo
H; high level, L; low level, X; irrelevant ; transition from low to high level a to d; the level of steady-state input at inputs A, B, C, or D, respectively QA0 to QD0; the level of QA, QB, QC, or QD, respectively before the indicated steady-state input conditions were established. 5. QAn to QDn; the level of QA, QB, QC, or QD, respectively before the most-recent transition of the clock.
Block Diagram
Parallel Inputs A B C D
Mode Control Inputs
S1 S0 Shift Right Serial Input Shift Left Serial Input
S QA CK R Clear
S QB CK R Clear
S QC CK R Clear
S QD CK R Clear
Clock Clear QA QB QC QD
Parallel Outputs
Rev.3.00, Jul.15.2005, page 2 of 7
HD74LS194A
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width Mode Control Setup time A, B, C, D, R, L CLR (inactive state) tsu Symbol VCC IOH IOL Topr clock tw (CK) tw (CLR) Min 4.75 -- -- -20 0 20 20 30 20 25 th 0 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns ns
Hold time
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** Input clamp voltage IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 15 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 23 -1.5 Unit V V V V A mA mA mA mA V Condition
Input current
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Notes: * VCC = 5 V, Ta = 25C ** With all outputs open, inputs A through D grounded, and 4.5 V applied to S0, S1, clear and the serial inputs, ICC is tested with a momentary GND, then 4.5 V, applied to clock.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Symbol max tPHL tPLH tPHL Inputs Clear Clock Clock Outputs min. 25 -- -- -- typ. 36 19 14 17 max. -- 30 22 26 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 k
Q
Rev.3.00, Jul.15.2005, page 3 of 7
HD74LS194A
Count Sequences
Clock Mode Control Inputs S0 S1 Clear Serial Inputs R L A Parallel Inputs B C D QA QB Outputs QC QD Shift Right Clear Load Shift Left Inhibit Clear
H L H L
Testing Method
Test Circuit
4.5V VCC Output
RL CK Input P.G. Zout = 50 QA CL Output R L A B C D CLR QB Output QC Output QD
Load circuit 1
See Testing Table
S0 S1
Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1.
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.3.00, Jul.15.2005, page 4 of 7
HD74LS194A Testing Table
Item max tPLH tPHL From input to output right-shift left-shift ClearQ ClockQ Inputs CLR 4.5V 4.5V IN 4.5V 4.5V S1 4.5V GND 4.5V 4.5V 4.5V S0 GND 4.5V 4.5V GND GND CK IN IN IN IN IN L 4.5V IN GND 4.5V IN R IN 4.5V GND IN 4.5V A GND GND 4.5V GND GND B GND GND 4.5V GND GND C GND GND 4.5V GND GND D GND GND 4.5V GND GND
Item max tPLH tPHL
From input to output right-shift left-shift ClearQ ClockQ
Outputs QA OUT OUT OUT OUT OUT QB OUT OUT OUT OUT OUT QC OUT OUT OUT OUT OUT QD OUT OUT OUT OUT OUT
Waveforms 1 (max, CKQ)
tTLH tTHL tn tn+1 tn tn+1 3V 1.3V th tTHL L, R tPHL 1.3V 90% 1.3V 10% tPLH tPHL tsu 1.3V th tTLH 90% 1.3V tPLH VOH Q 1.3V 1.3V 1.3V 1.3V VOL 3V 0V 1.3V 0V
CK 10%
90% 90% 1.3V 1.3V 10% tw (CK) tsu
10%
Notes:
1. Right-shift is measured with QA at tn + 1, QB at tn + 2, QC at tn + 3, and QD at tn + 4. Left-shift is measured with QA at tn + 4, QB at tn + 3, QC at tn + 2, and QD at tn + 1.
Rev.3.00, Jul.15.2005, page 5 of 7
HD74LS194A Waveforms 2 (ClearQ)
tTLH 90% CK 1.3V 10% 10% tTHL 90% 1.3V 10% tPLH Q tw tPHL 1.3V 1.3V 1.3V VOL tPLH VOH 3V 1.3V 0V tTHL 90% 1.3V 0V 3V
Clear
Notes: Input pulse; tTLH 15 ns, tTHL 6 ns
Rev.3.00, Jul.15.2005, page 6 of 7
HD74LS194A
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jul.15.2005, page 7 of 7
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