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| M35075-XXXFP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DESCRIPTION The M35075-XXXFP is a character pattern display control IC can display on the CRT display the liquid crystal display and the plasma display. It uses a silicon gate CMOS process and it housed in a 24-pin shrink SOP package (M35075-XXXFP). For M35075-001FP that is a standard ROM version of M35075XXXFP respectively, the character pattern is also mentioned. REJ03B0180-0110 Rev.1.10 Feb 13, 2006 PIN CONFIGURATION (TOP VIEW) CPOUT 1 VSS2 2 AC 3 CS 4 SCK/SCL 5 SIN/SDA 6 TCK 7 P6 8 P7 9 VDD1 10 NC 11 NC 12 24 NC FEATURES VDD2 23 22 P5/B 21 P4 20 P3/G 19 P2 18 P1/R 17 P0/BLNK0 16 BIN 15 VSS1 14 VERT 13 HOR M35075 - XXXFP * Screen composition ................................ 24 characters 12 lines * Number of characters displayed ................................... 288 (Max.) * Character composition ..................................... 12 18 dot matrix * Characters available ..................... ROM character:255 characters * * * * * RAM character:8 characters Character sizes available .................... 4 (vertical) 2 (horizontal) Display locations available Horizontal direction .............................................. 2007 locations Vertical direction .................................................. 2047 locations Blinking .................................................................. Character units Cycle : division of vertical synchronization signal into 32 or 64 Duty : 25%, 50%, or 75% Data input ............................. By the I2C-BUS serial input function Coloring for ROM character Character color ..................................... 8 colors (Character unit) Background coloring ............................. 8 colors (Character unit) Border (shadow) coloring ..................... 8 colors (unit of screen / character unit) Raster coloring.......................................8 colors (unit of screen) Blanking for ROM character Character size blanking Border size blanking Matrix-outline blanking All blanking (all raster area) Outline 24P2Q * * APPLICATION CRT display, Liquid crystal display, Plasma display * * Coloring for RAM character................................8 colors (dot by dot) * Blanking for RAM character Character size blanking Matrix-outline blanking All blanking (all raster area) * Output ports * * * * * 4 shared output ports (toggled between RGB output) 4 dedicated output ports Display RAM erase function Display input frequency range ....... FOSC = 20.0MHz to 110.0MHz Horizontal synchronous input frequency ........................................................ H.sync = 15 kHz to 130 kHz Display oscillation stop function * Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 1 of 44 M35075-XXXFP PIN DESCRIPTION Pin Number 1 2 3 4 Symbol CPOUT VSS2 __ Pin name Filter output Earthing pin Auto-clear input Chip select input Input/ Output Output - Input Input Function Filter output. Connect loop filter to this pin. Please connect to GND using circuit earthing pin. When "L", this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. AC __ CS 5 SCK/SCL Clock input Input 6 SIN/SDA Data input Input Data I/O I/O 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TCK P6 P7 VDD1 NC NC HOR VERT VSS1 BIN P0/BLNK0 P1/R P2 P3/G P4 P5/B VDD2 NC External clock Port P6 output Port P7 output Power pin - - Horizontal synchronous signal input Vertical synchronous signal input Earthing pin Test pin Port P0 output Port P1 output Port P2 output Port P3 output Port P4 output Port P5 output Power pin - Input Output Output - - - Input Input - Input Output Output Output Output Output Output - - Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 2 of 44 BLOCK DIAGRAM M35075-XXXFP TCK HOR VERT 14 13 7 1 CPOUT Rev.1.10 Feb 13, 2006 REJ03B0180-0110 Clock oscillation circuit display Polarity switching circuit Synchronous signal switching circuit 17 P0/BLNK0 Timing generator H counter 18 P1/R 20 P3/G Polarity switching circuit CS 4 SCK/SCL 5 Input control circuit page 3 of 44 Display location detection circuit Reading address control circuit Blinking circuit Port output control circuit Shift register Display control circuit 8 9 SIN/SDA 6 VDD1 10 Data control circuit Address control circuit VDD2 23 VSS1 15 Display control register 22 P5/B VSS2 2 AC 3 TEST 16 Display RAM 19 P2 21 P4 Display character RAM P6 Display character ROM P7 M35075-XXXFP MEMORY CONSTITUTION Address 00016 to 11F16 are assigned to the display RAM, address 12016 to 12916 are assigned to the display control registers and address 20016 to 2F116 are assigned to the RAM characters. The internal circuit is reset and all display control registers (address 12016 to 12916) are set to "0" when the AC pin level is "L". And then, RAM is not erased and be undefinited. For detail, see "DATA INPUT EXAMPLE". Memory constitution is shown in Figure 1 to 9. Addresses 00016 00116 DAF 0 0 DAE BB BB DAD BG BG DAC BR BR DAB BLINK BLINK Blinking DAA B B DA9 G G DA8 R R DA7 C7 C7 DA6 C6 C6 DA5 C5 C5 DA4 C4 C4 DA3 C3 C3 DA2 C2 C2 DA1 C1 C1 DA0 C0 C0 11E16 11F16 12016 12116 12216 12316 12416 12516 12616 12716 12816 12916 Fig.1 Memory constitution (Display RAM, Display Control register) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 ......... 0 0 0 0 0 0 0 0 0 0 0 0 ......... BB BB Background coloring BG BG BR BR Character color Character code BLINK BLINK B B G G DIV9 DIVS1 R R DIV8 DIVS0 C7 C7 DIV7 PTC7 C6 C6 DIV6 PTC6 PTD6 HP6 VP6 DSP6 LIN8 LIN16 C5 C5 DIV5 PTC5 PTD5 HP5 VP5 DSP5 LIN7 LIN15 C4 C4 DIV4 PTC4 PTD4 HP4 VP4 DSP4 LIN6 LIN14 C3 C3 DIV3 PTC3 PTD3 HP3 VP3 DSP3 LIN5 LIN13 C2 C2 DIV2 PTC2 PTD2 HP2 VP2 DSP2 LIN4 LIN12 C1 C1 DIV1 PTC1 PTD1 HP1 VP1 DSP1 LIN3 LIN11 C0 C0 DIV0 PTC0 PTD0 HP0 VP0 DSP0 LIN2 LIN10 SPACE2 SPACE1 SPACE0 TEST10 DIV10 EXCK1 EXCK0 RSEL1 RSEL0 DIVS2 TEST17 TEST16 TEST15 TEST14 TEST13 TEST12 TEST11 PTD7 TEST3 TEST2 TEST1 TEST0 HP10 HP9 VP9 DSP9 HP8 VP8 DSP8 HP7 VP7 DSP7 LIN9 TEST20 RBLK0 TEST19 TEST18 VP10 TEST23 TEST22 TEST21 DSP11 DSP10 TEST24 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 TEST25 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 TEST29 TEST32 HSZ20 TEST31 HSZ10 BETA14 TEST28 TEST27 TEST26 TEST30 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1 FB BLK0 FG POLH FR POLV RB VMASK RG B/F RR BCOL page 4 of 44 M35075-XXXFP Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 DAF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAE BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS DAD GS GS GS GS GS GS GS GS GS GS GS GS GS GS GS GS GS GS DAC RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR000B FR000A FR0009 FR0008 FR0007 FR0009 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000 FR001B FR001A FR0019 FR0018 FR0017 FR0019 FR0015 FR0014 FR0013 FR0012 FR0011 FR0010 FR002B FR002A FR0029 FR0028 FR0027 FR0026 FR0025 FR0024 FR0023 FR0022 FR0021 FR0020 FR003B FR003A FR0039 FR0038 FR0037 FR0036 FR0035 FR0034 FR0033 FR0032 FR0031 FR0030 FR004B FR004A FR0049 FR0048 FR0047 FR0046 FR0045 FR0044 FR0043 FR0042 FR0041 FR0040 FR005B FR005A FR0059 FR0058 FR0057 FR0056 FR0055 FR0054 FR0053 FR0052 FR0051 FR0050 FR006B FR006A FR0069 FR0068 FR0067 FR0066 FR0065 FR0064 FR0063 FR0062 FR0061 FR0060 FR007B FR007A FR0079 FR0078 FR0077 FR0076 FR0075 FR0074 FR0073 FR0072 FR0071 FR0070 FR008B FR008A FR0089 FR0088 FR0087 FR0086 FR0085 FR0084 FR0083 FR0082 FR0081 FR0080 FR009B FR009A FR0099 FR0098 FR0097 FR0096 FR0095 FR0094 FR0093 FR0092 FR0091 FR0090 FR00AB FR00AA FR00A9 FR00A8 FR00A7 FR00A6 FR00A5 FR00A4 FR00A3 FR00A2 FR00A1 FR00A0 FR00BB FR00BA FR00B9 FR00B8 FR00B7 FR00B6 FR00B5 FR00B4 FR00B3 FR00B2 FR00B1 FR00B0 FR00CB FR00CA FR00C9 FR00C8 FR00C7 FR00C6 FR00C5 FR00C4 FR00C3 FR00C2 FR00C1 FR00C0 FR00DB FR00DA FR00D9 FR00D8 FR00D7 FR00D6 FR00D5 FR00D4 FR00D3 FR00D2 FR00D1 FR00D0 FR00EB FR00EA FR00E9 FR00E8 FR00E7 FR00E6 FR00E5 FR00E4 FR00E3 FR00E2 FR00E1 FR00E0 FR00FB FR00FA FR00F9 FR00F8 FR00F7 FR00F6 FR00F5 FR00F4 FR00F3 FR00F2 FR00F1 FR00F0 FR010B FR010A FR0109 FR0108 FR0107 FR0106 FR0105 FR0104 FR0103 FR0102 FR0101 FR0100 FR011B FR011A FR0119 FR0118 FR0117 FR0116 FR0115 FR0114 FR0113 FR0112 FR0111 FR0110 ........ 21216 Can not be used 21F16 Fig.2 Memory constitution (RAM character 0) Address 22016 22116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR100B FR100A FR1009 FR1008 FR1007 FR1006 FR1005 FR1004 FR1003 FR1002 FR1001 FR1000 ........ RAM character 1 data 23016 23116 23216 0 BS GS RS FR111B FR111A FR1119 FR1118 FR1117 FR1116 FR1115 FR1114 FR1113 FR1112 FR1111 FR1110 ........ Can not be used 23F16 Fig.3 Memory constitution (RAM character 1) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 5 of 44 M35075-XXXFP Address 24016 24116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR200B FR200A FR2009 FR2008 FR2007 FR2006 FR2005 FR2004 FR2003 FR2002 FR2001 FR2000 ........ RAM character 2 data 25016 25116 25216 0 BS GS RS FR211B FR211A FR2119 FR2118 FR2117 FR2116 FR2115 FR2114 FR2113 FR2112 FR2111 FR2110 ........ Can not be used 25F16 Fig.4 Memory constitution (RAM character 2) Address 26016 26116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR300B FR300A FR3009 FR3008 FR3007 FR3006 FR3005 FR3004 FR3003 FR3002 FR3001 FR3000 ........ RAM character 3 data 27016 27116 27216 0 BS GS RS FR311B FR311A FR3119 FR3118 FR3117 FR3116 FR3115 FR3114 FR3113 FR3112 FR3111 FR3110 ........ Can not be used 27F16 Fig.5 Memory constitution (RAM character 3) Address 28016 28116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR400B FR400A FR4009 FR4008 FR4007 FR4006 FR4005 FR4004 FR4003 FR4002 FR4001 FR4000 ........ RAM character 4 data 29016 29116 29216 0 BS GS RS FR411B FR411A FR4119 FR4118 FR4117 FR4116 FR4115 FR4114 FR4113 FR4112 FR4111 FR4510 ........ Can not be used 29F16 Fig.6 Memory constitution (RAM character 4) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 6 of 44 M35075-XXXFP Address 2A016 2A116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 D00 FR500B FR500A FR5009 FR5008 FR5007 FR5006 FR5005 FR5004 FR5003 FR5002 FR5001 FR5000 ........ RAM character 5 data 2B016 2B116 2B216 0 BS GS RS FR511B FR511A FR5119 FR5118 FR5117 FR5116 FR5115 FR5114 FR5113 FR5112 FR5111 FR5110 ........ Can not be used 2BF16 Fig.7 Memory constitution (RAM character 5) Address 2C016 2C116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR600B FR600A FR6009 FR6008 FR6007 FR6006 FR6005 FR6004 FR6003 FR6002 FR6001 FR6000 ........ RAM character 6 data 2D016 2D116 2D216 0 BS GS RS FR611B FR611A FR6119 FR6118 FR6117 FR6116 FR6115 FR6114 FR6113 FR6112 FR6111 FR6110 ........ Can not be used 2DF16 Fig.8 Memory constitution (RAM character 6) Address 2E016 2E116 DAF 0 DAE BS DAD GS DAC RS DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FR700B FR700A FR7009 FR7008 FR7007 FR7006 FR7005 FR7004 FR7003 FR7002 FR7001 FR7000 ........ RAM character 7 data 2F016 2F116 0 BS GS RS FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 Fig.9 Memory constitution (RAM character 7) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 7 of 44 M35075-XXXFP SCREEN CONSTITUTION The screen lines and rows are determined from each address of the display RAM . The screen constitution is shown in Figure 10. Row Line 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C16 00D16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 01816 01916 01A16 01B16 01C16 01D16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C16 02D16 02E16 02F16 03016 03116 03216 03316 03416 03516 03616 03716 03816 03916 03A16 03B16 03C16 03D16 03E16 03F16 04016 04116 04216 04316 04416 04516 04616 04716 04816 04916 04A16 04B16 04C16 04D16 04E16 04F16 05016 05116 05216 05316 05416 05516 05616 05716 05816 05916 05A16 05B16 05C16 05D16 05E16 05F16 06016 06116 06216 06316 06416 06516 06616 06716 06816 06916 06A16 06B16 06C16 06D16 06E16 06F16 07016 07116 07216 07316 07416 07516 07616 07716 07816 07916 07A16 07B16 07C16 07D16 07E16 07F16 08016 08116 08216 08316 08416 08516 08616 08716 08816 08916 08A16 08B16 08C16 08D16 08E16 08F16 09016 09116 09216 09316 09416 09516 09616 09716 09816 09916 09A16 09B16 09C16 09D16 09E16 09F16 0A016 0A116 0A216 0A316 0A416 0A516 0A616 0A716 0A816 0A916 0AA16 0AB16 0AC16 0AD16 0AE16 0AF16 0B016 0B116 0B216 0B316 0B416 0B516 0B616 0B716 0B816 0B916 0BA16 0BB16 0BC16 0BD16 0BE16 0BF16 0C016 0C116 0C216 0C316 0C416 0C516 0C616 0C716 0C816 0C916 0CA16 0CB16 0CC16 0CD16 0CE16 0CF16 0D016 0D116 0D216 0D316 0D416 0D516 0D616 0D716 0D816 0D916 0DA16 0DB16 0DC16 0DD16 0DE16 0DF16 0E016 0E116 0E216 0E316 0E416 0E516 0E616 0E716 0E816 0E916 0EA16 0EB16 0EC16 0ED16 0EE16 0EF16 0F016 0F116 0F216 0F316 0F416 0F516 0F616 0F716 0F816 0F916 0FA16 0FB16 0FC16 0FD16 0FE16 0FF16 10016 10116 10216 10316 10416 10516 10616 10716 10816 10916 10A16 10B16 10C16 10D16 10E16 10F16 11016 11116 11216 11316 11416 11516 11616 11716 11816 11916 11A16 11B16 11C16 11D16 11E16 11F16 The hexadecimal numbers in the boxes show the display RAM address. Fig.10 Screen constitution RAM Character CONSTITUTION The dot lines and dot rows of the character RAM are determined from each address and bit of the character RAM . The RAM character constitution is shown in Figure 11. Dot Dot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 FRn00B FRn01B FRn02B FRn03B FRn04B FRn05B FRn06B FRn07B FRn08B FRn09B 2 3 4 5 6 7 8 9 10 11 12 FRn00A FRn009 FRn008 FRn007 FRn006 FRn005 FRn004 FRn003 FRn002 FRn001 FRn000 FRn01A FRn019 FRn018 FRn017 FRn016 FRn015 FRn014 FRn013 FRn012 FRn011 FRn010 FRn02A FRn029 FRn028 FRn027 FRn026 FRn025 FRn024 FRn023 FRn022 FRn021 FRn020 FRn03A FRn039 FRn038 FRn037 FRn036 FRn035 FRn034 FRn033 FRn032 FRn031 FRn030 FRn04A FRn049 FRn048 FRn047 FRn046 FRn045 FRn044 FRn043 FRn042 FRn041 FRn040 FRn05A FRn059 FRn058 FRn057 FRn056 FRn055 FRn054 FRn053 FRn052 FRn051 FRn050 FRn06A FRn069 FRn068 FRn067 FRn066 FRn065 FRn064 FRn063 FRn062 FRn061 FRn060 FRn07A FRn079 FRn078 FRn077 FRn076 FRn075 FRn074 FRn073 FRn072 FRn071 FRn070 FRn08A FRn089 FRn088 FRn087 FRn086 FRn085 FRn084 FRn083 FRn082 FRn081 FRn080 FRn09A FRn099 FRn098 FRn097 FRn096 FRn095 FRn094 FRn093 FRn092 FRn091 FRn090 FRn0AB FRn0AA FRn0A9 FRn0A8 FRn0A7 FRn0A6 FRn0A5 FRn0A4 FRn0A3 FRn0A2 FRn0A1 FRn0A0 FRn0BB FRn0BA FRn0B9 FRn0B8 FRn0B7 FRn0B6 FRn0B5 FRn0B4 FRn0B3 FRn0B2 FRn0B1 FRn0B0 FRn0CB FRn0CA FRn0C9 FRn0C8 FRn0C7 FRn0C6 FRn0C5 FRn0C4 FRn0C3 FRn0C2 FRn0C1 FRn0C0 FRn0DB FRn0DA FRn0D9 FRn0D8 FRn0D7 FRn0D6 FRn0D5 FRn0D4 FRn0D3 FRn0D2 FRn0D1 FRn0D0 FRn0EB FRn0EA FRn0E9 FRn0E8 FRn0E7 FRn0E6 FRn0E5 FRn0E4 FRn0E3 FRn0E2 FRn0E1 FRn0E0 FRn0FB FRn0FA FRn0F9 FRn0F8 FRn0F7 FRn0F6 FRn0F5 FRn0F4 FRn0F3 FRn0F2 FRn0F1 FRn0F0 FRn10B FRn11B FRn10A FRn109 FRn108 FRn107 FRn106 FRn105 FRn104 FRn103 FRn102 FRn101 FRn100 FRn11A FRn119 FRn118 FRn117 FRn116 FRn115 FRn114 FRn113 FRn112 FRn111 FRn110 The number in the boxes show the bit address of the RAM character :n. ("n" is RAM number : 0 to 7) Fig.11 RAM charcter consititution Note. When the RAM character is used, it is necessary to clear all areas of the RAM character first. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 8 of 44 M35075-XXXFP DISPLAY RAM Address 00016 to 11F16 Contents DA Register Status 0 0 C0 1 0 1 C1 1 0 2 C2 1 0 3 C3 1 0 4 C4 1 0 5 C5 1 0 6 C6 1 0 7 C7 1 0 8 R 1 0 9 G 1 0 A B 1 0 B BLINK 1 0 C BR 1 0 D BG 1 0 E BB 1 Blinking BB 0 0 0 0 1 1 1 1 BG 0 0 1 1 0 0 1 1 ____ Remarks Function Set the displayed ROM character code. Set display character *RAM character is selected using the 8 bits from C7 to C0. When C7 to C0=(111111102) is set. And, RAM character code is set to R, G and B. B 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 RAM character code RAM character 0 RAM character 1 RAM character 2 RAM character 3 RAM character 4 RAM character 5 RAM character 6 RAM character 7 B 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Color Black Red Green Yellow Blue Magenta Cyan White Set character color (character unit) * When set C7 to C0= (111111102), can be set RAM character code. Do not blink. Set blinking See register BLINK2 to BLINK0 (address12916) BR 0 1 0 1 0 1 0 1 Color Black Red Green Yellow Blue Magenta Cyan White Set character background color. (character unit) * When set C7 to C0=(111111102) and register RBLK0 (address 12416)= "1", set coloring prohibition color. Moreover, when the blink is set, the parts other than the color set by this register are blinks. See DISPLAY FORM 2. Note. The display RAM is undefined state at the AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 9 of 44 M35075-XXXFP REGISTERS DESCRIPTION (1) Address 12016 Contents DA Register Status 0 0 DIV0 1 0 1 DIV1 1 0 2 DIV2 1 0 3 DIV3 1 0 4 DIV4 1 0 5 DIV5 1 0 6 DIV6 1 0 7 DIV7 1 0 8 DIV8 1 0 9 DIV9 1 0 A DIV10 1 0 B TEST10 1 0 C SPACE0 1 0 D SPACE1 1 0 E SPACE2 1 Note. The mark 2 0 0 0 0 1 1 1 1 SPACE 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Number of Lines and Space <(S) represents space> 10 Remarks Function Set division value (multiply value) of horizontal oscillation frequency. Set display frequency by division value (multiply value) setting. For details, see REGISTER SUPPLEMENTARY DESCRIPTION (1). Also, set the display frequency range by registers DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1(address 12116) in accordance with the display frequency. Any of this settings above is required only when EXCK1 = 0, EXCK0 = 1 and EXCK1 = 1, EXCK0 = 1. N1 = n=0 (DIVn 2n) N1 : division value (multiply value) It should be fixed to "0". Can not be used. Leave one line worth of space in the vertical direction. For example, 6 (S) 6 indicates two sets of 6 lines with a line of spaces between lines 6 and 7. A line is 18 N horizontal scan lines. N is determined by the character size in the vertical direction 12 1 (S) 10 (S) 1 2 (S) 8 (S) 2 3 (S) 6 (S) 3 4 (S) 4 (S) 4 5 (S) 2 (S) 5 6 (S) 6 6 (S)(S) 6 (S) represents one line worth of space around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 10 of 44 M35075-XXXFP (2) Address 12116 Contents DA Register Status 0 0 PTC0 1 0 1 PTC1 1 0 2 PTC2 1 0 3 PTC3 1 0 4 PTC4 1 0 5 PTC5 1 0 6 PTC6 1 0 7 PTC7 1 0 8 DIVS0 1 0 9 DIVS1 1 0 A DIVS2 1 0 B RSEL0 1 0 C RSEL1 1 0 D EXCK0 1 0 E EXCK1 1 Display clock input EXCK1 EXCK0 0 External synchronous (external clock) 0 1 Internal synchronous 0 0 Do not set 1 1 External synchronous (internal clock) 1 Function P0 output (port P0). Remarks P0 pin output control. BLNK0 output. P1 output (port P1). P1 pin output control. R signal output. P2 output (port P2). P2 pin output control. Can not be used. P3 output (port P3). P3 pin output control. G signal output. P4 output (port P4). P4 pin output control. Can not be used. P5 output (port P5). P5 pin output control. B signal output. P6 output (port P6). P6 pin output control. Can not be used. P7 output (port P7). P7 pin output control. Can not be used. For setting, see REGISTER SUPPLEMENTARY DESCRIPTION (2). Set display frequency range. Display clock setting See REGISTER SUPPLEMENTARY DESCRIPTION (1) Note. The mark around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 11 of 44 M35075-XXXFP (3) Address 12216 DA Register Contents Status 0 0 PTD0 1 0 1 PTD1 1 0 2 PTD2 1 0 3 PTD3 1 0 4 PTD4 1 0 5 PTD5 1 0 6 PTD6 1 0 7 PTD7 1 0 8 TEST11 1 0 9 TEST12 1 0 A TEST13 1 0 B TEST14 1 0 C TEST15 1 0 D TEST16 1 0 E TEST17 1 Can not be used. It should be fixed to "0". Can not be used. Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". It should be fixed to "1". It should be fixed to "0". "H" output. Can not be used. "H" output. "L" output. P7 pin data control. "H" output or positive polarity output (B signal output). "L" output. P6 pin data control. "H" output. "L" output or negative polarity output (B signal output). P5 pin data control. "H" output or positive polarity output (G signal output). "L" output. P4 pin data control. "H" output. "L" output or negative polarity output (G signal output). P3 pin data control. "H" output or positive polarity output (R signal output). "L" output. P2 pin data control. "H" output or positive polarity output (BLNK0 output). "L" output or negative polarity output (R signal output). P1 pin data control. Function "L" output or negative polarity output (BLNK0 output). P0 pin data control. Remarks Note. The mark around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 12 of 44 M35075-XXXFP (4) Address 12316 DA Register HP0 1 0 1 HP1 1 0 2 HP2 1 0 3 HP3 1 0 4 HP4 1 HOR Contents Status 0 Function If HS is the horizontal display start location, HS = T ( 2nNPn+m) n=0 10 Remarks Horizontal display start location is specified using the 11 bits from HP10 to HP0. HP10 to HP0 = (000000000002) and (000001001112) setting is forbidden. 0 T: Period of display frequency 2007 settings are possible. m : offset value differ for the setting of the register EXCK0 and EXCK1. It shown below. EXCK1 EXCK0 m 0 0 13 0 1 13 1 0 Do not set 1 1 19 0 5 HP5 1 0 6 HP6 VERT VS Note 2 HS*(shown left) shows horizontal display start location this is register B/F (address 12916) = "0" is set. 1 0 7 HP7 1 0 8 HP8 1 0 9 HP9 1 0 A HP10 1 0 B TEST0 1 0 C TEST1 1 0 D TEST2 1 0 E TEST3 1 HS Note 2 OSD Display area Note 2 Note 2 Monitor Screen It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. _____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 13 of 44 M35075-XXXFP (5) Address 12416 DA Contents Register Status 0 0 VP0 1 1 0 VP1 1 2 0 VP2 1 HOR Function If VS is the vertical display start location, 10 Remarks The vertical start location is specified using the 11 bits from VP10 to VP0. VP10 to VP0 = (000000000002) setting is forbidden. VS = H n=0 2nVPn T: Cycle with the horizonal synchronizing pulse 2047 settings are possible. 3 0 VP3 1 HS*(shown left) shows horizontal display start location this is register B/F (address 12916) = "0" is set. 4 0 VP4 VERT VS Note 2 1 5 0 VP5 1 6 0 VP6 1 HS Note 2 OSD Display area Note 2 Note 2 Monitor Screen 7 0 VP7 1 8 0 VP8 1 9 0 VP9 1 A 0 VP10 1 . B 0 TEST18 1 It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. Matrix-outline size. Charcter size. (Note 3) It should be fixed to "0". Can not be used. _____ C 0 TEST19 1 0 D RBLK0 1 0 Sets the blanking mode of RAM character. See DISPLAY FORM 2. E TEST20 1 Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds. 3. The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF". Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 14 of 44 M35075-XXXFP (6) Address 12516 DA Contents Register Status 0 0 DSP0 1 1 0 DSP1 1 2 0 DSP2 1 3 0 DSP3 1 (At register BCOL="0") 4 0 DSP4 1 5 0 DSP5 1 6 0 DSP6 1 7 0 DSP7 1 8 0 DSP8 1 9 0 DSP9 1 A 0 DSP10 1 B 0 DSP11 1 C 0 TEST21 1 0 D TEST22 1 0 E TEST23 1 Note. The mark BLK1 0 0 1 1 BLK0 0 1 0 1 DSPn="0" Matrix-outline border Character Border Matrix-outline DSPn="1" Matrix-outline Border Matrix-outline Charcter Function The display modes of display screen inside n+1 line by DSPn (n=0 to 11) The display mode decided by the combination with registers BLK1 and BLK0 (address 12916). Settings are given below. Remarks Sets the display mode of line 1. Sets the display mode of line 2. Sets the display mode of line 3. Sets the display mode of line 4. Sets the display mode of line 5. For detail, see DISPLAY FORM 1 (1). Sets the display mode of line 6. Sets the display mode of line 7. Sets the display mode of line 8. Sets the display mode of line 9. Sets the display mode of line 10. Sets the display mode of line 11. Sets the display mode of line 12. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 15 of 44 M35075-XXXFP (7) Address 12616 DA Contents Register Status 0 LIN2 0 1 1 0 LIN3 1 2 LIN4 0 1 LINn = "0" LINn = "1" Refer to VSZ1H0 and VSZ1H1 Function The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another. Remarks Character size setting in the vertical direction for the 2nd line. Character size setting in the vertical direction for the 3rd line. Character size setting in the vertical direction for the 4th line. 3 LIN5 0 1 1st line Refer to VSZ1L0 and VSZ1L1 Character size setting in the vertical direction for the 5th line. 2nd to 12th Refer to VSZ2L0 Refer to VSZ2H0 and VSZ2L1 and VSZ2H1 line 4 0 LIN6 1 Character size setting in the vertical direction for the 6th line. 5 LIN7 0 1 Character size setting in the vertical direction for the 7th line. 6 LIN8 0 1 Character size setting in the vertical direction for the 8th line. 7 LIN9 0 1 Character size setting in the vertical direction for the 9th line. 8 0 V1SZ0 1 H: Cycle with the horizontal synchronizing pulse V1SZ1 V1SZ0 0 0 0 1 1 0 1 1 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot Character size setting in the vertical direction for the 1st line. (display monitor 1 to 12 line) 9 V1SZ1 0 1 A VSZ1L0 0 1 H: Cycle with the horizontal synchronizing pulse VSZ1L1 VSZ1L0 Vertical direction size 0 0 1H/dot 0 1 2H/dot 1 0 3H/dot 1 1 4H/dot Character size setting in the vertical direction (display monitor 1 line) at "0" state in register LIN2 to LIN17 (address 12616, 12716). B 0 VSZ1L1 1 C VSZ1H0 0 1 0 H: Cycle with the horizontal synchronizing pulse VSZ1H1 VSZ1H0 Vertical direction size 0 0 1H/dot 0 1 2H/dot 1 0 3H/dot 1 1 4H/dot Character size setting in the vertical direction (display monitor 1 line) at "1" state in register LIN2 to LIN17 (address 12616, 12716). D VSZ1H1 1 0 1 E TEST24 It should be fixed to "0". Can not be used. Note. The mark around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 16 of 44 M35075-XXXFP (8) Address 12716 DA Contents Register Status 0 0 LIN10 1 0 1 LIN11 1 0 2 LIN12 1 0 3 LIN13 1 0 4 LIN14 1 0 5 LIN15 1 0 6 LIN16 1 0 7 LIN17 1 0 8 V18SZ0 1 0 9 V18SZ1 1 0 A VSZ2L0 1 0 B VSZ2L1 1 0 C VSZ2H0 1 0 D VSZ2H1 1 0 E TEST25 1 H: Cycle with the horizontal synchronizing pulse V18SZ1 V18SZ0 Vertical direction size 0 0 1H/dot 0 1 2H/dot 1 0 3H/dot 1 1 4H/dot 1st line LINn = "0" Refer to VSZ1L0 and VSZ1L1 Function The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another. Remarks Character size setting in the vertical direction for the 10th line. Character size setting in the vertical direction for the 11th line. Character size setting in the vertical direction for the 12th line. LINn = "1" Refer to VSZ1H0 and VSZ1H1 Character size setting in the vertical direction for the 13th line. 2nd to 12th Refer to VSZ2L0 Refer to VSZ2H0 and VSZ2L1 and VSZ2H1 line Character size setting in the vertical direction for the 14th line. Character size setting in the vertical direction for the 15th line. Character size setting in the vertical direction for the 16th line. Character size setting in the vertical direction for the 17th line. Character size setting in the vertical direction for the 18th line. (display monitor 1 to 12 line) H: Cycle with the horizontal synchronizing pulse VSZ2L1 VSZ2L0 Vertical direction size 1H/dot 0 0 2H/dot 0 1 3H/dot 1 0 4H/dot 1 1 Character size setting in the vertical direction (display monitor for 2 to 12 line) at "0" state in register LIN2 to LIN17 (address 12616, 12716). H: Cycle with the horizontal synchronizing pulse VSZ2H1 VSZ2H0 Vertical direction size 0 1H/dot 0 2H/dot 1 1 0 3H/dot 0 1 4H/dot 1 Character size setting in the vertical direction (display monitor for 2 to12 line) at "1" state in register LIN2 to LIN17(address 12616, 12716). It should be fixed to "0". Can not be used. Note. The mark around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 17 of 44 M35075-XXXFP (9) Address 12816 DA Contents Register Status 0 0 RR 1 1 0 RG 1 2 0 RB 1 3 0 FR 1 4 0 FG 1 5 0 FB 1 6 0 TEST26 1 7 0 TEST27 1 8 0 TEST28 1 9 0 BETA14 1 A 0 HSZ10 1 B 0 TEST31 1 C 0 HSZ20 1 0 D TEST32 1 0 E TEST29 1 Note. The mark FB 0 0 0 0 1 1 1 1 FG 0 0 1 1 0 0 1 1 FR 0 1 0 1 0 1 0 1 Color Black Red Green Yellow Blue Magenta Cyan White RB 0 0 0 0 1 1 1 1 RG 0 0 1 1 0 0 1 1 RR 0 1 0 1 0 1 0 1 Color Black Red Green Yellow Blue Magenta Cyan White Function Remarks Sets the raster color of all blankings. Set the blanking color of the Border size, or the shadow size. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. Matrix-outline display (12 18 dot) Matrix-outline display (14 18 dot) HSZ10 0 1 Horizontal direction size 1T/dot 2T/dot Charcter size setting in the horizontal direction for the first line. T: Display frequency cycle It should be fixed to "0". Can not be used. HSZ20 0 1 Horizontal direction size 1T/dot 2T/dot Charcter size setting in the horizontal direction for the 2nd line to 12th line. T: Display frequency cycle It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 18 of 44 M35075-XXXFP (10) Address 12916 DA Contents Register Status 0 0 BCOL 1 1 0 B/F 1 2 0 VMASK 1 3 0 POLV 1 4 0 POLH 1 5 0 BLK0 1 6 0 BLK1 1 7 0 SYAD 1 8 0 RAMERS 1 9 0 STOP 1 A 0 DSPON 1 B 0 BLINK0 1 C 0 BLINK1 1 0 D BLINK2 1 0 E TEST30 1 Note. The mark Function Blanking of BLK0, BLK1 All raster blanking Synchronize with the leading edge of horizontal synchronization. Synchronize with the trailing edge of horizontal synchronization. Do not mask by VERT input signal Mask by VERT input signal VERT pin is negative polarity VERT pin is positive polarity HOR pin is negative polarity HOR pin is positive polarity BLK1 0 0 1 1 BLK0 0 1 0 1 Blanking mode Matrix-outline size Character size Border size Matrix-outline size Remarks Sets all raster blanking Synchronize with the front porch or back porch of the horizontal synchronization signal. Set mask at phase comparison operating. Set VERT pin polarity. Set HOR pin polarity. Set blanking mode. See DISPLAY FORM 1 (1). ( When DSPn (address 12516) = "0" ) Border display of character Shadow display of character RAM not erased RAM erased Oscillation of clock for display Stop the oscillation of clock for display Display OFF Display ON BLINK1 BLINK0 0 0 1 0 0 1 1 1 Duty Blinking OFF 25% 50% 75% See DISPLAY FORM 1 (2). When register RAMERS is set to "1", do not stop the display clock. There is no need to reset because there is no register for this bit. Set blinking duty ratio. Divided into 64 of vertical synchronous signal Divided into 32 of vertical synchronous signal It should be fixed to "0". Can not be used. Set blinking frequency. around the status value means the reset status by the "L" level is input to AC pin. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 19 of 44 M35075-XXXFP REGISTER SUPPLEMENTARY DESCRIPTION (1) Setting external clock input and display frequency mode Setting external clock input and display frequency mode (by use of EXCK0, EXCK1 (12116), and DIV10 to DIV0 (12016) as explained here following. (a) When (EXCK1, EXCK0) = (0, 0) ......External clock mode 1 Fosc = 6.3 to 80 MHz (VDD = 4.75 to 5.25 V) Fosc = 6.3 to 40 MHz (VDD = 2.50 to 3.50 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. Do not have to set a display frequency because the clock just as it is entered from outside is used as the display clock. (b) When (EXCK1, EXCK0) = (0, 1) ......Internal clock mode Fosc = 20 to 110 MHz (VDD = 4.75 to 5.25 V) Clock input from the TCK pin is unnecessary. The multiply clock of the internally generated horizontal synchronous signal is used as the display clock. The display frequency is set by setting the multiply value of the horizontal synchronous frequency (of the display frequency) in DIV10 to DIV0 (address 12016). Also, set the display frequency range. (See the next page.) Display frequency is calculated using the below expression. Display frequency = Horizontal synchronous frequency x Multiply value (c) When (EXCK1, EXCK0) = (1, 0) ......... Setting disabled (d) When (EXCK1, EXCK0) = (1, 1) ......External clock mode 2 Fosc = 20 to 110 MHz (VDD = 4.75 to 5.25 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant-period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. An internal clock which is in sync with the external input clock is used as the display clock. Because the display frequency equals the external clock frequency, set N1 (division value) that satisfies the below expressions to DIV10 to DIV0 (address 12016) for make the display frequency is equal to the external clock frequency. N1 = external clock frequency / horizontal synchronous frequency 10 N1 = n=0 2nDIVn Also, set the display frequency range. (See the next page.) Horizontal synchronous signal 1H External clock Number of clock (N1) Fig. 12 Example of external clock input Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 20 of 44 M35075-XXXFP (2) To set display frequency range Whenever setting display frequency (when EXCK1 = "0", EXCK0 = "1", or EXCK1 = "1", EXCK0 = "1"), always set the display frequency range in accordance with the display frequency. This range is set from DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 12116). Frequency ranges are given here below. RSEL1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 RSEL0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DIVS2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 DIVS1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 DIVS0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Display frequency range MHz 100.0 to 110.0 - 92.0 to 100.0 73.0 to 92.0 66.5 to 73.0 - 61.0 to 66.5 49.0 to 61.0 - - 45.5 to 49.0 36.5 to 45.5 33.5 to 36.5 - 30.5 to 33.5 24.5 to 30.5 - - 23.0 to 24.5 20.0 to 23.0 (3) Notes on setting display frequency To change external clock (display) frequency or horizontal synchronization frequency, always use the following procedures. To set EXCK1 = "0", EXCK0 = "1" (a) Turn the display OFF. ... DSPON (address 12916) = "0" (b) Set the display frequency. ... Set from DIV10 to DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 12116). (c) Wait 20 ms while the horizontal synchronization signal is being input. (d) Turn the display ON. ... DSPON (address 12916) = "1" To set EXCK1 = "1", EXCK0 = "1" (a) Turn the display OFF. ... DSPON (address 12916) = "0" (b) Set the display frequency. ... Set from DIV10 to DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 12116). (c) Wait 20 ms while the horizontal synchronization signal and external clock are being input. (d) Turn the display ON. ... DSPON (address 12916) = "1" Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 21 of 44 M35075-XXXFP DISPLAY FORM 1 M35075-XXXFP has the following four display forms. (1) ROM character blanking mode Character size : Blanking same as the character size. Border size : Blanking the background as a size from character. Matrix-outline size : Blanking the background 12 18 dot. All blanking size : When set register BCOL to "1", all raster area is blanking. The display mode and blanking mode can be set line-by-line, as follows, from registers BCOL, BLK1, BLK0 (address 12916), DSP0 to DSP11 (address 12516). BCOL BLK1 0 BLK0 0 1 0 1 0 1 0 1 Line of DSPn = "0" Display mode Matrix-outline border display Line of DSPn = "1" Display mode Matrix-outline display Border display Matrix-outline display Character display Matrix-outline display Border display Blanking mode Matrix-outline size Border size Matrix-outlinesize Character size Blanking mode Matrix-outline size Character size Border size Matrix-outline size 0 0 1 1 0 Character display Border display Matrix-outline display Matrix-outline border display 1 0 1 1 Character display Border display Matrix-outline display All blanking size Matrix-outline display Character display All blanking size (Note 1) 12 dots (Note 2) 12 dots 12 dots 12 dots (Note 2) Scanning R,GorB output BLNK0 output color setting Character color Border color : R,G,B of display RAM Character color : R,G,B of display RAM (Character unit) (Character unit) :Register FR,FG,FB (Display unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) 18 dots Character color : R,G,B of display RAM (Character unit) Border color :BR,BG,BB of display RAM (Character unit) Character color : R,G,B of display RAM (Character unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) (a) Matrix-outline and border display (Matrix-outline size) (b) Character display (Character size) (c) Border display (Border size) (d) Matrix-outline display (Matrix-outline size) ( ) is blanking mode. Note 1. When register BCOL is set to "1", the raster range of the display modes set respectively by BLK1 and BLK0 are colored by registers RR, RG, and RB (address 12816). And the blanking mode is set all blanking size (all raster size) regardless of the BLK1 and BLK0 settings. Note 2. The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be output at 14 dots. Fig. 13 Display form Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 22 of 44 M35075-XXXFP (2) Shadow display When border display mode, if set SYAD (address 12916) = "0" to "1", it change to shadow display mode. Border and shadow display are shown below. Set shadow display color by BR, BG and BB of display RAM or by register FR, FG and FB. Register SYAD(12916 address) = "0" Border display Register SYAD(12916 address) = "1" Shadow display Note : Border display is invalid in RAM characters. Fig.14 Border and shadow display Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 23 of 44 M35075-XXXFP DISPLAY FORM 2 This IC can display both ROM character and RAM character at the same time. The display form is shown in Figure 15 and 16. (1) RAM character blanking mode BCOL 0 1 RBLK0 0 1 0 1 Display mode Matrix-outline display Character display (Note1) Matrix-outline display Character display (Note1) Blanking mode Matrix-outline size Character size (Note2) All blanking size All blanking size Note1: The part of the appointed color by BR, BG and BB of the display RAM changes that is not coloring. Note2: The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF" < Regiser BCOL = "0", RBLK0 = "0"> (Note 1) RAM Character ROM Character RAM Character ROM Character 12dots (Note 2) 12dots (Note 2) Scanning Scanning R,GorB output BLNK0 output Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color : : Matrix-outline display (Matrix- outline size) (b) Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color : : Matrix-outline display (Matrix- outline size) Border color (c) RAM Character ROM Character RAM Character ROM Character 12dots (Note 2) 12dots (Note 2) Scanning Scanning R,GorB output BLNK0 output Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color : : Matrix-outline display (Matrix- outline size) Matrix-outline color (d) Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) FR, FG, FB of register (Display unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color : : : Matrix-outline display (Matrix- outline size) Matrix-outline color Border color (a) ( ) is blanking mode. Refer to DISPLAY FORM 1 about (a)-(d). Fig.15 Display form1 Continue to Next Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 24 of 44 M35075-XXXFP < Register BCOL = "0", RBLK0 = "1"> (Note 1) RAM Character ROM Character RAM Character ROM Character 12dots (Note 2) 12dots (Note 2) Scanning Scanning R,GorB output BLNK0 output Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color . : Coloring prohibition color : Character display (Character size) (b) Color setting R, G, B of display RAM (Character unit) BR, BG, BB of display RAM (Character unit) Display mode (RAM character setting) (ROM character setting) : RAM character code No. Character color : Coloring prohibition color Border color (c) : Character display (Character size) RAM Character ROM Character RAM Character ROM Character 12dots (Note 2) 12dots (Note 2) Scanning Scanning R,GorB output BLNK0 output Color setting (RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) Matrix-outline color BR, BG, BB of display RAM : (Note 3) (Character unit) Display mode : Matrix-outline display (Matrix-outline size) (Note 3) (d) Color setting (RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) (Note 3) Matrix-outline color BR, BG, BB of display RAM : (Character unit) FR, FG, FB of register (Display unit) Display mode : : Matrix-outline display (Matrix-outline size) (Note 3) Border color (a) ( ) is blanking mode. Refer to DISPLAY FORM 1 about (a)-(d). Note 1 : When register BCOL = "1", the raster range of the display modes set respectively by RBLK0 is colored by register RR, RG and RB (address 12816) . And the blanking mode is set all blanking size (all raster size) independent of the RBLK0 settings. Note 2 : The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be output at 14 dots. Note 3 : When display mode (setting by register BLK1, BLK0, DSPn) is Matrix-outline display or Matrix-outline border display, register RBLK0= "1" setting (coloring prohibition color setting) is invalid. Fig. 16 Display form2 Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 25 of 44 M35075-XXXFP Example of setting RAM character data For example : RAM character 0 Example of setting the RED bit code data Address (1)20016 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 DAF DAE DAD DAC DAB DAA DA9 DA8 (BS) (GS) (RS) (1) (2) (3) (4) DA7 DA6 DA5 DA4 DA3 (5) (6) (7) (8) (9) DA2 DA1 DA0 (10) (11) (12) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RED (Dot) (Dot) 1 2 3 4 5 6 7 8 9 101112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ....... Can not used 21F16 Example of setting the GREEN bit code data Address (1)20016 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 DAF DAE DAD DAC (BS) (GS) (RS) DAB DAA DA9 DA8 DA7 DA6 (1) (2) (3) (4) (5) (6) DA5 DA4 DA3 DA2 DA1 DA0 (7) (8) (9) (10) (11) (12) + GREEN (Dot) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R+G+B display image) (Dot) 1 2 3 4 5 6 7 8 9 101112 (Dot) 1 2 3 4 5 6 7 8 9 101112 (Dot) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ....... Can not used 21F16 Example of setting the GREEN bit code data Address (1)20016 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 DAF DAE DAD DAC (BS) (GS) (RS) DAB DAA DA9 DA8 DA7 (1) (2) (3) (4) (5) DA6 DA5 (6) (7) DA4 DA3 DA2 DA1 DA0 (8) (9) (10) (11) (12) + BLUE (Dot) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 101112 (Dot) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ....... Can not used 21F16 Note 1 : After clearing or setting all character RAM areas, and use the RAM characters. Note 2 : The RAM character's dots are set RED, GREEN and BLUE data, which are controlled by BS, GS and RS bit. (Can be set at same time) Fig.17 Setting of the data of RAM character Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 26 of 44 M35075-XXXFP CHARACTER FONT Images are composed on a 12 18 dot matrix, and characters can be linked vertically and horizontally with other characters to allow the display the continuous symbols. Character code FF16 is fixed as a blank without background. Therefore, cannot register a character font in this code. 12 dots 18 dots Note: Border When the character extends to the top line of the matrix, no border is left at the top. When the character extends to the bottom (18th) line of the matrix, no border is left at the bottom. Note: Hatching represents border. Fig.18 Example of border display Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 27 of 44 M35075-XXXFP DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by the I 2C-BUS serial input function. Example of data setting is shown in Figure 19 (at EXCK0 = "1", EXCK1 = "0" setting). Address/data DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 200 m sec hold Remarks System set up (Note 3) Address 12016 Data Data Data Data Data Data Data Data Data Data 12016 12116 12216 12316 12416 12516 12616 12716 12816 12916 0 0 0 0 0 0 0 0 0 0 0 0 0 ...... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DIV8 0 DIV7 0 DIV6 1 DIV5 0 DIV4 0 DIV3 0 DIV2 0 DIV1 0 DIV0 Address setting Frequency value setting Frequency range setting Output setting Horizontal display location setting Vertical display location setting DIV10 DIV9 RSEL1RSEL0 DIVS2 DIVS1 DIVS0 1 1 HP7 VP7 1 1 HP6 VP6 1 1 HP5 VP5 0 0 HP4 VP4 1 1 HP3 VP3 0 0 HP2 VP2 1 1 HP1 VP1 1 1 HP0 VP0 0 HP10 VP10 0 HP9 VP9 1 HP8 VP8 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display form setting Character size setting Character size setting Color, character size setting POLH POLV Display OFF Be stable/Waiting time Address setting 20 m sec hold Address 20016 Data 20016 0 0 FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000 ...... Bit color Bit code/RED RED*bit code setting Data Data 2F116 20016 Address 20016 0 0 0 ...... 0 0 0 0 0 1 Bit color 1 0 0 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 0 0 1 0 0 0 0 0 0 0 0 0 Address setting FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000 ...... Bit code/GREEN GREEN*bit code setting Data Data 2F116 20016 Address 20016 0 0 0 ...... 0 0 1 1 0 0 Bit color 0 0 0 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 0 0 1 0 0 0 0 0 0 0 0 0 Address setting FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000 ...... Bit code/BLUE BLUE*bit code setting Data Data 2F116 00016 0 0 0 ...... 1 0 0 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 Address00016 0 0 0 BB BG BR Background coloring 0 BLINK 0 B 0 G 0 R 0 0 C7 C6 0 0 0 0 0 0 C5 C4 C3 C2 C1 C0 Character code Address setting Blink -ing BLINK Character color ...... Character setting Data Data 11F16 12916 0 0 0 BB BG BR 0 0 0 0 0 0 B 0 1 G 0 0 R 1 0 C7 C6 0 0 0 1 C5 C4 C3 C2 C1 C0 1 1 0 1 POLH POLV Address 12916 0 0 0 0 0 0 1 0 Address setting Display ON (Note 2) Notes 1 : Input a continuous clock of constant period from the TCK pin. Also, input a horizontal synchronous signal into the HOR pin and a vertical synchronous signal into the VERT pin. 2 : Matrix-outline display in this data. ____ 3 : Secure the waiting time of 200ms after releasing AC, and set data from setting the display frequency (setting of the register). 4 : Set data to Display RAM and Display character RAM at internal clock (display clock) is stabilized. Fig. 19 Example of data setting Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 28 of 44 M35075-XXXFP Synchronous signal generator Horizontal synchronors signal (3V or 5V) Vertical synchronors signal (3V or 5V) +3V or +5V 1 2 1F -+ 3 4 5 Microcomputer 6 7 8 9 External clock 10 11 12 CPOUT VSS2 AC CS SCK/SCL SIN/SDA TCK P6 P7 VDD1 NC NC 100F +- 1F 0.01F NC VDD2 P5/B P4 P3/G P2 P1/R P0/BLNK0 BIN VSS1 VERT HOR 24 23 22 21 20 19 18 17 16 15 14 13 R BLNK0 G B M35075-XXXFP +3V or +5V 100F -+ 1F 0.01F Notes 1: CPOUT pin can be opened when use only EXCK1= "0" and EXCK= "0." 2: Connect CS pin to VDD at the time of I2C-Bus communication use. Fig.20 Example of the M35075-XXXFP peripheral circuit (Internal synchronous. At EXCK1 = "0", EXCK0 = "0") Horizontal synchronors signal (5V) Synchronous signal generator Vertical synchronors signal (5V) +5V 1 1.0k (note 1) 0.1F (note 2) 470PF (note 2) 1F -+ 2 3 4 5 Microcomputer 6 7 8 9 10 11 12 NC NC 100F +- 1F 0.01F Note : Connect CS pin to VDD at the time of I2C-Bus communication use. Note 1: Use this 1% precision element Note 2: Use this 10% precision element CPOUT VSS2 AC CS SCK/SCL SIN/SDA TCK P6 P7 VDD1 NC VDD2 P5/B P4 P3/G P2 P1/R P0/BLNK0 BIN VSS1 VERT HOR 24 23 22 21 20 19 18 17 16 15 14 13 R BLNK0 G B M35075-XXXFP +5V 100F -+ 1F 0.01F Fig.21 Example of the M35075-XXXFP peripheral circuit (External synchronous. At EXCK1 = "0", EXCK0 = "1") Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 29 of 44 M35075-XXXFP Synchronous signal generator Horizontal synchronors signal (5V) Vertical synchronors signal (5V) +5V 1 1.0k (note 1) 0.01F (note 2) 47PF (note 2) 1F -+ 2 3 4 5 Microcomputer 6 7 8 9 External clock 10 11 12 NC NC 100F +- 1F 0.01F Note : Connect CS pin to VDD at the time of I2C-Bus communication use. Note 1: Use this 1% precision element Note 2: Use this 10% precision element CPOUT VSS2 AC CS SCK/SCL SIN/SDA TCK P6 P7 VDD1 NC VDD2 P5/B P4 P3/G P2 P1/R P0/BLNK0 BIN VSS1 VERT HOR 24 23 22 21 20 19 18 17 16 15 14 13 R BLNK0 G B M35075-XXXFP +5V 100F -+ 1F 0.01F Fig.22 Example of the M35075-XXXFP peripheral circuit (External clock mode 2. At EXCK1 = "1", EXCK0 = "1") Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 30 of 44 M35075-XXXFP DATA INPUT 1 (1) The16-bit communication function (a)Serial data should be input with the LSB first. (b)The address consists of 16 bits. (c)The data consists of 16 bits. __ (d)The 16 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. Therefore, it is not necessary to in put the address from the second data. __ Note. Stop the input to SCK pin and fix it to "H" at CS pin "H" level. CS SCK SIN LSB Address(16 bits) MSB LSB Data(16 bits) N MSB LSB Data(16 bits) N+1 N = 1,2,3......... MSB Fig.23 Serial input timing Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 31 of 44 M35075-XXXFP (2)Timing requirements Data input Symbol tw(SCK) __ tsu(CS) __ th(CS) tsu(SIN) th(SIN) tword SCK width __ Parameter CS setup time __ CS hold time SIN setup time SIN hold time 1 word writing time Min. 200 200 2 200 200 10 Limits Typ. -- -- -- -- -- -- Max. -- -- -- -- -- -- Unit ns ns s ns ns s Remarks See Figure 24 tw(CS) 1s(min.) CS tsu(CS) tw(SCK) tw(SCK) th(CS) SCK tsu(SIN) th(SIN) SIN CS tword more than 2 s SCK 1 2 ... 12 13 14 15 16 1 ... 12 13 14 15 16 Fig. 24 Serial input timing requirements Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 32 of 44 M35075-XXXFP DATA INPUT 2 (1) I2C-Bus communication function This IC has a built-in data transmission interface which utilizes 2 unidirectional buses. In communications, this IC functions as a slave reception device. _____ Must connect CS pin to "H" at the time of I2C-Bus communication use. The IC is synchronized with the serial clock (SCL) sent from the master device and receives the data (SDA). Communications are controlled from the start/stop states. Also, always in put the control byte after attaining the start state. The below chart shows the start/stop state and control byte configuration. SCL SDA Start state Data receive Data modify enable Stop state Fig.25 Start state / Stop state Control byte: 7C16(Fixed) Slave address R/W 0 1 1 1 1 1 0 0 (0: Written) Fig.26 Control byte configuration Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 33 of 44 M35075-XXXFP (2) Data input (Sequence) (a) Addresses are consists of 16 bits. (b) Data is consists of 16 bits. (c) Addresses and data are communicated in 8-bit units. Input the lower 8 bits before the upper 8 bits. Make input from the MSB side. (d) After the start state has been attained and the control byte (7CH) received, the next 16 bits (2 bytes) are for inputting the address. Addresses are increased in increments for every 16 bits (2 bytes) of data input thereafter. As a result, it is not necessary to input the address from the second data. Note:During external synchronous , do not stop the external clock input from the TCK pin while inputting data. S T A R T SDA S Control byte (7 CH) Lower address (N) Upper address (N) Lower data (N) Upper data (N) lower data (N + 1) S T O P L S B A C K P M S B A* C K L S B A C K M S B L S B A C K M S B L S B A C K M S B L S B A C K M S B ACK* (Acknowledge) : Output the acknowledge signal whenever one byte input after the start state. Output the acknowledge signal and recieve the data thereafter when match the slave address (7CH). Fig.27 Data input sequence Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 34 of 44 M35075-XXXFP (2) Timing requirements Data input Limits Symbol fCLK tHIGH tLOW tR Parameter 0 4000 4700 - Typ. mode Min. Clock frequency HIGH period of Clock LOW period of Clock SDA & SCL rise time Max. 100 - - 1000 High-speed mode Min. 0 600 1300 20+(Note) 0.1CB 20+(Note) 0.1CB 600 600 0 100 600 1300 Max. 400 - - 300 KHz ns ns ns Unit Remarks tF tHD : STA tSU : STA tHD : DAT tSU : DAT tSU : STO tBUF SDA & SCL fall time Hold time at START status Set up time at START status Data input hold time Data input setup time Set up time at STOP state Bus release time - 4000 4700 0 250 4000 4700 300 - - - - - - 300 - - - - - - ns ns ns ns ns ns ns Time must be released bus before next transmission Only at START state repeating generation tSP Input filter / spike suppress (SDA & SCL pin) N/A N/A 0 50 ns Note. CB = total capacitance of 1 bus line. tF tHIGH tLOW tR SCL tsu : STA tHD : STA SDA tSP tHD : DAT tSU : DAT tSU : STO tBUF Fig.28 Data input timing Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 35 of 44 M35075-XXXFP ABSOLUTE MAXIMUM RATINGS (VDD = 5.00V, Ta = -20 to +85C, unless otherwise noted) Symbol VDD VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ta = +25 C Parameter Conditions With respect to VSS. Ratings -0.3 to +6.0 VSS -0.3 VI VDD +0.3 VSS VO VDD +300 -20 to +85 -40 to +125 Unit V V V mW C C RECOMMENDED OPERATING CONDITIONS Symbol VDD Supply voltage "H" level input voltage VIH "L" level input voltage VIL FOSC Oscillating frequency for display External clock mode 2 Internal clock mode H.sync Horizontal synchronous signal input frequeney Parameter 5V 3V __ __ (VDD = 5.00V, Ta = -20 to +85C, unless otherwise noted) Min. 4.75 2.50 0.8VDD 0.7VDD 0 0 VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V 6.3 6.3 20.0 20.0 15.0 15.0 Limits Typ. 5.0 3.0 VDD VDD 0 0 -- -- -- -- -- -- Max. 5.25 3.50 VDD VDD 0.2VDD 0.3VDD 80.0 40.0 110.0 110.0 130.0 60.0 Unit V V V V V V MHz MHz MHz MHz kHz kHz AC, CS, HOR, VERT SCK/SCL, SIN/SDA __ __ AC, CS, HOR, VERT SCK/SCL, SIN/SDA External clock mode 1 ELECTRICAL CHARACTERISTICS 1 Symbol VDD IDD VOH VOL Supply voltage Supply current Parameter (VDD = 5.00V, Ta = 25C, unless otherwise noted) Test conditions Ta = -20 to +85C VDD = 5.00V Min. 4.75 -- 3.5 Limits Typ. 5.0 40 -- Max. 5.25 60 -- Unit V mA V P0 to P7 (Note1) "H" level output voltage "L" level output voltage CPOUT P0 to P7 (Note2) CPOUT SIN/SDA __ __ VDD = 4.75V, IOH = -0.4mA VDD = 4.75V, IOH = -0.05mA VDD = 4.75V, IOL = 0.4mA VDD = 4.75V, IOL = 0.05mA VDD = 4.75V, IOL = 3.0mA VDD = 5.00V 4.75V VDD 5.25V -- 10 0.6VDD -- 30 -- 0.4 100 0.9VDD V k V RI VTCK Pull-up resistance AC, CS External clock input width Notes 1. The current from the IC must not exceed - 0.4 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.4 mA/port at any of port pins (P0 to P7). Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 36 of 44 M35075-XXXFP ELECTRICAL CHARACTERISTICS 2 VDD=3V (VDD = 3.00V, Ta = 25C, unless otherwise noted) Symbol VDD IDD VOH VOL RI VTCK Supply voltage Supply current "H" level output voltage P0 to P7 (Note1) Parameter Test conditions Ta = -20 to +85C VDD = 3.00V VDD = 2.70V, IOH = -0.1mA VDD = 2.70V, IOH = 0.1mA VDD = 3.00V 2.50V VDD 3.50V Min. 2.50 -- 2.30 -- 30 0.9VDD Limits Typ. 3.00 20 -- -- -- -- Max. 3.50 30 -- 0.4 150 VDD Unit V mA V V k V P0 to P7 (Note2) "L" level output voltage __ __ Pull-up resistance AC, CS External clock input width Notes 1. The current from the IC must not exceed - 0.1 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.1 mA/port at any of port pins (P0 to P7). Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 37 of 44 M35075-XXXFP NOTE FOR SUPPLYING POWER __ (1)Timing of power supplying to AC pin The internal circuit of M35075-XXXFP is reset when the level of __ the auto clear input pin AC is "L". This pin in hysteresis input with the pull-up resistor. __ The timing about power supplying of AC pin is shown in Figure 29. After supplying the power (VDD and VSS) to M35075-XXXFP and the supply voltage becomes more than 0.8 VDD, it needs __ to keep VIL time; tw of the AC pin for more than 1ms. __ Start inputting from microcomputer after AC pin supply voltage becomes more than 0.8 VDD and keeping 200ms wait time. (2)Timing of power supplying to VDD1 and VDD2. Supply power to VDD1 and VDD2 at the same time. Voltage [V] Data input disable VDD Supply voltage 0.8 x VDD VAC (AC pin input voltage) 0.2 x VDD tW more than 1ms __ Time t [s] tS Fig.29 Timing of power supplying to AC pin PRECAUTION FOR USE Notes on noise and latch-up In order to avoid noise and latch-up, connect a bypass capacitor (0.1F) directly between the VDD1 pin and VSS1 pin, and the VDD2 pin and VSS2 pin using a heavy wire. Note for waveform timing of the horizontal signals to the HOR pin Set horizontal synchronous signal edge* waveform timing to under 5ns and input to HOR pin. _ Set only the side which set by B/F register waveform timing under 5ns and input to HOR pin. _ *: Set front porch edge or back porch edge by B/F register. tf 90% Horizontal synchronous signal 10% DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M35075-XXXFP mask ROM order confirmation form (2) 24P2Q mark specification form (3) ROM data : EPROMs or floppy disks *In the case of EPROMs, thres sets of EPROMs are required per pattern. *In the case of floppy disks, 3.5-inch 2HD disk (1BM format) is required per pattern. tr Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 38 of 44 M35075-XXXFP STANDARD ROM TYPE : M35075-001FP M35075-001FP is a standard ROM type of M35075-XXXFP. The character patterns are fixed to the contents of Figure 30 to 33. Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 39 of 44 M35075-XXXFP 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Fig.30 M35075-001FP character patterns (1) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 40 of 44 M35075-XXXFP 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Fig.31 M35075-001FP character patterns (2) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 41 of 44 M35075-XXXFP 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C16 9D16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA16 AB16 AC16 AD16 AE16 AF16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA16 BB16 BC16 BD16 BE16 BF16 Fig.32 M35075-001FP character patterns (3) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 42 of 44 M35075-XXXFP C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16blank Fig.33 M35075-001FP character patterns (4) Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 43 of 44 M35075-XXXFP PACKAGE OUTLINE 24P2Q-A EIAJ Package Code SSOP24-P-300-0.80 24 MMP JEDEC Code - Weight(g) 0.2 13 Plastic 24pin 300mil SSOP Lead Material Cu Alloy e b2 HE E F Recommended Mount Pad Symbol 1 12 e1 A G D A2 e b A1 y c z Z1 Detail G Detail F A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 Dimension in Millimeters Min Nom Max 2.1 - - 0.2 0.1 0 - 1.8 - 0.45 0.35 0.3 0.25 0.2 0.18 10.2 10.1 10.0 5.4 5.3 5.2 - 0.8 - 8.1 7.8 7.5 0.8 0.6 0.4 - 1.25 - - 0.65 - - - 0.8 0.1 - - 0 - 8 - 0. 5 - - 7.62 - - 1.27 - L1 Rev.1.10 Feb 13, 2006 REJ03B0180-0110 page 44 of 44 L I2 REVISION HISTORY Rev. Date Page 1.00 Mar 01, 2002 1.10 Feb 13, 2006 P36 P37 First edition issued M35075-XXXFP Description Summary "RECOMMENDED OPERATING CONDITIONS" and "ELECTRICAL CHARACTERISTICS 1" are changed. "ELECTRICAL CHARACTERISTICS 2" is changed. A- 1 |
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