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LTC6603 Dual Adjustable Lowpass Filter FEATURES
n n n n n n n n n n n n
DESCRIPTION
The LTC(R)6603 is a dual, matched, programmable lowpass filter for communications receivers and transmitters. The selectivity of the LTC6603, combined with its linear phase, phase matching and dynamic range, make it suitable for filtering in many communications systems. With 1.5 phase matching between channels, the LTC6603 can be used in applications requiring pairs of matched filters, such as transceiver I and Q channels. Furthermore, the differential inputs and outputs provide a simple interface for most communications systems. The sampled data filter does not require an external clock yet its cutoff frequency can be set with a single external resistor with an accuracy of 3.5% or better. The external resistor programs an internal oscillator whose frequency is divided prior to being applied to the filter networks. This allows up to three cutoff frequencies that can be obtained for each external resistor value, allowing the cutoff frequency to be programmed over a range of more than six octaves. Alternatively, the cutoff frequency can be set with an external clock. The filter gain can also be programmed to 1, 2, 4 or 16. The LTC6603 features a low power shutdown mode that can be programmed through the serial interface and is available in a 24-pin 4mm x 4mm QFN package.
Guaranteed Phase and Gain Matching Specs Programmable BW Up to 2.5MHz Programmable Gain (0dB/6dB/12dB/24dB) 9th Order Linear Phase Response Differential, Rail-to-Rail Inputs and Outputs Low Noise: -145dBm/Hz (Input Referred) Low Distortion: -75dBc at 200kHz Simple Pin Programming or SPI Interface Set the Max Speed/Power with an External R Operates from 2.7V to 3.6V Input Range from 0V to 5.5V 4mm x 4mm QFN Package
APPLICATIONS
n
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Small/Low Cost Basestations: IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA, UMTS Low Cost Repeaters, Radio Links, and Modems 802.11x Receivers JTRS
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2.5MHz I and Q Lowpass Filter and Dual ADC
5V 3V 49.9 100nH* 0.1F 0.1F I OUTPUT V+IN IIN QIN 0.1F +INA -INA +INB -INB RBIAS VOCM 0.1F CAP GAIN1 GAIN0 GND GND BASEBAND GAIN CONTROL CLKCNTL SDO SDI LPFO LPF1
6603 TA01a
LTC2297
Phase Matching
180pF 10pF 14-BIT ADC 180pF 10pF 60 50 40 VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25C 1000 UNITS
V+A
V+D 49.9 100nH* +OUTA -OUTA +OUTB
LTC6603 -OUTB CLKIO
49.9 100nH* 180pF Q OUTPUT 10pF 14-BIT ADC 180pF 10pF VCM 2.2F
UNITS (%)
30 20 10 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 MISMATCH (DEG)
30.9k
SER 49.9 100nH* 3V
1.5
2
2.5
6603 TA01b
3V
*COILCRAFT 0603HP
6603f
1
LTC6603 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW GAIN0(D0) +OUTA 18 -OUTA 17 SER 25 16 V+D 15 CLKIO 14 GND 13 +OUTB 7 +INB 8 -INB 9 10 11 12 LPFO(SCLK) -OUTB SDO SDI GAIN1 +INA -INA
V+IN to GND ................................................................6V V+A , V+D to GND .........................................................4V V+A to V+D .............................................. -0.3V to +0.3V Filter Inputs to GND ....................... -0.3V to V+IN + 0.3V Pins 3, 4 to GND ............................. -0.3V to V+A + 0.3V Pins 5, 6, 9-11, 15, 17, 21, 22 to GND ................. -0.3V to V+D + 0.3V Maximum Input Current .......................................10mA Output Short Circuit Duration........................... Indefinite Operating Temperature Range (Note 2) LTC6603CUF .......................................-40C TO 85C LTC6603IUF ........................................-40C TO 85C Specified Temperature Range (Note 3) LTC6603CUF ...........................................0C TO 70C LTC6603IUF ........................................-40C TO 85C Storage Temperature Range................... -65C to 150C
24 23 22 21 20 19 V+IN 1 V+A 2 VOCM 3 RBIAS 4 CLKCNTL 5 LPF1(CS) 6
UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN
TJMAX = 150C, JA = 37C/W, JC = 4.3C/W EXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB.
ORDER INFORMATION
LEAD FREE FINISH LTC6603CUF#PBF LTC6603IUF#PBF TAPE AND REEL LTC6603CUF#TRPBF LTC6603IUF#TRPBF PART MARKING* 6603 6603 PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE 24-Lead (4mm x 4mm) Plastic QFN 0C to 70C 24-Lead (4mm x 4mm) Plastic QFN -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER Filter Gain Either Channel CONDITIONS External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 * fC), Relative to DC Gain fIN = 125kHz (0.8 * fC), Relative to DC Gain fIN = 156.25kHz (fC), Relative to DC Gain fIN = 234.375kHz (1.5 * fC), Relative to DC Gain External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
l l l l l l l l l
0.25 -0.5 0.4 -0.6
CAP
0.4 -0.3 0.6 -0.4 -32 0.03 0.03 0.03 0.03
0.55 -0.1 0.8 -0.2 -29.5 0.1 0.1 0.1 0.15
dB dB dB dB dB dB dB dB dB
Matching of Filter Gain
6603f
2
LTC6603 ELECTRICAL CHARACTERISTICS
PARAMETER Filter Phase Either Channel CONDITIONS External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 * fC) fIN = 125kHz (0.8 * fC) fIN = 156.25kHz (fC) External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 1MHz (0.4 * fC), Relative to DC Gain fIN = 2MHz (0.8 * fC), Relative to DC Gain fIN = 2.5MHz (fC), Relative to DC Gain fIN = 4MHz (1.5 * fC), Relative to DC Gain External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC) External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 * fC) fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC) External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 * fC) fIN = 2MHz (0.8 * fC) fIN = 2.5MHz (fC)
l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
MIN 158 -44 -152 TYP 161 -39 -146 0.2 0.4 0.5 0 -2 -0.7 -1.1 0.5 -0.8 0.4 0.1 -43 0.05 0.2 150 -45 -152 155 -39 -141 MAX 163 -36 -142 1.5 3 4 1.2 -0.1 1.5 1 -32.6 0.2 0.4 159 -28 -126 2.5 4 4 3 3 3.5 0 5.6 11.2 22.5 0.5 6 11.8 23.2 0.1 0.05 0.05 0.1 -124 -129 -135 -145 -53 -59 -65 -76 -75 1.6 5 1.2 6.6 12.5 24 0.2 0.1 0.15 0.2 UNITS deg deg deg deg deg deg dB dB dB dB dB dB dB deg deg deg deg deg deg % % % dB dB dB dB dB dB dB dB dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm dBm dBm dBm dB k k
6603f
Matching of Filter Phase
Filter Gain Either Channel
Matching of Filter Gain Filter Phase Either Channel
Matching of Filter Phase
Filter Cutoff Accuracy CLKCNTL = 3V (Note 4) when Self Clocked RBIAS = 200k RBIAS = 54.9k RBIAS = 30.9k DC Gain Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB Voltage Noise Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB Noise Bandwidth = 5MHz, Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB VIN = 2VP-P, fIN = 200kHz, Gain Setting = 24dB Gain = 24dB, RBIAS = 30.9k, Filter Cutoff (fC) = 2.5MHz Differential Common Mode
DC Gain Matching
Noise At 200kHz
Integrated Noise
THD Input Impedance
3
LTC6603 ELECTRICAL CHARACTERISTICS
PARAMETER VOS Differential CONDITIONS Input Referred Differential Offset Voltage at Either Output Lowest Cutoff Frequency, Gain Setting = 24dB Highest Cutoff Frequency, Gain Setting = 24dB Lowest Cutoff Frequency, Gain Setting = 0dB Highest Cutoff Frequency, Gain Setting = 0dB fC = 625kHz Common Mode Input from 0 to 3V, V+IN = 3V Common Mode Input from 0 to 5V, V+IN = 5V V+A = V+D = 3V, Pin 3 Open V+A = V+D = 3V, Pin 3 Open Common Mode Offset Voltage, VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM - VOCM Source 1mA, Relative to V+A Sink 1mA, Relative to GND Sourcing Sinking Internal Clock (RBIAS = 30.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V fC = 156.25kHz fC = 625kHz fC = 2.5MHz Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface V+D, V+A Relative to GND V+IN Relative to GND V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3V, V+IN from 4.5V to 5.5V
l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
MIN TYP MAX 8 14 40 60 60 60 1.3 2.5 90 90 1.45 3.4 100 200 150 7 11 25 30 1.5 4.5 185 500 400 UNITS mV mV mV mV dB dB V k mV mV mV mA mA
CMRR Differential
VOCM Pin Voltage VOCM Pin Input Impedance VOSCM Output Swing Short-Circuit Current Supply Current
l l l l l l l l l l
88 121 162 170 2.7 2.7 40 65 30.9 54.9 1.17 40 50 85
96 130 175 235 3.6 5.5
mA mA mA A V V dB dB
Supply Current, Shutdown Mode Supply Voltage PSRR
RBIAS Resistor Range CLKCNTL = 3V Clock Frequency Error < 3.5% Clock Frequency Error < 3% RBIAS Pin Voltage 30.9k < RBIAS < 200k Clock Frequency Drift RBIAS = 30.9k CLKCNTL Pin Open Over Temperature Clock Frequency Drift V+A, V+D from 2.7V to 3.6V, RBIAS = 30.9k CLKCNTL Pin Open Over Supply Output Clock Duty Cycle RBIAS = 30.9k
54.9 200
k k V ppm/C
l l l l
0.2 45 V+D - 0.3 50
0.5 55
%/V % V
CLKIO Pin High Level CLKCNTL = 0V (Note 5) Input Voltage CLKIO Pin Low Level Input Voltage CLKIO Pin Input Current CLKCNTL = 0V (Note 5) CLKCNTL = 0V CLKIO = 0V (Note 6) CLKIO = V+D
0.3
V
l l
-1 10 2.95 2.9
A A V V
CLKIO Pin High Level V+A = V+D = 3V, CLKCNTL = 3V Output Voltage IOH = -1mA IOH = -4mA
6603f
4
LTC6603 ELECTRICAL CHARACTERISTICS
PARAMETER CLKIO Pin Low Level Output Voltage CLKIO Pin Rise Time CLKIO Pin Fall Time SER High Level Input Voltage SER Low Level Input Voltage SER Input Current CLKCNTL High Level Input Voltage CLKCNTL Low Level Input Voltage CLKCNTL Input Current CONDITIONS V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF Pin 17 Pin 17 Pin 17 = 0V (Note 6) Pin 17 = V+D Pin 5 Pin 5 CLKCNTL = 0V (Note 6) CLKCNTL = V+D
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
MIN TYP 0.05 0.1 0.3 0.3 V+D - 0.3 0.3 -10 2 V+D - 0.5 0.5 -25 -15 15 MAX UNITS V V ns ns V V A A V V A A
25
Pin Programmable Control Mode Specifications. Specifications apply to pins 6, 9, 21 and 22 in pin programmable control mode.
SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN Digital Input High Voltage Digital Input Low Voltage Digital Input Current Pins 6, 9, 21, 22 Pins 6, 9, 21, 22 Pins 6, 9, 21, 22 (Note 6)
l l l
PARAMETER
CONDITIONS
MIN 2
TYP
MAX
UNITS V
0.8 -1 1
V A
Serial Port DC and Timing Specifications. Specifications apply to pins 6, 9-11, and 21 in serial programming mode.
SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN VOH VOL t1 (Note 5) t2 (Note 5) t3 t4 t5 t6 (Note 5) t7 (Note 5) t8 t9 (Note 5) Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Output High Voltage Digital Output Low Voltage SDI Valid to SCLK Setup SDI Valid to SCLK Hold SCLK Low SCLK High CS Pulse Width LSB SCLK to CS CS Low to SCLK SDO Output Delay SCLK Low to CS Low CL = 15pF Pins 6, 9, 10 Pins 6, 9, 10 Pins 6, 9, 10 (Note 6) Pins 11, 21 Sourcing 500A Pins 11, 21 Sinking 500A
l l l l l l l l l l l l l l
PARAMETER
CONDITIONS
MIN 2
TYP
MAX
UNITS V
0.8 -1 VSUPPLY - 0.3 0.3 60 0 100 100 60 60 30 125 0 1
V A V V ns ns ns ns ns ns ns ns ns
6603f
5
LTC6603 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6603C and LTC6603I are guaranteed functional over the operating temperature range of -40C to 85C. Note 3: LTC6603C is guaranteed to meet specified performance from 0C to 70C. The LTC6603C is designed, characterized and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. The LTC6603I is guaranteed to meet the specified performance limits from -40C to 85C. Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator cause variations in the filter cutoff frequency. See the "Applications Information" section. Note 5: Guaranteed by design, not subject to test. Note 6: To conform to the logic IC standard, current out of a pin is arbitrarily given a negative value.
TYPICAL PERFORMANCE CHARACTERISTICS
DC Gain Matching
70 70 VS = 3V, BW = 2.5MHz GAIN SETTING = 0dB, TA = 25C 60 1000 UNITS 50 UNITS (%) UNITS (%) 40 30 20 10 0 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 MISMATCH (dB)
6603 G01
DC Gain Matching
VS = 3V, BW = 156.25kHz GAIN SETTING = 0dB, TA = 25C 60 1000 UNITS 50 40 30 20 10 0 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 MISMATCH (dB)
6603 G02
Phase Matching
30 25 20 UNITS (%) 15 10 5 0 -2.5 -2-1.5-1-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 MISMATCH (DEG)
6603 G03
VS = 3V, BW = 2.5MHz f = 2MHz, TA = 25C 1000 UNITS
Phase Matching
60 50 40 UNITS (%) GAIN (dB) 35 30 20 10 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 MISMATCH (DEG) VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25C 1000 UNITS 30 20 10 0 -10 -20 -30 -40 -50
Gain and Group Delay vs Frequency
800 GAIN = 24dB 760 720 GAIN = 0dB GAIN = 12dB GAIN = 6dB GROUP DELAY 680 640 600 560 520 480 440 400 10M
6603 G05
GROUP DELAY (ns)
1.5
2
2.5
RBIAS = 30.9k, VS = 3V -60 LPF1 = 1, BW = 2.5MHz TA = 25C -70 10k 100k 1M FREQUENCY (Hz)
6603 G04
6603f
6
LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Group Delay vs Frequency
30 20 10 0 GAIN (dB) -10 -20 -30 GROUP DELAY -40 RBIAS = 30.9k, VS = 3V -50 LPF1 = 0, LPF0 = 1, -60 BW = 625kHz TA = 25C -70 10k 100k 1M FREQUENCY (Hz) GAIN = 0dB GAIN = 24dB GAIN = 12dB GAIN = 6dB 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 10M
6603 G06
Gain and Group Delay vs Frequency
30 20 10 0 GAIN (dB) -10 -20 -30 -40 RBIAS = 30.9k, VS = 3V -50 LPF1 = LPF0 = 0, -60 BW = 156.25kHz TA = 25C -70 1k 10k 100k FREQUENCY (Hz) GROUP DELAY (ns) GAIN = 12dB GAIN = 6dB GAIN = 0dB GROUP DELAY GAIN = 24dB 12.0 11.5 11.0 DISTORTION (dBc) 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 1M
6603 G07
Distortion vs Input Frequency
-50 RBIAS = 30.9k, VS = 3V LPF1 = 1, BW = 2.5MHz VOUT = 2VP-P, TA = 25C -60 HD3, GAIN = 24dB HD3, GAIN = 0dB -70 HD2, GAIN = 0dB -80 HD2, GAIN = 24dB GROUP DELAY (s)
-90 100
500 900 1300 1700 INPUT FREQUENCY (kHz)
6603 G08
Distortion vs Input Frequency
-60 -65 DISTORTION (dBc) -70 -75 -80 -85 -90 100 RBIAS = 54.9k, VS = 3V LPF1 = 1, BW = 1.41MHz TA = 25C DISTORTION (dBc) HD3, GAIN = 0dB -60
Distortion vs Input Frequency
-70 RBIAS = 30.9k, VS = 3V LPF1 = 0, LPF0 = 1, BW = 625kHz -65 VOUT = 2VP-P, TA = 25C HD3, GAIN = 0dB DISTORTION (dBc) -70 -75 -80 -85 -90 HD2, GAIN = 24dB HD2, GAIN = 0dB 20 120 220 420 320 INPUT FREQUENCY (kHz) 520
6603 G10
Distortion vs Input Frequency
HD3, GAIN = 0dB -75 -80 HD2, GAIN = 24dB -85 HD2, GAIN = 0dB -90 HD3, GAIN = 24dB
HD3, GAIN = 24dB
HD2, GAIN = 0dB HD2, GAIN = 24dB HD3, GAIN = 24dB 300 700 500 900 INPUT FREQUENCY (kHz) 1100
6603 G09
-95 RBIAS = 30.9k, VS = 3V LPF1 = LPF0 = 0, BW = 156.25kHz VOUT = 2VP-P, TA = 25C -100 50 90 110 130 10 30 70 INPUT FREQUENCY (kHz)
150
6603 G11
Distortion vs Output Voltage
FILTER CUTOFF FREQUENCY DEVIATION (%) -60 RBIAS = 30.9k, VS = 3V, LPF1 = 0, LPF0 = 1, BW = 2.5MHz, GAIN = 24dB, TA = 25C HD3, f = 1MHz 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7
Filter Cutoff Accuracy vs Supply Voltage
FILTER CUTOFF FREQUENCY DEVIATION (%) LPF1 = LPF0 = 0, BW = 156.25kHz 1.0
Filter Cutoff Accuracy vs Temperature
VS = 3V 0.8 RBIAS = 30.9k 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -50 -30 BW = 2.5MHz BW = 156.25kHz BW = 625kHz
-70 DISTORTION (dBc)
LPF1 = 0, LPF0 = 1, BW = 625kHz
HD2, f = 1MHz -80
LPF1 = 1, BW = 2.5MHz
-90
HD3, f = 200kHz HD2, f = 200kHz
-100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT VOLTAGE (VP-P)
6603 G11
-0.8 RBIAS = 30.9k TA = 25C -0.9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
6603 G13
-10 10 30 50 TEMPERATURE (C)
70
90
6603 G14
6603f
7
LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS
Common Mode Rejection Ratio
100 90 80 CMRR (dB) CMRR (dB) 70 60 50 40 VS = 3V, RBIAS = 30.9k 30 LPF1 = 1, BW = 2.5MHz TA = 25C 20 10k 100k 1M FREQUENCY (Hz) GAIN = 12dB GAIN = 24dB GAIN = 0dB GAIN = 6dB 110 100 90 80 GAIN = 6dB 70 60 50 40 30 10M
6603 G15
Common Mode Rejection Ratio
VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz, TA = 25C GAIN = 24dB GAIN = 0dB GAIN = 12dB CMRR (dB) 120 110 100 90 80 70 60 50
Common Mode Rejection Ratio
GAIN = 24dB GAIN = 12dB
GAIN = 0dB GAIN = 6dB
20 10k
100k 1M FREQUENCY (Hz)
10M
6603 G16
VS = 3V, RBIAS = 30.9k 40 LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25C 30 1k 10k 100k FREQUENCY (Hz)
1M
6603 G17
Common Mode Rejection
100 COMMON MODE REJECTION (dB) 90 80 GAIN = 6dB 70 GAIN = 12dB 60 GAIN = 24dB 50 40 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz, TA = 25C 30 10k 100k 1M FREQUENCY (Hz) CMR = VIN-CM/VOUT-DIFF COMMON MODE REJECTION (dB) GAIN = 0dB 110 100 90 80 70 60
Common Mode Rejection
100 COMMON MODE REJECTION (dB) VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF1 = 1, BW = 625kHz, TA = 25C GAIN = 0dB GAIN = 6dB
Common Mode Rejection
GAIN = 12dB 90
80 GAIN = 24dB GAIN = 0dB 70 GAIN = 6dB CMR = VIN-CM/VOUT-DIFF VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25C 1k 10k 100k FREQUENCY (Hz) 1M
6603 G20
GAIN = 12dB GAIN = 24dB
60
10M
6603 G18
CMR = VIN-CM/VOUT-DIFF 50 10k 100k 1M FREQUENCY (Hz)
50 10M
6603 G19
OIP3 vs Average Signal Frequency
41 GAIN = 6dB 40 GAIN = 12dB 39 OIP3 (dBm) OIP3 (dBm) 38 37 36 GAIN = 0dB 42 GAIN = 24dB 44 46
OIP3 vs Average Signal Frequency
43 GAIN = 12dB 42 GAIN = 0dB 41 GAIN = 6dB GAIN = 24dB OIP3 (dBm) 40 39 38 37 36 35
OIP3 vs Average Signal Frequency
GAIN = 0dB
GAIN = 12dB GAIN = 6dB GAIN = 24dB
40
VS = 3V, RBIAS = 30.9k, TA = 25C 35 LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 34 100 500 900 1300 1700 2100 2500 AVERAGE FREQUENCY OF TWO TONES (kHz)
6603 G21
38 VS = 3V, RBIAS = 30.9k, TA = 25C LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 36 0 100 200 300 400 500 600 AVERAGE FREQUENCY OF TWO TONES (kHz)
6603 G22
VS = 3V, RBIAS = 30.9k, TA = 25C LPF1 = 0, LPF0 = 1, BW = 156.25kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz 20 40 60 80 100 120 140 160 AVERAGE FREQUENCY OF TWO TONES (kHz)
6603 G23
6603f
8
LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS
OIP3 vs Temperature
42 41 40 OIP3 (dBm) 39 BW = 625kHz, FREQUENCY = 200kHz 38 BW = 156.25kHz, FREQUENCY = 60kHz 37 36 BW = 2.5MHz, FREQUENCY = 1MHz 0.001 -30 -10 10 30 50 TEMPERATURE (C) 70 90
6603 G23
Output Impedance vs Frequency
10 VS = 3V, RBIAS = 30.9k, TA = 25C LPF1 = 0, LPF0 = 1, BW = 625kHz LPF1 = LPF0 = 0, BW = 156.25kHz 0.1 200 180 SUPPLY CURRENT (mA) 160 140
Supply Current vs Supply Voltage
TA = 25C RBIAS = 30.9k BW = 2.5MHz
OUTPUT IMPEDANCE ()
VS = 3V, RBIAS = 30.9k PASSBAND GAIN = 24dB VOUT = 6dBm PER TONE FOR 2-TONE TEST f = 10kHz
1
BW = 625kHz 120 100 80 60 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
6603 G26
0.01
LPF1 = 1, BW = 2.5MHz
BW = 156.25kHz
35 -50
1k
10k
100k 1M FREQUENCY (Hz)
10M
6603 G25
Supply Current vs Temperature
180 160 SUPPLY CURRENT (mA) 140 VOLTAGE (V) 120 100 80 60 -50 BW = 156.25kHz TA = 25C RBIAS = 30.9k BW = 2.5MHz 5 4 3 2 1 0 -1
Clock Output Operating at 80MHz
RBIAS = 30.9k, VS = 3V TA = 25C RBIAS PIN VOLTAGE (V) 1.25
RBIAS Pin Voltage vs IRBIAS
TA = 25C VS = 3V
1.20
BW = 625kHz
1.15
-30
-10 10 30 50 TEMPERATURE (C)
70
90
-2 -14 -12 -10
1.10 -8 -6 -4 TIME (ns) -2 0 2
0
5
10 15 IRBIAS (A)
20
25
6603 G29
6603 G27
6603 G28
Input Referred Noise Density
1000 VOLTAGE NOISE DENSITY (nV/Hz) GAIN = 0dB GAIN = 6dB GAIN = 12dB 10 GAIN = 24dB VOLTAGE NOISE DENSITY (nV/Hz) 1000
Input Referred Noise Density
1000 VOLTAGE NOISE DENSITY (nV/Hz)
Input Referred Noise Density
GAIN = 0dB GAIN = 6dB 100 GAIN = 12dB GAIN = 24dB
100
GAIN = 0dB 100 GAIN = 6dB GAIN = 12dB GAIN = 24dB 10 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25C 100k 1M FREQUENCY (Hz) 10M
6603 G31
10 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 0, BW = 156.25kHz TA = 25C 1k 10k 100k FREQUENCY (Hz) 1M
6603 G32
1 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz TA = 25C 100k 1M FREQUENCY (Hz) 10M
6603 G30
0.1 10k
1 10k
1
6603f
9
LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Input Referred Noise
1000 VS = 3V, RBIAS = 30.9k LPF1 = 1,BW = 2.5MHz TA = 25C VOLTAGE NOISE (V) GAIN = 6dB GAIN = 0dB 1000
Integral Input Referred Noise
VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25C GAIN = 0dB VOLTAGE NOISE (V) GAIN = 6dB GAIN = 12dB 1000
Integral Input Referred Noise
VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz TA = 25C GAIN = 0dB GAIN = 6dB GAIN = 12dB GAIN = 24dB 10
VOLTAGE NOISE (V)
100
100
100
GAIN = 24dB 10
10 GAIN = 12dB GAIN = 24dB 1 10k 100k 1M INTEGRATION BW (Hz) 10M
6603 G33
1 10k
100k 1M INTEGRATION BW (Hz)
10M
6603 G34
1 10k
100k INTEGRATION BW (Hz)
1M
6603 G35
PIN FUNCTIONS
V+IN (Pin 1): Input Voltage Supply (2.7V V 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output common mode voltage reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 1F capacitor to ground. This pin has a typical input impedance of 3.4k and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6603 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 30.9k and 200k and limit the capacitance on this pin to less than 10pF This resistor is . necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6603 attempts to pull the pin toward mid-supply. This is realized with two internal 15A current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15A. Likewise, driving the CLKCNTL pin low requires sinking 15A. When the CLKCNTL pin is floated, it should be bypassed by a 1nF capacitor to ground or be surrounded by a ground shield to prevent excessive coupling from other PCB traces.
6603f
10
LTC6603 PIN FUNCTIONS
LPF1(CS) (Pin 6): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, -INB (Pins 7, 8): Channel B differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0(SCLK) (Pin 9): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. SDI (Pin 10): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data input. SDO (Pin 11): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data output. -OUTB, +OUTB (Pins 12, 13): Channel B differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Should be tied to a ground plane for best performance. CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads (heavier loads will cause inaccuracies). V+D (Pin 16): Digital Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16) or floated, the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, LPF1 and LPF0 pins. When SER is tied to ground, the filter gain, the filter cutoff frequency and shutdown mode are programmed by the serial interface. -OUTA, +OUTA (Pins 18, 19): Channel A differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). CAP (Pin 20): Connect a 0.1F bypass capacitor to this pin. Pin 20 is a buffered version of Pin 3. GAIN0(D0) (Pin 21): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. GAIN1 (Pin 22): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. -INA, +INA (Pins 23, 24): Channel A differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB.
6603f
11
LTC6603 BLOCK DIAGRAM
+INA 24 -INA 23 GAIN1 22 GAIN0(D0) 21 CAP 20 +OUTA 19
V+IN 1
CHANNEL A
18 -OUTA
GAIN V+A 2 CONTROL V+A BIAS
LPF 17 SER CLK
VOCM 3
TO PIN 20 16 V+D
GND RBIAS 4
BIAS/OSC
CONTROL LOGIC
CLOCK GENERATOR 15 CLKIO
BIAS CLKCNTL 5
CONTROL
CLK 14 GND
GAIN
LPF
LPF1(CS) 6
CHANNEL B
13 +OUTB
7 +INB
8 -INB
9 LPF0(SCLK)
10 SDI
11 SDO
12 -OUTB
6603 BD
TIMING DIAGRAM
t1 t2 SCLK
Timing Diagram of the Serial Interface
t4 t3 t6 t7
t9
SDI
D3
D2
D1
D0
D7 * * * * D4
D3
t5 CS t8 D4 PREVIOUS BYTE D3 D2 D1 D0 D7 * * * * D4 CURRENT BYTE D3
6603 TD
SDO
6603f
12
LTC6603 APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram) The LTC6603 features two matched filter channels, each containing gain control and lowpass filter networks that are controlled by a single control block and clocked by a single clock generator. The gain and cutoff frequency can be separately programmed. The two channels are not independent, i.e. if the gain is set to 24dB then both channels have a gain of 24dB. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidth. This allows the filters to be "tuned" to many different bandwidths. Pin Programmable Interface As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, LPF1 and LPF0. The GAIN0(D0) pin is bidirectional (input in pin programmable control mode, output in serial mode). In pin programmable control mode, the voltage at GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the parasitic diodes (see Figure 2). Connecting a 10k resistor at the GAIN0(D0) pin (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal
3.3V LTC6603 V+IN V+A V+D
pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down. Serial Interface Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift-register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock's falling edge. A high CS will load the 8 bits of the shift-register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be "wire-or'ed" to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. An LTC6603 may be daisy chained with other LTC6603s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6603s in a daisy chained SPI configuration.
3.3V LTC6603 V+IN V+A V+D
0.1F
0.1F
+ -
VIN
+INA -INA SER LPF1(CS) LPF0(SCLK)
+OUTA -OUTA
+
VOUT
+ -
LPF1 LPF0 P VIN
+INA -INA SER LPF1(CS) LPF0(SCLK)
+OUTA -OUTA
+
VOUT
-
-
GAIN1 GAIN0(D0) GND
GAIN1 GAIN0 10k
GAIN1 GAIN0(D0) GND
LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz) GAIN = 4
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON GAIN0(OUT) PROTECTS THE DEVICE WHEN VGAIN0 > V+D
6603 F01
Figure 1. Filter in Pin Programmable Control Mode
6603f
13
LTC6603 APPLICATIONS INFORMATION
SHUTDOWN V+D OUT NO 4-BIT GAIN, BW FUNCTION CONTROL CODE
CS
8-BIT LATCH
GAIN0(D0)
SDI
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER
(INTERNAL NODE)
6603 F02
SCLK
SDO
6603 F03
Figure 2. Bidirectional Design of GAIN0(OUT) Pin
Figure 3. Diagram of Serial Interface (MSB First Out)
3.3V LTC6603 #1
3.3V LTC6603 #2
0.1F
V+IN V+A V+D
0.1F
V+IN V+A V+D
+
VIN1
+INA -INA SER
+OUTA -OUTA
+ -
VOUT1
+
VIN2
+INA -INA SER LPF1(CS)
+OUTA -OUTA
+ -
VOUT2
-
-
CSX P SCLK SDI
LPF1(CS) LPF0(SCLK) SDI GND GAIN0(D0) SDO OUT1
LPF0(SCLK) SDI GND
GAIN0(D0) SDO
OUT2 SDO
SCLK
SDI
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 CS
GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1
6603 F04
Figure 4. Two Devices in a Daisy Chain Serial Control Register Definition
D7 GAIN0 D6 GAIN1 D5 LPF0 D4 LPF1 D3 D2 D1 SHDN D0 OUT
6603f
NO FUNCTION NO FUNCTION
14
LTC6603 APPLICATIONS INFORMATION
GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to "1" to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode.
Table 1. Gain Control
GAIN 1 0 0 1 1 GAIN 0 0 1 0 1 PASSBAND GAIN (dB) 0 6 12 24
Self-Clocking Operation The LTC6603 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): fCLK = 247.2MHz * 10k/RBIAS Note: RBIAS 200k The design is optimized for V+A, V+D = 3V, fCLK = 45MHz, where the filter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used (any resistor (RBIAS) tolerance, will shift the clock frequency). With different resistor values and cutoff frequency control settings (LPF1 and LPF0), the lowpass cutoff frequency can
200 175 150 RBIAS (k) 125 100 75 50 25
be accurately varied from 24.14kHz to 2.5MHz. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 30.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if LPF1 and LPF0 are both equal to zero, and RBIAS is increased from 30.9k to 200k, fCLK will decrease from 80MHz to 12.36MHz and the cutoff frequency will be reduced from 156.25kHz to 24.14kHz. The cutoff frequencies that can be obtained with external resistor values of 54.9k and 200k are shown in Table 3 and Table 4, respectively. When the LTC6603 is programmed for the cutoff frequencies lower than the maximum, the power is automatically reduced. The power savings at the middle bandwidth setting (LPF1 = `0', LPF0 = `1'), is about 23%, while the power savings at the lowest bandwidth setting (LPF1 = `0', LPF0 = `0') is about 60%.
Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHz
LPF1 0 0 1 1 LPF0 0 1 0 1 LOWPASS BW(kHz) 156.25 625 2500 2500
Table 3. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 45MHz
LPF1 0 0 1 1 LPF0 0 1 0 1 LOWPASS BW(kHz) 87.94 351.78 1407 1407
Table 4. Cutoff Frequency Control, RBIAS = 200k, fCLK = 12.36MHz
LPF1 0 0 1 1 LPF0 0 1 0 1 LOWPASS BW(kHz) 24.14 96.56 386.25 386.25
10
20 30 40 50 60 70 DESIRED CLOCK FREQUENCY (MHz)
80
6603 F05
Figure 5. RBIAS vs Desired Clock Frequency
6603f
15
LTC6603 APPLICATIONS INFORMATION
The following graphs show a few of the possible lowpass filters.
Gain and Group Delay vs Frequency (2.5MHz Lowpass Response)
0 -20 GAIN (dB) -40 -60 GROUP DELAY -80 -100 -120 100k 0.4 0.2 0 1.2 GAIN 1.0 GROUP DELAY (s) 0.8 0.6
Alternative Methods of Setting the Clock Frequency of the LTC6603 The oscillator may be programmed by any method that sinks a current out of the RBIAS pin. The circuit in Figure 6 sets the clock frequency by using a programmable current source and in the expression for fCLK, the resistor RBIAS is replaced by the ratio of 1.17V/ICONTROL. Because the voltage of the RBIAS pin is approximately 1.17V 5%, the Figure 6 circuit is less accurate than if a resistor controls the clock frequency. In this circuit, the LTC2621 (a 12-bit DAC) is daisy chained with the LTC6603. Because the sinking current from the RBIAS pin is 2N * R1 the equivalent RBIAS is 2N * R1 k, VRBIAS * k
1M FREQUENCY (Hz)
10M
6603 G17
Gain and Group Delay vs Frequency (650kHz Lowpass Response)
0 GAIN GROUP DELAY (s) -20 GAIN (dB) 3 4
where k is the binary DAC input code and N is the resolution. Figure 7 shows some of the frequency responses that can be obtained using this circuit. Figure 8 shows the LTC6603's oscillator configured as a VCO. A voltage source is connected in series with the RBIAS resistor. The clock frequency, fCLK, will vary with VCONTROL. Again, this circuit decouples the relationship between the current out of the RBIAS pin and the voltage of the RBIAS pin; the frequency accuracy will be degraded. The clock frequency, however, will increase monotonically with decreasing VCONTROL. Operation Using an External Clock The LTC6603 may be clocked by an external oscillator for tighter bandwidth control by pulling CLKCNTL (Pin 5) to ground and driving a clock into CLKIO (Pin 15). If an external clock is used, the RBIAS resistor is still necessary. The value of RBIAS must be no larger than the value that would be required for using the internal oscillator. For example, a 100k resistor would program the internal oscillator for 24.705MHz, so an external oscillator frequency of 24.705MHz would require an RBIAS resistance of no more
6603f
-40
GROUP DELAY
2
-60
1
-80 100k
1M FREQUENCY (Hz)
6603 G18
0
The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 0.1F ceramic capacitor between V+A (Pin 2) and ground, as close as possible to the IC to minimize inductance. The PCB layout should also include an additional 0.1F ceramic capacitor between V+D (Pin 16) and ground. Avoid parasitic capacitance on RBIAS (Pin 4) and avoid routing noisy signals near RBIAS. Use a ground plane connected to Pin 14 and the Exposed Pad (Pin 25).
16
LTC6603 APPLICATIONS INFORMATION
-INB 5V I RANGE = 6A TO 38.4A C7 100nF LTC6078 2 3 -IN +IN V+ OUT V- 1 2 Q1 RK7002AT116CT VOCM 1 2 3 4 5 6 7 8 9 10 11 12 V+IN +INA V+A -INA VOCM GAIN1 RBIAS GAIN0(D0) CLKCNTL VOCM CAP LPF1(CS) +OUTA +INB LTC6603 -OUTA -INB SER LPF0(SCLK) V+D CLK IO SDI GND SDO +OUTB -OUTB
6603 F06
+INB
5V V+IN V+
3V
+INA
-INA
USE NARROW SHORT TRACES FOR MINIMUM CAPACITANCE.
R23 50k
R24 50k
C1 100nF
C2 2.2F
C3 2.2F
C4 100nF
R25 50k
R26 50k
R1 30.5k 5V LTC6078 V+ 7 -IN OUT +IN V- 5V R4 100k C8 100nF C16 50pF C17 50pF
24 23 22 21 20 19 18 17 16 15 14 13
C18 50pF
C19 50pF +OUTA -OUTA
C15 10nF +OUTB -OUTB
SPI INTERFACE VREF VCC 7 VOUT SDO SDI SCK LTC2621-1 CLR CS/LD GND LDAC 1 2 3 4 5 10 SDI SCLK CS 5V C9 1F CLR LOW WILL SET DAC TO MID-SCALE (WITH A -1 VERSION). HAS ~100ms TC AT START-UP TO RESET TO ZERO SCALE. DATA FORMAT DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621. THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC, WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER. D6 & D7 = GAIN, D4 & D5 = LPF D1 = SHDN. D0 = GEN. PURPOSE OUTPUT. ,
Figure 6. Current Controlled Clock Frequency
10 0 -10 -20 GAIN (dB) -30 -40 -50 -60 -70 VS = 3V TA = 25C -80 1k 10k VCONTROL RBIAS RBIAS
+ -
100k 1M FREQUENCY (Hz)
10M
6603 F07
fCLK = 247.2MHz * (10k/RBIAS) * (1 - VCONTROL/1.17V)
6603 F08
Figure 7. Frequency Response Controlled by LTC2621-1
Figure 8. Voltage Controlled Clock Frequency
6603f
17
LTC6603 APPLICATIONS INFORMATION
than 100k. If the value of RBIAS is too large, the filters will not receive a large enough bias current, possibly causing errors due to insufficient settling. Be sure to obey the absolute maximum specifications when driving a clock into CLKIO (Pin 15). Input Common Mode and Differential Voltage Range The input signal range extends from zero to the V+IN supply voltage. This input supply can be tied to V+A and V+D, or driven up to 5.5V for increased input signal range. Figure 9 shows the distortion of the filter versus common mode input voltage with a 2VP-P differential input signal (V+IN = 5V).
-60 HD3, f = 1MHz DISTORTION (dBc)
control bits LPF1 and LPF0. The differential input impedance is a function of the clock frequency and the control bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the typical input impedances for a clock frequency of 80MHz. These input impedances are all proportional to 1/fCLK, so if the clock frequency were reduced by half to 40MHz, the impedances would be doubled. The typical variation in dynamic input impedance for a given clock frequency is -20% to +35%.
Table 5. Differential, Common Mode Input Impedances, fCLK = 80MHz
GAIN1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GAIN0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LPF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LPF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Differential Common Mode Input Impedance Input Impedance (k) (k) 38 16 2.5 2.5 20 9.5 2.5 2.5 10 5.4 1.9 1.9 5.2 2.8 1.6 1.6 40 20 5 5 40 20 5 5 40 20 5 5 40 20 5 5
-70
HD3, f = 200kHz -80 RBIAS = 30.9k, VS = 3V, V+IN = 5.5V LPF1 = 1, BW = 2.5MHz, GAIN = 24dB VOUT = VP-P, TA = 25C 1.5 2.0 2.5 3.0 3.5 4.0 4.5 COMMON MODE INPUT VOLTAGE (V) 5.0
-90 1.0
6603 F09
Figure 9. Distortion vs Common Mode Input Voltage (5V)
For best performance, the inputs should be driven differentially. For single ended signals, connect the unused input to VOCM (Pin 3) or to a quiet DC reference voltage. To achieve the best distortion performance, the input signal should be centered around the DC voltage of the unused input. Refer to the Typical Performance Characteristics section to estimate the distortion for a given input level. Dynamic Input Impedance The unique input sampling structure of the LTC6603 has a dynamic input impedance which depends on the configuration and the clock frequency. This dynamic input impedance has both a differential component and a common mode component. The common mode input impedance is a function of the clock frequency and the
Output Common Mode and Differential Voltage Range The output voltage is a fully differential signal with a common mode level equal to the voltage at VOCM. Any of the filter outputs may be used as single-ended outputs, although this will degrade the performance. The output voltage range is typically 0.5V to V+A - 0.5V (V+A = 2.7V to 3.6V). The common mode output voltage can be adjusted by overdriving the voltage present on VOCM. To maximize the undistorted peak-to-peak signal swing of the filter, the VOCM voltage should be set to V+A /2. Note that the output common mode voltages of the two channels are
6603f
18
LTC6603 APPLICATIONS INFORMATION
not independent as they are both set by the VOCM pin. Figure 10 illustrates the distortion versus output common mode voltage for a 2VP-P differential input voltage and a common mode input voltage that is equal to mid-supply.
-60 RBIAS = 30.9k, VS = 3V, GAIN = 24dB, TA = 25C SIGNAL FREQUENCY = 200kHz HD3, LPF1 = 0, LPF0 = 1 HD2, LPF1 = 0, LPF0 = 1
Connecting resistors between each input and V+IN will pull the input common mode voltage up, increasing the input signal swing. The resistance, RPULL-UP, necessary to set the input common mode voltage, VICM, to any desired level can be calculated by RPULL where
UP
-65 DISTORTION (dBc)
= RCM
VSUPPLY VICM
1
-70 HD2, LPF1 = 1 -75 HD3, LPF1 = 1 -80 0.8
RCM = 40k*80MHz/fCLK for LPF1=0, LPF0=0 RCM = 20k*80MHz/fCLK for LPF1=0, LPF0=1 RCM = 5k*80MHz/fCLK for LPF1=1 For example, if the lowpass cutoff frequency is set to 2.5MHz, 5k resistors connected between each input and V+IN will set the input common mode voltage to midsupply. Circuit A of Figure 12 is for a fixed CLK and LPF0, LPF1 setting. If the clock varies or the LPF0, LPF1 setting changes then Circuit B of Figure 12 should be used. Due to the sampled data nature of the filter, an anti-aliasing filter at the inputs is recommended. The output common mode voltage is equal to the voltage of the VOCM pin. The VOCM pin is biased to one half of the supply voltage by an internal resistive divider (see Block Diagram). To alter the common mode output voltage, VOCM can be driven with an external voltage source or resistor network. If external resistors are used, it is important to note that the internal 2k resistors can vary 30% (their ratio varies only 1%). The filter outputs can also be AC coupled. The LTC6603 can be interfaced to an A/D converter by pulling CLKCNTL (Pin 5) to V+D. This configures CLKIO (Pin 15) as a clock output, which can be used to drive the clock input of the A/D converter. This allows the A/D converter to be synchronized with the filter sampling clock, avoiding "beat frequencies" and simplifying the board layout. Any routing attached to the CLKIO pin should be as short as possible, in order to minimize reflections. Similarly, the LTC6603 can be interfaced to another LTC6603 in a master/slave configuration as shown in Figure 13. This
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1.0 1.4 1.2 1.6 1.8 COMMON MODE OUTPUT VOLTAGE (V)
6603 F10
Figure 10. Distortion vs Common Mode Output Voltage
Interfacing to the LTC6603 The input and output common mode voltages of the LTC6603 are independent. The input common mode voltage is set by the signal source if DC coupled, as shown in Figure 11. If the inputs are AC coupled, as shown in Figure 12 (Circuit A), the input common mode voltage will be pulled to ground by an equivalent resistance of RCM, shown in Table 5. This does not affect the filter's performance as long as the input amplitude is less than 0.5VP-P. At low filter gain settings, a larger input voltage swing may be desired.
VSUPPLY LTC6603 V+IN V+A V+D +INA -INA VIN+ +OUTA -OUTA VOUT+ VOUT-
0.1F
+ -
VIN-
+ -
1F
VOCM GND
DC COUPLED INPUT VIN (COMMON MODE) = (VIN+ + VIN-)/2 VOUT (COMMON MODE) = (VOUT+ + VOUT-)/2 = VSUPPLY/2
6603 F11
Figure 11. DC Coupled Inputs
19
LTC6603 APPLICATIONS INFORMATION
CIRCUIT A VSUPPLY VSUPPLY LTC6603 V+IN V+A V+D +INA +OUTA -OUTA VOUT+ VOUT-
0.1F RPULL-UP RPULL-UP
VIN+
+ -
0.1F VIN-
-INA
+ -
0.1F
1F
VOCM GND
AC COUPLED INPUT VIN (COMMON MODE) = VOUT (COMMON MODE) = VSUPPLY/2 CIRCUIT B V+IN
VSUPPLY
V+A
0.1F
1.87k 0.1F
0.1F
LTC6603 V+IN V+A V+D +INA -INA +OUTA -OUTA VOUT+ VOUT-
1.87k
+ -
VIN+
1.87k
+ -
VIN-
0.1F
1.87k
1F
VOCM GND
AC COUPLED INPUT VIN (COMMON MODE) =
RCM * V +IN 2 * RCM + 1.87k
6603 F12
Figure 12. AC Coupled Inputs
3.3V LTC6603 MASTER V+IN V+A V+D
3.3V LTC6603 SLAVE V+IN V+A V+D +OUTA -OUTA
0.1F
0.1F
+
VIN1
+INA -INA CLKCNTL CLKIO GND
+
VOUT1
+
VIN2
+INA -INA CLKCNTL CLKIO GND
+OUTA -OUTA
+
VOUT2
-
-
-
-
6603 F13
Figure 13. Two Devices in a Master/Slave Clocking Configuration
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20
LTC6603 APPLICATIONS INFORMATION
results in four matched filter channels, all synchronized to the same clock. The master has its CLKCNTL pin pulled to V+D, configuring its CLKIO pin as an output, while the slave has its CLKCNTL pin pulled to ground, configuring its CLKIO pin as an input. Note that in order to synchronize the two filters, the clock frequency must not be buffered. This requires that the filters be close together on the PC board. If the clock is buffered, the filters would have matching bandwidths, but would not be synchronized. Output Drive The filter outputs can drive 1k and/or 50pF loads connected to AC ground with a 0.5V to 2.5V signal (corresponding to a 4VP-P differential signal). For differential loads (loads connected between +OUTA and -OUTA or +OUTB and -OUTB) the outputs can produce a 4VP-P signal across 2k and/or 25pF For smaller signal amplitudes, the outputs can . drive correspondingly larger loads. For larger capacitive loads, an external 50 series resistor is recommended for each output. Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output. The clock feedthrough is measured with +INA and -INA (or +INB, -INB) tied to VOCM and depends on the PC board layout and the power supply decoupling. The clock feedthrough can be reduced with a simple RC post filter. Decoupling Capacitors The LTC6603 uses sampling techniques, therefore its performance is sensitive to supply noise. 0.1F ceramic decoupling capacitors must be connected from V+A (Pin 2) and V+D (Pin 16) to ground with leads as short as possible. A ground plane should be used. Noisy signals should be isolated from the filter's input pins. In addition, a 0.1F decoupling capacitor at Pin 20 is recommended since this pin receives clocked current injection. Aliasing Aliasing is an inherent phenomenon of sampled data filters. Significant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling frequency. The ratio of the LTC6603 input sampling frequency to the clock frequency, fCLK, is determined by the state of control bits LPF1 and LPF0. Table 6 shows the possible input sampling frequencies for a clock frequency of 80MHz. The input sampling frequency is proportional to the clock frequency. For example, if the clock frequency is lowered from 80MHz to 40MHz, the input sampling frequency will be lowered by half. Input signals with frequencies near the input sampling frequency will be aliased to the passband of the filter and appear at the output unattenuated.
Table 6. Input Sampling Frequency (fCLK = 80MHz)
LPF1 0 0 1 1 LPF0 0 1 0 1 Input Sampling Frequency (MHz) 20 40 160 160
A simple LC anti-aliasing filter is recommended at the filter inputs to attenuate frequencies near the input sampling frequency that will be aliased to the passband. For example, if the clock frequency is set to 80MHz and the cutoff frequency of the filter is set to its maximum (LPF1 = `1'), the lowest frequency that would be aliased to the passband would be fCLK - fCUTOFF, i.e. 160MHz - 2.5MHz = 157.5MHz. The LTC6603 filter inputs should be driven by a low impedance output (<100). Wideband Noise The wideband noise of the filter is the RMS value of the device's output noise spectral density. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering. Power Supply Current The power supply current depends on the state of the lowpass cutoff frequency controls (LPF1, LPF0) and the value of RBIAS. When the LTC6603 is programmed for the middle cutoff frequency (LPF1 = `0', LPF0 = `1'), the supply current is reduced by about 23% relative to the supply current for the higher bandwidth setting. Pro6603f
21
LTC6603 APPLICATIONS INFORMATION
gramming the LTC6603 for the lowest cutoff frequency (LPF1 = `0', LFP0 = `0') reduces the supply current by about 60%. Power supply current vs. cutoff frequency for various bandwidth settings is shown in the "Typical Performance Characteristics" section. The LTC6603 can be programmed through the serial interface to enter into a low power shutdown mode. The power supply current during shutdown is less than 235A. Supply Current vs. Noise Tradeoff The passband of the LTC6603 is determined by the master clock frequency (which is set by RBIAS when the internal oscillator is used), LPF1 and LPF0. The LTC6603 is optimized for use with RBIAS having a value between 200k and 30.9k to set the internal oscillation frequency from 12.36MHz to 80MHz. The lowpass corner frequency is proportional to the clock frequency (internal or external).
100
To extend the filter's operational frequency range, the master clock is divided down before reaching the filter. LPF1 and LPF0 set the division ratio of the lowpass clock. Figure 14 shows the possible cutoff frequencies versus fCLK, LPF1 and LPF0. Overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. Figure 15 shows supply current as a function of the filter cutoff frequency, LPF1 and LPF0. Note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. The input referred integrated noise voltage for a passband gain of 24dB is shown in Table 7. Note that the noise is higher for the higher bandwidth settings. This creates a tradeoff between supply current and noise. For a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise.
180 160 SUPPLY CURRENT (mA)
LPF1 = 0 LPF0 = 0 fCLK (MHz)
140 120 100 80 60 40 20
TA = 25C VS = 3V CLKCNTL PIN FLOATING GAIN = 0dB LPF1 = 0 LPF0 = 1 LPF1 = 0 LPF0 = 0 LPF1 = 1
LPF1 = 1
LPF1 = 0 LPF0 = 1 10 10k 100k 1M FILTER CUTOFF FREQUENCY (Hz) 10M
6603 F14
0 10k
100k 1M FILTER CUTOFF FREQUENCY (Hz)
10M
6603 F15
Figure 14. fCLK vs Filter Cutoff Frequencies
Figure 15. Supply Current vs Filter Cutoff Frequency
Table 7. Total Input Referred Integrated Noise Voltage (Passband Gain = 24dB)
LPF1 0 0 1 LPF0 0 1 X Noise Voltage -81dBm -80dBm -76dBm
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22
LTC6603 TYPICAL APPLICATIONS
LTC6603 Parallel Clock Control
3V 1 V+IN 19 18 13 12 15 17 3V 1 2 3 CS SCLK SDI VOUT GND V+ 6 5 4 0.1F 3V 20 22 21 14 25 VC R2 0.1F VB 0.1F R1 3 DAC VOUT RANGE 0V TO 2.5V (USING THE LTC2630 INTERNAL REFERENCE) 24 23 7 8 4 +INA -INA +INB -INB RBIAS VOCM 2 V+A 1 V+IN 24 23 7 8 4 R3 DIODES INC DMN2004DWK VOCM R2 R1 0.1F 3 0.1F +INA -INA +INB -INB RBIAS VOCM 2 V+A 16 V+D +OUTA -OUTA +OUTB LTC6603 -OUTB CLKIO SER
LTC6603 SPI Clock Control
3V 0.1 16 V+D +OUTA -OUTA +OUTB LTC6603 -OUTB CLKIO SER 19 18 13 12 15 17 0.1F
20 22 21 14
CAP GAIN1 GAIN0(D0) GND GND
CLKCNTL SDO SDI LPF0(SCLK) LPF1(CS)
5 11 10 9 6
LTC2630 8-BIT DAC
CAP GAIN1 GAIN0(D0) GND GND
CLKCNTL SDO SDI LPF0(SCLK) LPF1(CS)
5 11 10 9 6
3V
CLK1 CLK0 LPF1 LPF0 GAIN1 GAIN0 CLK1 0 0 1 1 CLK0 0 1 0 1 RBIAS1 RBIAS2 RBIAS3 RBIAS4 fCLK1 fCLK2 fCLK3 fCLK4
25
CS1
6603 TA02
SCK R1+ R2 R1* R2
SDI VC
CS2
6603 TA03
IF R1 = 51.1k and R2 = 78.7k THEN THE fCLK RANGE IS 12.36MHz to 80MHz R1 =
12 5.282 * 1012 , R2 = 5.282 * 10 1.137fCLKHI + fCLKLO fCLKHI - fCLKLO
fCLK = 2.472 * 1012
VB * R2
VC RANGE 0V to 2.5V, VB = 1.17V IF VC = 0V THEN fCLK= fCLKHI IF VC = 2.5V THEN fCLK= fCLKLO
RBIAS1 > RBIAS2 OR RBIAS3 RBIAS = 2472 fCLK RBIAS IN k fCLK in MHz R1 = RBIAS1 R2 = RBIAS1 * RBIAS2 RBIAS1 - RBIAS2
DESIGN PROCEDURE 1. CHOOSE fCLK1, fCLK2 AND fCLK3 2. CALCULATE RBIAS1, RBIAS2 AND RBIAS3 3. CALCULATE R2, R3 AND RBIAS4 R3 = RBIAS1 * RBIAS3 RBIAS1 - RBIAS3 RBIAS4 = R1 * R2 * R3 R1 * (R2 + R3) + R2 * R3
PACKAGE DESCRIPTION
UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) 0.70 0.05 PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
23 24 0.40 0.10 1 2
4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES)
2.45 0.10 (4-SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.200 REF 0.00 - 0.05
(UF24) QFN 0105
0.25 0.05 0.50 BSC
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6603 TYPICAL APPLICATION
Direct Conversion Demodulator and I and Q Baseband Filter, fCUTOFF =1.92MHz (UTMS WCDMA)
5V 3V 49.9 56nH* 10pF 4 5 EN 6 VCC 7V
CC
3.9pF RF IN
56nH* 10pF
0.1F 1 V+IN 10pF 24 23 7 8 +INA -INA +INB -INB RBIAS VOCM 2 V+A 16 V+D +OUTA -OUTA +OUTB LTC6603 -OUTB CLKIO SER
0.1F 100pF 49.9 56nH* IOUT 10pF
3
2
1 16
10pF 56nH*
100pF
GND GND RF GND IOUT + 15 - I LTC5575 OUT QOUT + 14 - 13 Q
OUT
19 18 13 12 15
5V
49.9
56nH* 10pF QOUT 10pF
8V CC 1F 0.1F 1000pF GND 9
56nH* 10pF 10pF 56nH* 100pF 10pF 0.1F 40.2k 0.1F
4 3
100pF 17 49.9 56nH*
LO GND VCC 10 11 12
20 22 21 14 25
5.6pF LO IN
CAP GAIN1 GAIN0(D0) GND GND
CLKCNTL SDO SDI LPFO(SCLK) LPF1(CS)
5 11 10 9 6
3V
1000pF
3V
*COILCRAFT 0603HP
GAIN1 GAIN0 BASEBAND GAIN CONTROL
6603 TA04
RELATED PARTS
PART NUMBER DESCRIPTION LTC 1565-31 LTC1566-1 LTC1567 LTC1568 LTC1569-6 LTC1569-7 LT1994 LTC6406 LT6600-2.5 LT6600-5 LT6600-10 LT6600-15 LT6600-20 LTC6601 LTC6602 LTC6604-2.5 LTC6604-5 LTC6604-10 LTC6604-15
(R)
COMMENTS Continuous Time, SO8 Package, Fully Differential Continuous Time, SO8 Package 1.4nV/Hz Op Amp, MSOP Package, Differential Outputs Lowpass and Bandpass Filter Designs Up to 10MHz, Differential Outputs fC 64kHz, One Resistor Sets fC, SO-8 Differential Inputs fC 256kHz, One Resistor Sets fC, SO-8 Differential Inputs Adjustable, Low Power, VS = 2.375V to 12.6V Low Noise: 1.6nV/Hz, Low Power: 18A 86dB S/N with 3V Supply, SO-8 Package 82dB S/N with 3V Supply, SO-8 Package 82dB S/N with 3V Supply, SO-8 Package 76dB S/N with 3V Supply, SO-8 Package 76dB S/N with 3V Supply, SO-8 Package fC 7MHz to 27MHz Fully Differential 4mm x 4mm QFN Package Fully Differential 4mm x 4mm QFN Package 86dB S/N with 3V Supply, 4mm x 7mm QFN Package 82dB S/N with 3V Supply, 4mm x 7mm QFN Package 82dB S/N with 3V Supply, 4mm x 7mm QFN Package 76dB S/N with 3V Supply, 4mm x 7mm QFN Package
650kHz Linear Phase Lowpass Filter Low Noise, 2.3MHz Lowpass Filter Very Low Noise, High Frequency Filter Building Block Very Low Noise, 4th Order Building Block Low Power 10-Pole Delay Equalized Elliptic Lowpass 10-Pole Delay Equalized Elliptic Lowpass Low Distortion, Low Noise Differential Amplifier/ADC Driver 3GHz Low Noise, Rail-to-Rail Input Differential ADC Driver Very Low Noise, Fully Differential Amplifier and 2.5MHz Filter Very Low Noise, Fully Differential Amplifier and 5MHz Filter Very Low Noise, Fully Differential Amplifier and 10MHz Filter Very Low Noise, Fully Differential Amplifier and 15MHz Filter Very Low Noise, Fully Differential Amplifier and 20MHz Filter Pin-Configurable Second Order Filter/Driver Dual Baseband Bandpass Filter for UHF RFID Dual Very Low Noise, Differential Amp and 2.5MHz Filter Dual Very Low Noise, Differential Amp and 5MHz Filter Dual Very Low Noise, Differential Amp and 10MHz Filter Dual Very Low Noise, Differential Amp and 15MHz Filter
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24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0908 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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