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T6B70BFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70BFG
Interface IC for Hot Water Dispensers
The T6B70BFG is designed to be used mainly as an interface IC for communication between hot water dispensers and the corresponding controller unit, and comes equipped with a two channel 4-bit D/A converter, pseudo sine wave generator and an external analog signal detection circuit.
Features
* * * * Built-in two channel 4-bit D/A converter (opposite polarities) Built-in pseudo sine wave generator (external clock 1/16 frequency divider) Built-in external analog signal detection/non-detection circuit Built-in two channel analog switch Weight: 0.16 g (typ.)
Block Diagram
4-bit D/A converter 4-bit D/A converter
OSCIN 1 OSCOUT 2 FOUT 3 /SCTL 4 SW1IN 14 SW1OUT 15
Modulation control circuit 16 frequency divider unit
0C Pseudo sine wave 180C generator Waveform initialization block
13 SOUT+ 12 SOUT-
16 VDD
Zero crossing waveform shaping circuit
Amp input circuit
7 AMPIN
6 AMPOUT SW2IN 11 SW2OUT 10 /RESET 5
Reset circuit
Cycle measurement counter Detection/non-detection judgment circuit
8 VSS 9 /DOUT
Output buffer
Pin Assignment Diagram
OSCIN 1 OSCOUT 2 FOUT 3 /SCTL 4 /RESET 5 AMPOUT 6 AMPIN 7 VSS 8 16 VDD 15 SW1OUT 14 SW1IN
T6B70BFG
13 SOUT+ 12 SOUT- 11 SW2IN 10 SW2OUT 9 /DOUT
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Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol OSCIN OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN VSS /DOUT SW2OUT SW2IN SOUT- SOUT+ SW1IN SW1OUT VDD Input/Output Input Output Output Input Input Output Input Output Output Input Output Output Input Output Pins connected to oscillation Pins connected to oscillation Output pin for oscillation waveform shaping circuit Modulation control signal input pin Reset signal input pin Amplifier signal output pin Amplifier signal input pin Device ground pin (0 V) Output pin for amplifier input signal detector Output pin on analog SW2 side Input pin on analog SW2 side Pseudo sine wave (opposite polarity of SOUT + output) output pin Pseudo sine wave output pin Input pin on analog SW1 side Output pin on analog SW1 side Device power supply pin (+5 V) Function
The equivalent circuit diagrams provided in the above table are given to facilitate understanding in designing the external circuitry but are not intended to accurately represent the internal circuitry.
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Functions
1. Pseudo sine wave generator and 4-bit D/A converters (transmission block)
The pseudo sine wave signal with Fosc/16 frequency is output from the pseudo sine wave output pins (SOUT+ and SOUT-). The output polarity of SOUT+ and SOUT- are the opposite. The transmission block (pseudo sine wave generator and 4-bit D/A converter are as shown below (SOUT+ pin side):
SOUT+ pin MSB R Pseudo sine wave generator R R
SOUT+ R R R R LSB R R VSS R R SOUT- 2R
FOSC
RST
The data of the pseudo sine wave generator is output in the following sequence: 0 1 3 6 9 C E F F E C 9 6 3 1 0 (hexadecimal)
F E C F E C
9
9
6 3 0 1
6 3
FSIN 250 kHz @FOSC = 4 MHz
1
0
Therefore, when there is no load, the pseudo sine waveform of the positive and negative output is like a staircase (as illustrated above). An analog switch is built-in so that the driver output buffer connects to the transmission line only during transmission. However, an emitter follower circuit is externally connected to the driver output buffer. The phase difference between the positive and negative output is within 180 5 (to account for fluctuation in the pseudo sine wave output phase).
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2. Amplifier input circuit and signal detection/non-detection circuit (reception block)
The modulation signal input block is equipped with high and a low comparator to detect only when the external sine wave signal's amplitude is above the defined threshold. In this way, signals with amplitudes lower than the specified threshold (e.g., noise signals) are prevented from being mistakenly detected as sine waves. The detection frequency range (frequency window) is determined by the divider ratio 1/17 to 1/15 of Fosc. Detection/non-detection confirmation conditions are such that when the signals within the specified frequency range are detected (or not detected) in succession, the signals are controlled. It takes about 9 to 15 waves (based on Fosc 1/16 frequency) to make detection/non-detection confirmation in this manner.
VDD R1
VDD Reference voltage VH
High comparator VA + - VBIAS Low comparator VB + -
APU
7 R3 AMPIN pin APU Reference voltage VL
R2
R
Q
Cycle measurement counter
Detection /non-detection 9 judgment /DOUT pin circuit
S
Q
RESET
R4
6 AMPOUT pin VSS
VSS
AMP IN input sine waveform
VH
Input sensitivity VL V PP
Reception detected
Reception non-detected
Reception non-detected
Reception non-detected
AMPOUT output timing (/RESET = L)
VH VL
VBIAS
AMPOUT Truth Table
VA VBIAS > VH L H H VB H H L AMPOUT L Hold H
AMPOUT
Held at high Held at low
VH > VBIAS > VL VBIAS < VL
VBIAS < VL
VBIAS > VH
VH > VBIAS > VL VH > VBIAS > VL
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3. Transmission block function and timing
When the modulation control input (/SCTL) is in High-level, the pseudo sine wave output is held at 0 phase of the pseudo sine wave. When the modulation control input changes from High-level to Low-level, the pseudo sine wave output (SOUT+) initially outputs from -90 (SOUT- outputs from +90). The time required to turn ON in this case is as follows: td (ON) < 500 ns When modulation control input changes from Low-level to High-level, the phase is forcibly held at 0 (the pseudo sine wave output is stopped), regardless of the phase of the pseudo sine wave output. The time required to turn OFF in this case is as follows: td (OFF) < 1 s
/SCTL
td (ON) SOUT+ pseudo sine wave output (SOUT- is the opposite polarity)
td (OFF)
4. Reception block function and timing
Once it is okay to receive the amplifier input signal, the time it takes for the /DOUT pin to changes from High to Low (T (DET)) is about 9 to 15 waves (based on Fosc 1/16 frequency). This condition is only valid when the cyclic input signal within the range specified by the frequency window is detected (or not detected) in continuation.
Amplifier input T (DET) /DOUT
T (DET)
Note 1: You are free to use any kind of communication protocol you wish, however be sure to configure a time of carrier wave x 15 waves or more for both when there are and aren't signals.
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Timing Chart (SOUT+ = SW1IN, SW1OUT, SOUT- = SW2IN, SW2OUT)
VDD
/RESET OSCIN (4 MHz)
FOUT
AMPIN
(250 kHz)
VPP
AMPOUT
X
/SCTL td (ON) SOUT+
Transmitting
FSIN
td (OFF)
VOPP SOUT-
/DOUT
Receiving TDET TDET
SW1IN SW1OUT
X
X
SW2IN SW2OUT
X
X
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Absolute Maximum Ratings (Ta = 25 1.5C)
Characteristics Power supply voltage Input voltage Input peak current Operating temperature Storage temperature Power dissipation Symbol VDD VI IIK Topr Tstg PD (Note 1) Rating -0.3 to 6.0 -0.3 to VDD + 0.3 -20 to 20 -20 to 80 -55 to 125 0.54 Unit V V mA C C W
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result injury by explosion or combustion. Note 1: Power dissipation decreases approximately 4.35 mW per degree (Centigrade).
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Electrical Characteristics
Characteristics VDD pin (pin 16) Operating voltage Current consumption VDD IDD 1 When there is no load; FOSC = 4 MHz 4.5 5.0 5.5 10 V mA
(unless otherwise specified, VDD = 5.0 V, VSS = 0 V, FOSC = 4 MHz and Ta = -20 to 80C)
Symbol Test Circuit Test Condition Min Typ. Max Unit
OSCIN pin (pin 1) and OSCOUT pin (pin 2) Oscillation frequency High level Input voltage Low level Input current High level Low level High level Low level VILOSC IIHROSC IILROSC VOHOSC VOLOSC 3 4 4 3 4 VIN = 5 V, Ta = 25C VIN = 0 V, Ta = 25C IOH = -0.1 mA IOL = +0.1 mA FOSC VIHOSC 2 3 1 0.7 VDD VSS 3.2 -3.2 VDD - 1 VSS 4 6.58 -6.58 10 VDD 0.3 VDD 13.2 -13.2 VDD VSS + 0.6 V V MHz
A
Output voltage
/RESET pin (5 pin) Low to High input switching level High to Low input switching level High-level input current Pull-up resistance 1 Pull-up resistance 2 /SCTL pin (pin 4) Low to High input switching level High to Low input switching level Input current High level Low level VIHSCTL VILSCTL IIHSCTL IILSCTL 8 8 9 9 VIN = VDD VIN = VDD 0.65 VDD VSS -1 -1 VDD 0.35 VDD 1 1 V V A VIHRST VILRST IIHRST IILRRST1 IILRRST2 5 5 6 7 7 VIN = VDD VIN = VSS, Ta = 25C VIN = VSS, Ta = -20 to 80C 0.65 VDD VSS -10 9 6.3 15 VDD 0.35 VDD 10 21 27.3 V V A k k
FOUT pin (pin 3) Output voltage High level Low level VOHFOUT VOLFOUT 10 11 IOH = -1.0 mA IOL = +1.0 mA VDD - 1 VSS VDD VSS + 0.6 V
/DOUT pin (pin 9) Output voltage High level Low level VOHDOUT VOLDOUT 12 13 IOH = -1.0 mA IOL = +1.0 mA FOSC = 4 MHz, AMPIN = 250 kHz Time it takes for /DOUT to change from High to Low FOSC = 4 MHz, AMPIN = 250 kHz Time it takes for /DOUT to change from Low to High VDD - 1.0 VSS VDD VSS + 0.6 V
Non-reception to reception detection time
TDET1
19
40
60
s
Reception to non-reception detection time
TDET2
19
36
56
s
Note: The direction of current flow should be + (sink) when flowing into the IC and - (drain) when flowing out of the IC.
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Characteristics AMPIN pin (pin 7) Input dynamic range Pull-up resistance 1 Pull-up resistance 2 Pull-down resistance 1 Pull-down resistance 2 Amplifier input bias voltage VAMPIN IILRAPU1 IILRAPU2 IIHRAPD1 IIHRAPD2 VBIAS 14 15 15 16 16 17 VIN = VSS, Ta = 25C VIN = VSS, Ta = -20 to 80C VIN = VDD, Ta = 25C VIN = VDD, Ta = -20 to 80C No load (design target) No load, receivable amplitude range is 250 kHz, when sine wave signal is applied. (design target) FOSC = 4 MHz FOSC = 4 MHz FOSC = 4 MHz VSS 11.6 7 5.9 3 1.54 19.4 9.8 1.63 VDD 27.2 38 13.7 19.2 1.71 V k k k k V Symbol Test Circuit Test Condition Min Typ. Max Unit
Amplifier input sensitivity
VPP
18
0.3
0.45
V
Detection frequency range Non-detection frequency (low frequency) Non-detection frequency (high frequency)
DETON DETOFF1 DETOFF2
19 19 19
236 266
266 236
kHz kHz kHz
SW1IN pin (pin 14) and SW1OUT pin (pin 15) Analog switch input voltage Analog switch output voltage OFF-leak current of analog switch 1 ON-resistance of analog switch 1 VINASW1 VOUTASW1 IOFFASW1 20 /SCTL = H, SW1IN = VDD, SW1OUT = VSS /SCTL = L, SW1IN = 5 V, SW1OUT = 0 V Current measure VSS VSS -1 VDD VDD 1 V V A
RONASW1
21
35
105
SW2IN pin (pin 11) and SW2OUT pin (pin 10) Analog switch input voltage Analog switch output voltage OFF-leak current of analog switch 2 ON-resistance of analog switch 2 VINASW2 VOUTASW2 IOFFASW2 20 /SCTL = H, SW2IN = VDD, SW2OUT = VSS /SCTL = L, SW2IN = 5 V, SW2OUT = 0 V Current measure VSS VSS -1 VDD VDD 1 V V A
RONASW2
21
35
105
SOUT+ pin (13 pin), SOUT- pin (12 pin) Output voltage Pseudo sine wave output frequency Pseudo sine wave output start time Pseudo sine wave output stop time Equivalent output impedance VOPP FSIN tdON tdOFF ROUTSIN 22 23 23 23 24 Maximum voltage value when there is no load FOSC = 4 MHz /SCTL = H L /SCTL = L H No load 0.85 VDD 2.8 250 4 VDD 500 1 5.2 V kHz ns s k
Note: The direction of current flow should be + (sink) when flowing into the IC and - (drain) when flowing out of the IC.
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Test Circuit
(1) Current consumption
5V 4 MHz PG A 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 ICC 1 to 10 MHz PG FOSC Monitor 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(2) Oscillation frequency
5V
(3) High-level input voltage Low-level input voltage High-level output voltage
5V VIHOSC VILOSC -0.1 mA 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16
(4) High-level input current Low-level input current Low-level output voltage
IIHROSC IILROSC A +0.1 mA IOL VIN 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 5V
VOHOSC IOH V
SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
VOLOUT V
(5) Low to High input switching level High to Low input switching level
5V 4 MHz PG 1 2 3 4 VIHRST VILRST 5 6 7 8 OSCIN OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 Monitor Monitor
(6) High-level input current
5V 1 OSCIN 2 OSCOUT 3 FOUT IIHRST A VIN 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
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(7) Pull-up resistance 1 Pull-up resistance 2
5V 1 OSCIN 2 OSCOUT IILRRST1 IILRRST2 A 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 VIHSCTL VILSCTL 4 MHz PG 1 2 3 4 5 6 7 8 OSCIN OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 Monitor Monitor
(8) Low to High input switching level High to Low input switching level
5V
(9) High-level input current Low-level input current
5V 1 IIHSCTL 2 IILSCTL 3 A 4 5 VIN 6 7 8 OSCIN OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN VSS VDD 16 SW1OUT 15 SW1IN 14
(10) High-level output voltage
5V 1 OSCIN 2 OSCOUT 3 FOUT -0.1 mA IOH VOHFOUT V 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(11) Low-level output voltage
5V +1.0 mA 1 IOL 2 3 4 5 6 7 8 OSCIN OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(12) High-level output voltage
5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 -1.0 mA /DOUT 9 VOHDOUT V
VOLFOUT V
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T6B70BFG
(13) Low-level output voltage
5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 +1.0mA SW2IN 11 SW2OUT 10 /DOUT 9 V VOLDOUT 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(14) Input dynamic range
5V
Monitor
IOL VAMPIN
6 AMPOUT 7 AMPIN 8 VSS
(15) Pull-up resistance 1 Pull-up resistance 2
5V 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL IILRAPU1 IILRAPU2 A 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(16) Pull-down resistance 1 Pull-down resistance 2
5V 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL IIHRAPD1 IIHRAPD2 A VIN 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(17) Amplifier input bias voltage
5V 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN VBIAS V 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(18) Amplifier input sensitivity
5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET Monitor 250 kHz Vp-p SIN wave 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
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(19) Detection frequency range
Non-detection frequency (low frequency) Non-detection frequency (high frequency) Non-reception to reception detection time Reception to non-reception detection time
5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL DETON DETOFF1 DETOFF2 200 to 300 kHz PG 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 Monitor TDET1 TDET2 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 IOFFASW2 A 5V 5V 4 MHz PG RONASW1 A 5V 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 5V 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 V VOPP V VOPP 5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT Monitor FSIN DEGSOUT tdON Monitor tdOFF 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 5V A A ROUTSIN 5V ROUTSIN IOFFASW1 A 5V
(20) OFF-leak current of analog switch 1 OFF-leak current of analog switch 2
5V
(21) ON-resistance of analog switch 1 ON-resistance of analog switch 2
5V 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9 RONASW2 A
(22) Output voltage
(23) Pseudo sine wave output frequency Pseudo sine wave output start time Pseudo sine wave output stop time
5V 4 MHz PG 1 OSCIN 2 OSCOUT 3 FOUT 4 /SCTL 5 /RESET 6 AMPOUT 7 AMPIN 8 VSS VDD 16 SW1OUT 15 SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 /DOUT 9
(24) Equivalent output impedance
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IC Marking Specification
Lot Code
T6B70BFG
Trace Code
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Toshiba CMOS SOP Embossed Taping - Common Specifications
1. Applicable Scope
This specification defines the embossed taping package specifications and related items for Toshiba flat package CMOS ICs. As a rule, these taping specifications comply with JEITA (RC-1009B) and EIA (EIA481).
2. Specifications
2.1 Tape Form and Dimensions
Package 300 mm 14, 16 pin (JEITA Type II) 300 mm 20 pin (JEITA Type II) JEITA Tape Standard TE1612 TE2412
D0 Y
P1
P2 P0 E t
D1 F
X
X
Y
Section view X-X Direction of feed
W
T1
Section view Y-Y
A
A 14, 16 pin type 20 pin type 8.5 0.2 8.3 0.2
B 10.8 0.2 13.2 0.2
W 16.0 0.3 24.0 0.3
F 7.5 0.1 11.5 0.1
E 1.75 0.1 1.75 0.1
P1 12.0 0.1 12.0 0.1
P2 2.0 0.1 2.0 0.1
P0 4.0 0.1 4.0 0.1
D0 1.5 + 0.1 -0 1.5 + 0.1 -0
B Unit: mm
t 0.3 0.1 0.3 0.1 T1 2.1 0.2 2.2 0.2 D1 1.65 0.1 2.0 0.2
Note 1: The tape surface resistance shall be 106 /cm or less. Note 2: The accumulated error tolerance for the feed hole pitch (P0) shall be 0.2 mm per 10 pitches.
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2.2 Seal Tape Dimensions
Unit: mm
Tape Width 14,16 pin type 20 pin type 13.5 21.5 Tape Thickness 0.06 0.06
2.3
Reel Form and Dimensions
(Unit: mm)
2.5 2 0.5 13 0.5 R1.0 21 0.8 W 330 2 80 2 T t = 3.0 max
(a)
Unit: mm
14,16 pin W dimension 20 pin + 2.0 16.4 - 0 + 2.0 24.4 - 0
(a)
Bar code label (See page 18)
2.4
Insertion Direction
Pin 1
Type L (EL)
Direction of feed
2.5
Tape Minimum Bending Radius
The strength of the seal tape shall not change even when an IC is inserted into the tape and the tape is bent 40 mm. In addition, the tape and inserted IC shall not change under the corresponding conditions.
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2.6 Seal Tape Peeling Strength
300 mm/minut
165 to 180
The seal tape shall maintain a peeling strength of 0.1 N (10 gf) when tape bonding surface is at 165 to 180 and being pulled at a speed of 300 mm per minute. However, the seal tape shall not fracture or break when it is being peeled.
2.7
Leader and Trailer Sections of the Tape
Empty cavities shall be created in leader and trailer sections of the tape in which ICs shall not be inserted as specified below:
Seal Tape Leader section Trailer section Minimum of 500 mm Minimum of 400 mm Carrier Tape Minimum of 400 mm Minimum of 400 mm
Carrier tape Seal tape
Hub end
Start end
Trailer section Empty cavities in which ICs shall not be inserted
Empty cavities in which ICs shall not be inserted Leader section
2.8
IC Insertion Failure Ratio
Item Consecutive insertion failure Non-consecutive insertion failure Tolerated Ratio None 0.1 % or less (per reel) Comments Does not apply to the empty cavities in the leading and trailing sections of the tape.
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3. Standard Packaging Unit
The standard packaging unit for one reel of tape shall be 2000 units.
4. Labeling
The reel shall be labeled with the following: 1) Product Name 2) Quantity 3) Lot No.
5. Boxing
Each completed reel of tape shall be boxed in a cardboard box (one per box). The box shall also be labeled with the same labeling information as the reel (see above). Dimensions
A 14, 16 pin type 20 pin type 340 340 B 25 33
Unit: mm
C 27 35
Bar code label
C
(inner dimension)
A
30 A
B
(inner dimension)
(inner dimension)
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6. Issuing Purchase Orders
When issuing IC purchase orders using the taping packaging information, be sure to include the product name, taping type, insertion direction and quantity as follows:
Example: TC74HC00F (EL) 10000
* Quantity * Insertion * Taping type * IC part number
7. Delivery and Storage Precautions
Tape reels should be delivered with enough care so as to prevent extreme vibration from impacting the product. Tape reels should be kept out of direct sunlight and be kept below 45C during delivery and storage so as to prevent wearing down the peeling strength of seal tape and/or causing other deformities to the tape.
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Package Dimensions
Weight: 0.16 g (typ.)
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About solderability, following conditions were confirmed Solderability (1) Use of Sn-37Pb solder Bath solder bath temperature = 230 dipping time = 5 seconds the number of times = once use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath solder bath temperature = 245 dipping time = 5 seconds the number of times = once use of R-type flux
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
070711EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are designed and manufactured for usage in hot water dispensers. Do not use any of these products for any purposes other than hot water dispensers, unless otherwise agreed in writing by TOSHIBA. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. * The products described in this document are subject to foreign exchange and foreign trade control laws.
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