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(R)
ISL73096RH, ISL73127RH, ISL73128RH
Data Sheet March 23, 2009 FN6475.2
Radiation Hardened Ultra High Frequency NPN/PNP Transistor Arrays
The ISL73096RH, ISL73127RH and ISL73128RH are radiation hardened bipolar transistor arrays. The ISL73096RH consists of three NPN transistors and two PNP transistors on a common substrate. The ISL73127RH consists of five NPN transistors on a common substrate. The ISL73128RH consists of five PNP transistors on a common substrate. One of our bonded wafer, dielectrically isolated fabrication processes provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. The high gain-bandwidth product and low noise figure of these transistors make them ideal for use in high frequency amplifier and mixer applications. Monolithic construction of the NPN and PNP transistors provides the closest electrical and thermal matching possible. Access is provided to each terminal of the transistors for maximum application flexibility. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-07218. A "hot-link" is provided on our website for downloading.
Features
* Electrically Screened to SMD # 5962-07218 * QML Qualified per MIL-PRF-38535 Requirements * Radiation Environment - Gamma Dose () . . . . . . . . . . . . . . . . . 3 x 105RAD(Si) - SEL Immune. . . . . . . Bonded Wafer Dielectric Isolation * NPN Gain Bandwidth Product (FT) . . . . . . . . .8GHz (Typ) * NPN Current Gain (hFE). . . . . . . . . . . . . . . . . . . 130 (Typ) * NPN Early Voltage (VA) . . . . . . . . . . . . . . . . . . . 50V (Typ) * PNP Gain Bandwidth Product (FT). . . . . . . . 5.5GHz (Typ) * PNP Current Gain (hFE). . . . . . . . . . . . . . . . . . . . 60 (Typ) * PNP Early Voltage (VA) . . . . . . . . . . . . . . . . . . . 20V (Typ) * Noise Figure (50) at 1GHz . . . . . . . . . . . . . .3.5dB (Typ) * Collector-to-Collector Leakage. . . . . . . . . . . . . <1pA (Typ) * Complete Isolation Between Transistors
Applications
* High Frequency Amplifiers and Mixers - Refer to Application Note AN9315 * High Frequency Converters * Synchronous Detector
Ordering Information
ORDERING NUMBER 5962F0721801V9A 5962F0721801VXC 5962F0721802V9A 5962F0721802VXC 5962F0721803V9A 5962F0721803VXC ISL73096RHF/PROTO ISL73096RHX/SAMPLE ISL73127RHF/PROTO ISL73127RHX/SAMPLE ISL73128RHF/PROTO ISL73128RHX/SAMPLE INTERNAL MKT. NUMBER ISL73096RHVX ISL73096RHVF ISL73127RHVX ISL73127RHVF ISL73128RHVX ISL73128RHVF ISL73096RHF/PROTO ISL73096RHX/SAMPLE ISL73127RHF/PROTO ISL73127RHX/SAMPLE ISL73128RHF/PROTO ISL73128RHX/SAMPLE TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners..
ISL73096RH, ISL73127RH, ISL73128RH Pinouts
ISL73096RH (16 LD FLATPACK) CDFP4-F16 TOP VIEW ISL73127RH (16 LD FLATPACK) CDFP4-F16 TOP VIEW
Q1B Q1E Q1C Q2E Q2B Q2C Q3E Q3B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
NC Q5C Q5B Q5E Q4C Q4B Q4E Q3C
Q1C Q2C Q2E Q2B NC Q3C Q3E Q3B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Q1E Q1B Q5B Q5E Q5C Q4C Q4E Q4B
ISL73128RH (16 LD FLATPACK) CDFP4-F16 TOP VIEW
Q1C Q2C Q2E Q2B NC Q3C Q3E Q3B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Q1E Q1B Q5B Q5E Q5C Q4C Q4E Q4B
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FN6475.2 March 23, 2009
ISL73096RH, ISL73127RH, ISL73128RH Die Characteristics
DIE DIMENSIONS: 52.8 mils x 52.0 mils x 14 mils 1 mil 1340m x 1320m x 355.6m 25.4m INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 4kA 0.5kA Top Metallization: Type: Metal 1: AlCu (2%)/TiW Thickness: Metal 1: 8kA 0.5kA Type: Metal 2: AlCu (2%) Thickness: Metal 2: 16kA 0.8kA Substrate: UHF-1X Bonded Wafer, DI Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Floating ADDITIONAL INFORMATION: Worst Case Current Density: 3.04 x 105A/cm2 Transistor Count: 5
Metallization Mask Layout
(2) Q2C (1) Q1C (16) Q1E (15) Q1B
(3) Q2E
(14) Q5B
(4) Q2B
(13) Q5E
(5) NC
(12) Q5C
(6) Q3C
(11) Q4C
(7) Q3E
(8) Q3B (9) Q4B (10) Q4E
FIGURE 1. ISL73096RH, ISL73127RH
3
FN6475.2 March 23, 2009
ISL73096RH, ISL73127RH, ISL73128RH Metallization Mask Layout (Continued)
(2) Q2C (1) Q1C (16) Q1E (15) Q1B
(3) Q2E
(14) Q5B
(4) Q2B
(13) Q5E
(5) NC
(12) Q5C
(6) Q3C
(11) Q4C
(7) Q3E
(8) Q3B (9) Q4B (10) Q4E
FIGURE 2. ISL73128RH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 4
FN6475.2 March 23, 2009
ISL73096RH, ISL73127RH, ISL73128RH Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.245 0.130 0.030 0.008 0.250 0.026 0.005 16 MAX 0.115 0.022 0.019 0.009 0.006 0.440 0.285 0.315 0.015 0.370 0.045 0.0015 A b b1 c c1 D MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.22 3.30 0.76 1.27 BSC 0.20 6.35 0.66 0.13 16 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 11.18 7.24 8.00 NOTES 3 3 7 2 8 6 Rev. 1 2-20-95
e
PIN NO. 1 ID AREA
A
-A-
-B-
D
S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS
E E1 E2 E3 e k L Q S1 M N
0.050 BSC
BASE METAL b1 M M (b) SECTION A-A
(c)
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
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FN6475.2 March 23, 2009

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