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19-4570; Rev 0; 6/09
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
General Description
The MAX2078 octal-channel ultrasound front-end is a fully integrated bipolar, high-density octal-channel ultrasound receiver optimized for low cost, high-channel count, high-performance portable and cart-based ultrasound systems. The easy-to-use IC allows the user to achieve high-end 2D, PW, and CW Doppler (CWD) imaging capability using substantially less space and power. The highly compact imaging receiver lineup, including low-noise amplifier (LNA), variable-gain amplifier (VGA), and anti-alias filter (AAF), achieves an ultra-low 2.4dB noise figure at RS = RIN = 200 at a very low 64.8mW per channel power dissipation. The full imaging receiver channel has been optimized for second-harmonic imaging with -64dBFS second-harmonic distortion performance with a 1VP-P 5MHz output signal. The bipolar front-end has also been optimized for excellent low-velocity PW and color-flow Doppler sensitivity with an exceptional near-carrier SNR of 140dBc/Hz at 1kHz offset from a 5MHz 1VP-P output clutter signal. A fully integrated high-performance, programmable CWD beamformer is also included. Separate I/Q mixers for each channel are available for optimal CWD sensitivity in high-clutter environments, yielding an impressive near-carrier SNR of 154dBc/Hz at 1kHz offset from a 1.25MHz 200mVP-P input clutter signal. The MAX2078 octal-channel ultrasound front-end is available in a small 10mm x 10mm, 68-pin thin QFN package with an exposed pad and is specified over a 0C to +70C temperature range.
Features
o 8 Full Channels of LNA, VGA, AAF, and CWD Mixers in a Small, 10mm x 10mm TQFN Package o Pin Compatible with MAX2077 with LNA, VGA, and AAF in 10mm x 10mm TQFN Variant o Ultra-Low Full-Channel Noise Figure of 2.4dB at RIN = RS = 200 o Low Output-Referred Noise of 23nV/Hz at 5MHz, 20dB Gain, Yielding a Broadband SNR of 68dB** for Excellent Second-Harmonic Imaging o High Near-Carrier SNR of 140dBc/Hz at 1kHz Offset from a 5MHz, 1VP-P Output Signal, and 20dB of Gain for Excellent Low-Velocity PW and Color-Flow Doppler Sensitivity in a High-Clutter Environment o Ultra-Low-Power 64.8mW per Full-Channel (LNA, VGA, and AAF) Normal Imaging Mode (234mW per Channel in CWD Mode) o Selectable Active Input-Impedance Matching of 50, 100, 200, and 1k o Wide Input-Voltage Range of 330mVP-P in High LNA Gain Mode and 550mVP-P in Low LNA Gain Mode o Integrated Selectable 3-Pole 9MHz, 10MHz, 15MHz, and 18MHz Butterworth AAF o Fast-Recovery, Low-Power Modes (< 2s) o Fully Integrated, High Dynamic Range CWD Beamformer with Near-Carrier SNR of 154dBc/Hz at 1kHz Offset from a 1.25MHz, 200mVP-P Input Clutter Signal
**When coupled with the MAX1437B ADC.
MAX2078
Applications
VCC2 VCC1 INC1 ZF2 ZF1 IN1 CI+ CI-
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 IN2 1 2 3 4 5 6 7 8 9 OUT1+ 51 OUT150 OUT2+ 49 OUT248 OUT3+ 47 OUT346 OUT4+ 45 OUT444 VCC1 43 LO+ 42 LO41 OUT5+ 40 OUT539 OUT6+ 38 OUT637 OUT7+ *EP 36 OUT735 OUT8+ 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 INC7 ZF8 OUT8INC8 VCC2 VCC1 DOUT VCC2 VREF VG+ VGGND CLP PD GND IN7 IN8 VCC2
CQ+
Sonar
+
Ordering Information
PART MAX2078CTK+ TEMP RANGE 0C to +70C PIN-PACKAGE 68 Thin QFN-EP*
INC2 ZF3 IN3 INC3 ZF4 IN4 INC4 GND
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
MAX2078
AG 10 ZF5 11 IN5 12 INC5 13 ZF6 14 IN6 15 INC6 16 ZF7 17
THIN QFN
*EP = EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
CLK
CQ-
V/C
DIN
NP
CS
Medical Ultrasound Imaging
TOP VIEW
1
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
ABSOLUTE MAXIMUM RATINGS
VCC_ to GND .........................................................-0.3V to +5.5V VCC2 - VCC1 .....................................................................> -0.3V CI_, CQ_ to GND ....................................................-0.3V to +13V ZF_, IN_, AG to GND ..................................-0.3V to (VCC + 0.3V) INC_ ..............................................................................20mA DC VREF to GND.............................................................-0.3V to +3V IN_ to AG ...............................................................-0.6V to +0.6V OUT_, LO_, DIN, DOUT, VG_, NP, CS, CLK, PD, CLP, V/C to GND .....................................-0.3V to VCC1 + 0.3V CI_, CQ_, VCC_, VREF analog and digital control signals must Note 1A: Note 1B: be applied in this order Input Differential Voltage ................................2.0VP-P differential Continuous Power Dissipation (TA = +70C) 68-Pin TQFN (derated 40mW/C above +70C) ..................4W Operating Temperature Range (Note 1A) ..............0C to +70C Junction Temperature ......................................................+150C JC (Note 1B, 1C) .........................................................+0.3C/W JA (Note 1C, 1D) ..........................................................+20C/W Storage Temperature Range .............................-40C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1C: Note 1D:
TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB. Junction temperature TJ = TC + (JC x VCC x ICC). This formula can only be used if the component is soldered down to a printed circuit board pad containing multiple ground vias to remove the heat. The junction temperature must not exceed 150C. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Junction temperature TJ = TA + (JA x VCC x ICC), assuming there is no heat removal from the exposed pad. The junction temperature must not exceed 150C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER 3.3V Supply Voltage 4.75V/5V Supply Voltage External Reference Voltage Range CMOS Input High Voltage CMOS Input Low Voltage CMOS Input Leakage Current DATA Output High Voltage DATA Output Low Voltage SYMBOL VCC1 VCC2 VREF VIH VIL IIN DOUT_HI DOUT_LO (Note 3) Applies to CMOS control inputs Applies to CMOS control inputs TA = +25oC, applies to CMOS control inputs; input current = 0V, output current = 3.47V 10M load 10M load VCC1 0 CONDITIONS MIN 3.13 4.5 2.475 2.5 0.8 10 TYP 3.3 4.75 MAX 3.47 5.25 2.525 UNITS V V V V V A V V
DC ELECTRICAL CHARACTERISTICS--VGA MODE
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, V/C = 1, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER 4.75V/5V Supply Standby Current 3V Supply Standby Current 4.75V/5V Power-Down Current 3V Power-Down Current 3V Supply Current per Channel 4.75V/5V Supply Current per Channel DC Power per Channel SYMBOL I_NP_5V_TOT I_NP_3V_TOT I_PD_5V_TOT I_PD_3V_TOT I_3V_NM I_5V_NM P_NM CONDITIONS NP = 1, all channels NP = 1, all channels PD = 1, all channels PD = VCC1, all channels Total I divided by 8, VG+ - VG1 = -2V Total I divided by 8 MIN TYP 3.9 1.7 0.4 0.3 11 6.0 64.8 MAX 6 3 10 10 16 8.3 92.3 UNITS mA mA A A mA mA mW
2
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
DC ELECTRICAL CHARACTERISTICS--VGA MODE (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, V/C = 1, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Differential Analog Control Voltage Range Common-Mode Voltage for Difference Analog Control Source/Sink Current for Gain Control Pins Reference Voltage Input Reference Current Output Common-Mode Level SYMBOL VGAIN_RANG VGAIN_COMM I_ACONTROL VREF IREF VCMO All channels VG+ - VG(VG+ + VG-)/2 Per pin 2.475 9.7 1.73 CONDITIONS MIN TYP 3 1.65 5% 1.6 2.3 2.525 13 MAX UNITS V V A V A V
MAX2078
DC ELECTRICAL CHARACTERISTICS--CW MODE
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, CLP = 0, V/C = 0, no RF signals applied. CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Reference Current Mixer LVDS LO Input Common-Mode Voltage LVDS LO Differential Input Voltage LVDS LO Input Common-Mode Current LVDS LO Differential Input Resistance POWER-DOWN MODE 4.75V/5V Supply Current per Channel 3.3V Supply Current per Channel LOW-POWER MODE 4.75V/5V Supply Current per Channel 3.3V Supply Current per Channel 11V Supply Current per Channel On-Chip Power Dissipation (All 8 Channels) NORMAL POWER MODE 4.75V/5V Supply Current per Channel 3.3V Supply Current per Channel 11V Supply Current per Channel On-Chip Power Dissipation (All 8 Channels) I_C_5V_L I_C_3_3V_L I_C_11V_L PDIS_FP_TOT_L (Note 6) 31 0.4 11.3 1.87 34 0.95 13 2.2 mA mA mA W I_C_5V_N I_C_3_3V_N I_C_11V_N PDIS_FP_TOT_N CLP = 1 CLP = 1 CLP = 1 CLP = 1 27 0.4 6.8 1.44 30 0.95 8.4 1.7 mA mA mA W I_C_5V_P I_C_3_3V_P PD = 1 PD = 1 0.6 0.1 10 10 A A SYMBOL IREF V_LVDS_CM V_LVDS_DM I_LVDS_CM R_DM_LVDS LO+ and LOCommon-mode input voltage = 1.25V (Note 4) Current out of each pin, V_LVDS_CM = 1.25V (Note 5) 4 200 CONDITIONS MIN TYP 82.7 1.25 0.2 700 130 MAX UNITS A V mVP-P A k
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3
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB, D45/D44=1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Mode Select Response Time (Note 7) High Gain Maximum InputVoltage Range CONDITIONS V/C stepped from 0 to 1, DC stable within 10% V/C stepped from 1 to 0, DC stable within 10% High LNA gain D43/D42/D41/D40 = 1/0/1/0 MIN TYP 1 1 0.33 0.6 MAX UNITS s VP-P differential VP-P differential
Low Gain Maximum Input-Voltage Low LNA gain D43/D42/D41/D40 = 0/0/0/1 Range
AC ELECTRICAL CHARACTERISTICS--VGA MODE
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS D42/D41/D40 = 0/0/0, RIN = 50 Input Impedance D42/D41/D40 = 0/0/1, RIN = 100 D42/D41/D40 = 0/1/0, RIN = 200 D42/D41/D40 = 0/1/1, RIN = 1000, fRF = 2MHz RS = RIN = 50, VG+ - VG- = +3V Noise Figure RS = RIN =100, VG+ - VG- = +3V RS = RIN = 200, VG+ - VG- = +3V RS = RIN = 1000, VG+ - VG- = +3V Low-Gain Noise Figure Input-Referred Noise Voltage Input-Referred Noise Current Maximum Gain, High Gain Setting Minimum Gain, High Gain Setting Maximum Gain, Low Gain Setting Minimum Gain, Low Gain Setting Anti-Aliasing Filter 3dB Corner Frequency Gain Range D43/D42/D41/D40 = 0/0/0/1, LNA gain = 12.5dB, RS = RIN = 200, VG+ - VG- = +3V D43/D42/D41/D40 = 1/1/1/0 D43/D42/D41/D40 = 1/1/1/0 VG+ - VG- = +3V VG+ - VG- = -3V D43/D42/D41/D40 = 0/0/0/1, VG+ - VG- = +3V D43/D42/D41/D40 = 0/0/0/1, VG+ - VG- = -3V D45/D44 = 0/0, fC = 9MHz D45/D44 = 0/1, fC = 10MHz D45/D44 = 1/0, fC = 15MHz D45/D44 = 1/1, fC = 18MHz VG+ - VG- = -3V to +3V 41 8.5 35 2.5 MIN 47.5 90 185 700 TYP 50 100 200 830 4.5 3.4 2.4 2.1 3.9 0.9 2.1 42.8 10 36.8 4 9 10 15 18 33 dB MHz 45 11 38 6 dB nV/Hz pA/Hz dB dB dB dB dB MAX 60 110 210 1000 UNITS
4
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
AC ELECTRICAL CHARACTERISTICS--VGA MODE (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Absolute Gain Error CONDITIONS Measured at TA = +25oC, VG+ - VG- = -2V Measured at TA = +25oC, VG+ - VG- = 0V Measured at TA = +25oC, VG+ - VG- = +2V VG+ - VG- = -3V (VGA minimum gain), gain ratio with 330mVP-P/50mVP-P input tones LNA low gain = 12.5dB, VG+ - VG- = -3V (VGA minimum gain), gain ratio with 600mVP-P/50mVP-P Gain step up (VIN = 5mVP-P, gain changed from 10dB to 44dB, settling time is measured within 1dB final value) VGA Gain Response Time Gain step down (VIN = 5mVP-P, gain changed from 44dB to 10dB, settling time is measured within 1dB final value) VGA Output Offset Under Pulsed Overload Small-Signal Output Noise Large-Signal Output Noise Second Harmonic (HD2) High-Gain IM3 Distortion Overdrive is 10mA in clamping diodes, gain at 30dB, 16 pulses at 5MHz, repetition rate 20kHz; offset is measured at output when RF duty cycle is off 20dB of gain, VG+ - VG- = -0.85, no input signal 20dB of gain, VG+ - VG- = -0.85, fRF = 5MHz, fNOISE = fRF + 1kHz, VOUT = 1VP-P differential VIN = 50mVP-P, fRF = 2MHz, VOUT = 1VP-P VIN = 50mVP-P, fRF = 5MHz, VOUT = 1VP-P VIN = 50mVP-P, fRF1 = 5MHz, fRF2 = 5.01MHz, VOUT = 1VP-P (Note 8) D43/D42/D41/D40 = 0/0/0/1 (RIN = 200, LNA gain = 12.5dB),VIN = 100mVP-P, fRF1 = 5MHz, fRF2 = 5.01MHz, VOUT = 1VP-P (Note 8) Gain set for 26dB fRF = 5MHz, VOUT = 1VP-P, settled with in 1dB from transition on NP pin To reach DC current target 10% Gain set for 28dB, fRF = 5MHz, VOUT = 1VP-P, settled within 1dB from transition on PD Gain set for 28dB, fRF = 5MHz, DC power reaches 6mW/channel, from transition on PD VOUT = 1VP-P differential, fRF = 10MHz, 28dB of gain VOUT = 1VP-P differential, fRF = 10MHz, 28dB of gain Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 10MHz -52 1.6 MIN TYP 0.4 0.4 0.4 1.4 dB 0.8 1.4 s dB MAX UNITS
MAX2078
Input Gain Compression
180 23 35 -67 -64.2 -61
mV nV/Hz nV/Hz dBc dBc
Low-Gain IM3 Distortion Standby Mode Power-Up Response Time Standby Mode Power-Down Response Time Power-Up Response Time Power-Down Response Time Adjacent Channel Crosstalk Nonadjacent Channel Crosstalk Phase Matching Between Channels
-50
-60
dBc
2.1 2.0 2.7 5 -58 -71 1.2
s s ms ns dBc dBc Degrees
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
AC ELECTRICAL CHARACTERISTICS--VGA MODE (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER 3V Supply Modulation Ratio CONDITIONS Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 5MHz, fMOD = 1kHz, VMOD = 50mVP-P, ratio of output sideband at 5.001MHz, 1VP-P Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 5MHz, fMOD = 1kHz, VMOD = 50mVP-P, ratio of output sideband at 5.001MHz, 1VP-P Gain = 28dB, VG+ - VG- = 0.4V, fMOD = 5MHz, VMOD = 50mVP-P, VOUT = 1.0VP-P VG+ - VG- = -3V, delay between VIN = 300mVP-P and VIN = 30mVP-P differential Differential MIN TYP -73 MAX UNITS dBc
4.75V/5V Supply Modulation Ratio Gain Control Lines CommonMode Rejection Ratio Overdrive Phase Delay Output Impedance
-82
dBc
-74 5 100
dBc ns
AC ELECTRICAL CHARACTERISTICS--CW MODE
(Typical Application Circuit, V/C = 0, PD = 0, NP = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), fRF = fLO/16 = 5MHz, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz (Note 9). Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER CW DOPPLER MIXER Mixer RF Frequency Range LO Frequency Range Mixer Output Frequency Range FULL-POWER MODE Noise Figure Noise Figure at 100mVP-P Input Noise Figure at 200mVP-P Input SNR at 100mVP-P Input SNR at 200mVP-P Input No carrier 100mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 200mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 100mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 200mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 3.4 3.6 4.1 -148.3 -153.8 dB dB dB dBc/Hz dBc/Hz LO+ and LO0.9 16 DC 7.6 120 100 MHz MHz kHz CONDITIONS MIN TYP MAX UNITS
6
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
AC ELECTRICAL CHARACTERISTICS--CW MODE (continued)
(Typical Application Circuit, V/C = 0, PD = 0, NP = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), fRF = fLO/16 = 5MHz, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz (Note 9). Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Two-Tone Intermodulation IMD3 at 100mV Two-Tone Intermodulation IMD3 at 200mV Mixer Output-Voltage Compliance Channel-to-Channel Phase Matching Channel-to-Channel Gain Matching CONDITIONS fRF1 = 5MHz, 0.1VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) fRF1 = 5MHz, 0.2VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) Valid voltage range (AC + DC) on summed mixer output pins Measured under zero beat conditions, VRF = 100mVP-P, fRF = 5MHz, fLO = 80MHz (Note 10) Measured under zero beat conditions, VRF = 100mVP-P, fRF = 5MHz, fLO = 80MHz (Notes 10, 11) Calculated from LNA input voltage and twice the I or Q current fRF = 0.9MHz, fLO/16 = 1MHz fRF = 7.6MHz, fLO/16 = 7.5MHz 19 19 4.5 0.4 0.2 23 22.5 26 mS 26 MIN -50 TYP -55 -48.5 12 MAX UNITS dBc dBc V Degrees dB
MAX2078
Transconductance
LOW-POWER MODE (CLP = 1) Noise Figure Noise Figure at 100mVP-P Input Noise Figure at 200mVP-P Input SNR at 100mVP-P Input SNR at 200mVP-P Input Two-Tone Intermodulation IMD3 Mixer Output-Voltage Compliance No carrier 100mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 200mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 100mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 200mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset fRF1 = 5MHz, 0.1VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) Valid voltage range on summed mixer output pins (Note 12) Calculated from LNA input voltage and twice the I or Q current fRF = 1.1MHz, fLO/16 = 1MHz fRF = 7.6MHz, fLO/16 = 7.5MHz 4.5 19 19 21.5 21.5 3.2 3.5 4.3 -148.2 -153.6 -44 12 26 mS 26 dB dB dB dBc/Hz dBc/Hz dBc V
Transconductance (Note 13)
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7
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
AC ELECTRICAL CHARACTERISTICS--SERIAL PERIPHERAL INTERFACE
(DOUT loaded with 60pF and 10M, 2ns rise and fall edges on CLK.)
PARAMETER Clock Speed Mininimum Data-to-Clock Setup Time Mininimum Data-to-Clock Hold Time Mininimum Clock-to-CS Setup Time CS Positive Mininimum Pulse Width Mininimum Clock Pulse Width Mininimum CS High to Mixer Clock on tCS tCH tES tEW tCW tMIXCS 5 0 5 1 2 2 SYMBOL CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns
Note 2: Note 3: Note 4:
Note 5: Note 6: Note 7:
Note 8: Note 9: Note 10:
Note 11:
Note 12: Note 13:
Minimum and maximum limits at TA = +25C and +70C are guaranteed by design, characterization, and/or production test. Noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF. Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the input impedance of the pin causes a period of time (related to the RC time constant) when the DC level on the chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not excede both of the logic thresholds required for proper operation. This problem associated with AC-coupling causes an inability to ensure synchronization among beamforming channels. The LVDS signal is terminated differentially with an external 100 resistor on the board. An external 100 resistor terminates the LVDS differential signal path. Total on-chip power dissipation is calculated as PDISS = VCC1 x ICC1 + VCC2 x ICC2 + VREF x IREF + [11V - (I11V/4) x 162] x I11V. This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time may be excessive and a switching network is recommended, as shown in the Applications Information section. See the Ultrasound-Specific IMD3 Specification section. The reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8 channels. If more channels are used, the reference noise must be reduced to get the best noise performance. Channel-to-channel gain and phase matching measured on 30 pieces during engineering characterization at room temperature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the phase variation. Voltage gain is measured by subtracting the output-voltage signal from the input-voltage signal. The output-voltage signal is obtained by taking the differential CW I output and summing it in quadrature with the differential CW Q output. The input voltage is defined as the differential voltage applied to the CW input pins. Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs. Transconductance is defined as the quadrature-combined CW differential output current at baseband divided by the mixer's input voltage.
8
_______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Typical Operating Characteristics
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25C, unless otherwise noted.)
GAIN vs. DIFFERENTIAL ANALOG CONTROL VOLTAGE
MAX2078 toc01
MAX2078
COMPLEX INPUT IMPEDANCE MAGNITUDE vs. FREQUENCY
MAX2078 toc02
GAIN ERROR HISTOGRAM
GAIN = 20dB
MAX2078 toc03
45
1000
25
INPUT IMPEDANCE ()
35 GAIN (dB)
800
1k
20
25
% UNITS 50 100 200
600
15
400
10
15 200
5
5 -3 -2 -1 0 1 2 3 CONTROL VOLTAGE (V)
0 0 5 10 FREQUENCY (MHz) 15 20
0 -0.175 0.025 0.075 0.225 -0.125 -0.075 -0.025 0.275 44
MAX2078 toc06
0.125
GAIN ERROR (dB)
OUTPUT-REFERRED NOISE vs. GAIN
MAX2078 toc04
INPUT-REFERRED NOISE vs. GAIN
MAX2078 toc05
SECOND-HARMONIC DISTORTION vs. GAIN
-30 VOUT = 1VP-P -40 fRF = 10MHz -50 HD2 (dBc)
180 150 NOISE (nV/Hz) 120 90 60 30 0 8 17 26 GAIN (dB) 35
6
5 NOISE (nV/Hz)
4
-60 -70 fRF = 5MHz
3
2
-80 fRF = 2MHz -90 8 17 26 GAIN (dB) 35 44 20 26 32 GAIN (dB) 38
1 44
_______________________________________________________________________________________
0.175
9
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Typical Operating Characteristics (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25C, unless otherwise noted.)
THIRD-HARMONIC DISTORTION vs. GAIN
MAX2078 toc07
TWO-TONE ULTRASOUND-SPECIFIC IMD3 vs. GAIN
MAX2078 toc08
SECOND- AND THIRD-HARMONIC DISTORTION vs. VOUT_P-P
GAIN = 26dB fRF = 5MHz HD2
MAX2078 toc09
-30 VOUT = 1VP-P -40 -50 HD3 (dBc) -60 -70 fRF = 5MHz fRF = 10MHz
-10 VOUT = 1VP-P -30 fRF = 10MHz IMD3 (dBc) -50 fRF = 5MHz -70
-50
-60 HD2 and HD3 (dBc)
-70
-80 fRF = 2MHz
HD3
-80 fRF = 2MHz -90 20 26 32 GAIN (dB) 38 44 -90 20 26 32 GAIN (dB) 38 44 -90 0 0.2 0.4 0.6 0.8 1.0 VOUT_P-P (V)
SECOND- AND THIRD-HARMONIC DISTORTION vs. FREQUENCY
MAX2078 toc10
SECOND- AND THIRD-HARMONIC DISTORTION vs. DIFFERENTIAL OUTPUT RESISTANCE
MAX2078 toc11
SECOND- AND THIRD-HARMONIC DISTORTION vs. DIFFERENTIAL OUTPUT LOAD CAPACITANCE
VOUT = 1VP-P GAIN = 26dB fRF = 5MHz
MAX2078 toc12
-30
VOUT = 1VP-P GAIN = 26dB HD2
-30 -40 HD2 AND HD3 (dBc) -50 -60 -70
-40 HD2 AND HD3 (dBc)
VOUT = 1VP-P GAIN = 26dB fRF = 5MHz
-30 -40 HD2 AND DH3 (dBc) -50 -60 -70
-50
HD2
HD2
-60
-70 HD3 -80 0 5 10 FREQUENCY (MHz) 15 20
HD3 -80 -90 200 300 400 500 600 700 800 900 1000 RESISTANCE () -80 -90 0 20 40
HD3
60
80
100
CAPACITANCE (pF)
10
______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Typical Operating Characteristics (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25C, unless otherwise noted.)
TWO-TONE ULTRASOUND-SPECIFIC IMD3 vs. FREQUENCY
MAX2078 toc13
MAX2078
ADJACENT CHANNEL-TO-CHANNEL CROSSTALK vs. GAIN
MAX2078 toc14
ADJACENT CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY
VOUT = 1VP-P GAIN = 20dB
MAX2078 toc15
0
VOUT = 1VP-P GAIN = 26dB
-50
VOUT = 1VP-P fRF = 10MHz ADJACENT CHANNEL 1
0
-20 CROSSTALK (dBc) IMD3 (dBc)
-55
CROSSTALK (dBc)
-30 ADJACENT CHANNEL 1 -60 ADJACENT CHANNEL 2
-40
-60
-60
-65
ADJACENT CHANNEL 2
-80 0 5 10 FREQUENCY (MHz) 15 20
-70 8 17 26 GAIN (dB) 35 44
-90 1 10 FREQUENCY (MHz) 100
LARGE-SIGNAL BANDWIDTH vs. FREQUENCY
MAX2078 toc16
COMMON-MODE OUTPUT VOLTAGE vs. GAIN
COMMON-MODE OUTPUT VOLTAGE (V)
MAX2078 toc17
DIFFERENTIAL OUTPUT IMPEDANCE vs. FREQUENCY
180
MAX2078 toc18
30
VOUT = 1VP-P GAIN = 20dB 15MHz 18MHz 9MHz
1.9
80
REAL COMPONENT ()
1.8
60 120 REAL 40 60 IMAGINARY 20
GAIN (dB)
10
1.7
0 10MHz -10
1.6
-20 1 10 FREQUENCY (MHz) 100
1.5 8 17 26 GAIN (dB) 35 44
0 0 10 20 30 40 50 FREQUENCY (MHz)
0
______________________________________________________________________________________
11
IMAGINARY COMPONENT ()
20
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Typical Operating Characteristics (continued)
(Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0C to +70C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1k differential, RS = 200, CI_, CQ_ pulled up to 11V through four separate 0.1% 162 resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/Hz from 1kHz to 20MHz, DOUT loaded with 10M and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25C, unless otherwise noted.)
LNA OVERLOAD RECOVERY TIME (VIN = 500mVP-P for 1s TO 100mVP-P for 1s AND BACK TO 500mVP-P for 1s, GAIN = 10dB)
1.25 INPUT 0.75 OUTPUT (V) 0 OUTPUT (V) INPUT (V) 2
MAX2078 toc19
VGA OVERLOAD RECOVERY TIME (VIN = 40mVP-P for 1s TO 4mVP-P for 1s AND BACK TO 40mVP-P for 1s, GAIN = 42.5dB)
3 INPUT 36 0 PHASE DELAY (ns) INPUT (V) 27
MAX2078 toc20
OVERDRIVE PHASE DELAY vs. FREQUENCY
INPUT = 300mVP-P
MAX2078 toc21
0.5
0.05
45
1 -0.05 0 -0.10 OUTPUT
0.25
-0.5
18 INPUT = 30mVP-P 9 GAIN = 10dB
-0.25 OUTPUT -0.75 0 500 1000 TIME (ns) 1500
-1.0
-1
-1.5 2000
-2 0 500 1000 TIME (ns) 1500
-0.15 2000
0 0 5 10 FREQUENCY (MHz) 15 20
GROUP DELAY vs. FREQUENCY
MAX2078 toc22
CW IMD3 vs. FREQUENCY
MAX2078 toc23
INPUT-REFERRED NOISE vs. INPUT CLUTTER VOLTAGE
fCLUTTER = 1.25MHz OFFSET = 1kHz
MAX2078 toc24
45
-48 VIN = 100mVP-P -52
1.48
1.44 NOISE (nV/Hz)
GROUP DELAY (ns)
CW IMD3 (dBc)
35 GAIN = 30dB 25 GAIN = 40dB
1.40 NORMAL POWER MODE 1.36
-56
-60 GAIN = 20dB GAIN = 10dB 15 0 5 10 FREQUENCY (MHz) 15 20 -64 0 2 4 FREQUENCY (MHz) 6 8
1.32
LOW-POWER MODE
1.28 0 50 100 150 200 INPUT CLUTTER VOLTAGE (mVP-P)
12
______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Pin Description
PIN 1 2 3 4 5 6 7 8 9, 28, 31 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 33, 53, 64 24 NAME IN2 INC2 ZF3 IN3 INC3 ZF4 IN4 INC4 GND AG ZF5 IN5 INC5 ZF6 IN6 INC6 ZF7 IN7 INC7 ZF8 IN8 INC8 VCC2 Channel 2 Input Channel 2 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. Channel 3 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 3 Input Channel 3 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. Channel 4 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 4 Input Channel 4 Clamp Input. Connect to the input coupling capacitor. See the Typical Application Circuit for details. Ground AC Ground. Connect a low-ESR 1F capacitor to ground. Channel 5 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 5 Input Channel 5 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. Channel 6 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 6 Input Channel 6 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. Channel 7 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 7 Input Channel 7 Clamp Input. Connect to the input coupling capacitor. See the Typical Application Circuit for details. Channel 8 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 8 Input Channel 8 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 4.75V Power Supply. Connect to an external 4.75V power supply. Connect all 4.75V supply pins together externally and bypass with 100nF capacitors as close as possible to the pin. External 2.5V Reference Supply. Connect to a low-noise power supply. Bypass to GND with a 0.1F capacitor as close as possible to the pins. Note that noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF. 3.3V Power Supply. Connect to an external 3V power supply. Connect all 3.3V supply pins together externally and bypass with 100nF capacitors as close as possible to the pin. VGA Analog Gain Control Differential Input. Set the differential voltage to -3V for maximum gain and to +3V for minimum gain. CW Low-Power Mode Select Input. Drive CLP high to place CW mixers in low-power mode. Power-Down Mode Select Input. Set PD to VCC1 to place the entire device in power-down mode. Drive PD low for normal operation. This mode overrides the standby mode. Serial Port Data Output. Data output for ease of daisy-chain programming. The level is 3.3V CMOS. Channel 8 Negative Differential Output Channel 8 Positive Differential Output Channel 7 Negative Differential Output FUNCTION
MAX2078
VREF
25, 44, 63 26 27 29 30 32 34 35 36
VCC1 VG+ VGCLP PD DOUT OUT8OUT8+ OUT7-
______________________________________________________________________________________
13
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Pin Description (continued)
PIN 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 54 55 56 57 58 59 60 61 62 65 66 67 68 -- NAME OUT7+ OUT6OUT6+ OUT5OUT5+ LOLO+ OUT4OUT4+ OUT3OUT3+ OUT2OUT2+ OUT1OUT1+ CLK DIN CS NP V/C CQCQ+ CICI+ ZF1 IN1 INC1 ZF2 EP Channel 7 Positive Differential Output Channel 6 Negative Differential Output Channel 6 Positive Differential Output Channel 5 Negative Differential Output Channel 5 Positive Differential Output Differential Local Oscillator Input. LO is divided in the beamformer. Channel 4 Negative Differential Output Channel 4 Positive Differential Output Channel 3 Negative Differential Output Channel 3 Positive Differential Output Channel 2 Negative Differential Output Channel 2 Positive Differential Output Channel 1 Negative Differential Output Channel 1 Positive Differential Output Serial Port Clock Input (Positive Edge Triggered). 3.3V CMOS. Clock input for programming the serial shift registers. Serial Port Data Input. 3.3V CMOS. Data input to program the serial shift registers. Serial Port Chip Select Input. 3.3V CMOS. Used to store programming bits in registers, as well as in CW mode, synchronizing all channel phases (on a rising edge). VGA Standby Mode Select Input. Set NP to 1 to place the entire device in standby mode. Overrides soft channel shutdown in serial shift register, but not general power-down (PD). VGA/CW Mode Select Input. Set V/C to a logic-high to enable the VGAs and disable CW mode. Set V/C to a logic-low to enable the CW mixers and disable the VGA mode. 8-Channel CW Negative Quadrature Output. Connect to an external 11V power supply with a 162 external pullup resistor. 8-Channel CW Positive Quadrature Output. Connect to an external 11V power supply with a 162 external pullup resistor. 8-Channel CW Negative In-Phase Output. Connect to an external 11V power supply with a 162 external pullup resistor. 8-Channel CW Positive In-Phase Output. Connect to an external 11V power supply with a 162 external pullup resistor. Channel 1 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Channel 1 Positive Differential Input Channel 1 Clamp Input. Connect to the input coupling capacitor. Channel 2 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. Exposed Pad. Internally connected to ground. Connect to a large ground plane using multiple vias to maximize thermal and electrical performance. Not intended as an electrical connection point. FUNCTION
14
______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Block Diagram
MAX2078
CQMAX2078 VCC1 VCC2 ZF1 CQ+ CICI+ V/C NP CS DIN CLK VCC2 OUT1+ OUT1LNA VGA ANTI-ALIAS
IN1 INC1
ZF2
IN2 INC2 LNA VGA ANTI-ALIAS
OUT2+ OUT2-
ZF3
IN3 INC3 LNA VGA ANTI-ALIAS
OUT3+ OUT3-
ZF4
IN4 INC4 LNA GND VGA ANTI-ALIAS
OUT4+ OUT4-
VCC1 LO+ LO-
ZF5 AG IN5 INC5 LNA VGA ANTI-ALIAS OUT5+ OUT5-
ZF6
IN6 INC6 LNA VGA ANTI-ALIAS
OUT6+ OUT6-
ZF7
IN7 INC7 LNA VGA ANTI-ALIAS
OUT7+ OUT7-
ZF8
IN8 INC8 LNA VGA ANTI-ALIAS
OUT8+ OUT8-
______________________________________________________________________________________
15
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Detailed Description
The MAX2078 is a high-density, octal-channel ultrasound receiver optimized for low cost, high-channel count, high-performance portable and cart-based ultrasound applications. The integrated octal LNA, VGA, AAF, and programmable CWD beamformer offer a complete multi-specialty, ultrasound receiver solution. Imaging path dynamic range has been optimized for exceptional second-harmonic performance. The complete imaging receive channel exhibits an exceptional 68dBFS** SNR at 5MHz. The bipolar front-end has also been optimized for exceptionally low near-carrier modulation noise for exceptional low-velocity pulsed and color-flow Doppler sensitivity under high-clutter conditions, achieving an impressive near-carrier SNR of 140dBc/Hz at 1kHz offset from a VOUT = 1VP-P, 5MHz clutter signal.
**When coupled with the MAX1437B ADC.
The MAX2078 also integrates an octal quadrature mixer array and programmable LO phase generators for a complete continuous-wave Doppler (CWD) beamforming solution. Separate mixers for each channel are available for optimal CWD sensitivity, yielding an impressive SNR of 154dBc/Hz at 1kHz offset from a 200mVP-P, 1.25MHz input signal. The LO phase selection for each channel is programmed using a digital serial interface and a single high-frequency clock. The serial interface is designed to allow multiple devices to be easily daisy-chained to minimize program interface wiring. The outputs of the mixers are summed into single I and Q differential current outputs.
Modes of Operation
The MAX2078 requires programming before it can be used. The operating modes are controlled by 48 programming bits. Tables 1 and 2 show the functions of these programming bits.
Table 1. Summary of Programming Bits
BIT NAME D40, D41, D42 D43 D44, D45 D46 D0-D39 Input impedance programming LNA gain (D43 = 0 is low gain) Anti-alias filter fC programming Don't care Beamformer programming, from channel 1 to 8 DESCRIPTION
Table 2. Logic Functions of Programming Bits
D46 X X X X X X X X X X X X X D45 X X X X X X X X X 0 0 1 1 D44 X X X X X X X X X 0 1 0 1 D43 1 1 1 1 0 0 0 0 1 X X X X D42 0 0 0 0 0 0 0 0 1 X X X X D41 0 0 1 1 0 0 1 1 X X X X X D40 0 1 0 1 0 1 0 1 X X X X X MODE RIN = 50, LNA gain = 18.5dB RIN = 100 RIN = 200 RIN = 1000 RIN = 100, LNA gain = 12.5dB RIN = 200 RIN = 400 RIN = 2000 Open feedback fC = 9MHz fC = 10MHz fC = 15MHz fC = 18MHz
X = Don't care.
16
______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Low-Noise Amplifier (LNA)
The MAX2078's LNA is optimized for excellent dynamic range and linearity performance characteristics, making it ideal for ultrasound imaging applications. When the LNA is placed in low-gain mode, the input resistance (RIN), being a function of the gain A (RIN = RF/(1+A)), increases by a factor of approximately 2. Consequently, the switches that control the feedback resistance (RF) have to be changed. For instance, the 100 mode in high gain becomes the 200 mode in low gain (see Table 2).
Overload Recovery
The device is also optimized for quick overload recovery for operation under the large input signal conditions that are typically found in ultrasound input buffer imaging applications. See the Typical Operating Characteristics for an illustration of the rapid recovery time from a transmit-related overload.
MAX2078
Octal Continuous-Wave (CW) Mixer
The MAX2078 CW mixers are designed using an active double-balanced topology. The mixers achieve high dynamic range and high linearity performance, with exceptionally low thermal and jitter noise, ideal for ultrasound CWD signal reception. The octal quadrature mixer array provides noise performance of 154dBc/Hz at 1kHz offset from a 1.25MHz, 200mVP-P input clutter signal and a two-tone third-order ultrasound-specific intermodulation product of -48.5dBc (typ). See the Ultrasound-Specific IMD3 Specification section. The octal array exhibits quadrature and in-phase differential current outputs (CQ+, CQ-, CI+, CI-) to produce the total CWD beamformed signal. The maximum differential current output is typically 3mAP-P and the mixeroutput compliance voltage ranges from 4.5V to 12V.
Variable-Gain Amplifier (VGA)
The MAX2078's VGAs are optimized for high linearity, high dynamic range, and low output-noise performance, all of which are critical parameters for ultrasound imaging applications. Each VGA path includes circuitry for adjusting analog gain, as well as an output buffer with differential output ports (OUT_+, OUT_-) for driving ADCs. See the High-Level CW Mixer and Programmable Beamformer Functional Diagram for details. The VGA gain can be adjusted through the differential gain control input VG+ and VG-. Set the differential gain control input voltage at -3V for minimum gain and +3V for maximum gain. The differential analog control commonmode voltage is 1.65V (typ).
High-Level CW Mixer and Programmable Beamformer Functional Diagram
CW_IN8 CW_IN7 CW_IN6 CW_IN5 CW_IN4 CW_IN3 CW_IN2 CW_IN1 CW_IOUT CW_QOUT MAX2078
I
Q
I
Q
I
Q
I
Q
I
Q
I
Q
I
Q
I
Q
LO+ LO-
CHANNEL 1 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 2 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 3 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 4 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 5 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 6 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 7 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
CHANNEL 8 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR
DATA_IN CLK CS
DATA OUT
CLP
PD
______________________________________________________________________________________
17
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Each mixer can be programmed to 1 of 16 phases; therefore, 4 bits are required for each channel for programming. Each CW channel can be programmed to an off state by setting bit Di to 1. The power-down mode (PD) line overrides this soft shutdown. After the serial shift registers have been programmed, the CS signal, when going high, loads the phase information in the form of 5 bits per channel into the I/Q phase divider/selectors. This presets the dividers, selecting the appropriate mixer phasing. See Table 3 for mixer phase configurations.
MAX2078
differential quadrature (Q) outputs and eight differential in-phase (I) outputs. All quadrature and in-phase outputs are summed into single I and Q differential current outputs (CQ+, CQ-, CI+, CI-).
LO Phase Select
The LO phase dividers can be programmed through the shift registers to allow for 16 quadrature phases for a complete CW beamforming solution.
Synchronization
Figure 1 illustrates the serial programming of the eight individual channels through the serial data port. Note that the serial data can be daisy-chained from one part to another, allowing a single data line to be used to program multiple chips in the system.
CW Mixer Output Summation
The outputs from the octal-channel mixer array are summed internally to produce the total CWD summed beamformed signal. The octal array produces eight
Table 3. Mixer Phase Configurations
PER CHANNEL PHASE (DEGREE) 0 22.5 45 67.5 90 112.5 135 157.5 180 202.5 225 247.5 270 292.5 315 337.5 MSB Di + 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Di + 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DIN CLK
Di + 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
LSB Di + 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SHUTDOWN Di 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
D46
D45
D44
D43
D42
D41
D40
CHANNEL 1 A B C D SD B4 B3 B2 B1 B0
CHANNEL 2 A B C D SD B4 B3 B2 B1 B0
CHANNEL 3 A B C D SD B4 B3 B2 B1 B0
CHANNEL 4 A B C D SD B4 B3 B2 B1 B0
CHANNEL 5 A B C D SD B4 B3 B2 B1 B0
CHANNEL 6 A B C D SD B4 B3 B2 B1 B0
CHANNEL 7 A B C D SD B4 B3 B2 B1 B0
CHANNEL 8 A B C D SD B4 B3 B2 B1 B0 DOUT
Figure 1. Data Flow of Serial Shift Register
18 ______________________________________________________________________________________
Octal-Channel Ultrasound Front-End with CW Doppler Mixers
VGA and CW Mixer Operation
During normal operation, the MAX2078 is configured so that either the VGA path is enabled while the mixer array is powered down (VGA mode), or the quadrature mixer array is enabled while the VGA path is powered down (CW mode). For VGA mode, set V/C to a logichigh and for CW mode, set V/C to a logic-low.
162 162 1F CI50 31.6k 0.022F 31.6k CI+ 1F
MAX2078
Power-Down and Low-Power Mode
The MAX2078 can also be powered down with PD. Set PD to V CC 1 for power-down mode. In power-down mode, the device draws a total supply current less than 1A. Set PD to logic-low for normal operation. A low-power mode is available to lower the required power for CWD operation. When selected, the complex mixers operate at lower quiescent currents and the total per-channel current is lowered to 34.2mA. Note that operation in this mode slightly reduces the dynamic performance of the device. Table 4 shows the logic function of the standard operating modes.
Figure 2. Typical Example of a CW Mixer's Output Circuit
Applications Information
Mode Select Response Time
The mode select response time is the time that the device takes to switch between CW and VGA modes. Figure 2 depicts one possible approach to interfacing the CW outputs to an instrumentation amplifier, which is used to drive an ADC. In this implementation, there are four large-value (in the range of 470nF to 1F) capacitors between each of the CQ+, CQ-, CI+, CI- outputs and the circuitry they are driving. The output of the CW
mixer usually drives the input of an instrumentation amplifier made up of op amps whose input impedance is set by common-mode setting resistors. There are clearly both a highpass corner and a lowpass corner present in this output network. The lowpass corner is set primarily by the 162 mixer pullup resistors, the series 50 resistors, and the shunt 0.022F capacitor. This lowpass corner is used to filter a combination of LO leakage and upper sideband. The highpass corner, however, is of a larger concern since it is dominated by the combination of a 1F DC-blocking capacitor and the pair of shunt 31.6k resistors.
Table 4. Logic Function of Standard Operating Modes
PD INPUT 1 1 0 0 0 V/C CLP VGA CW MIXER Off Off On On Off INTERNAL SWITCH TO VGA Off Off Off Off On INTERNAL SWITCH TO CW MIXER Off Off On On Off 3.3V VCC 5V VCC 11V VMIX CURRENT CURRENT CURRENT CONSUMPTION CONSUMPTION CONSUMPTION 0.3A 0.1A 3.2mA 3.2mA 88mA 0.4A 0.6A 248mA 216mA 48mA 0 0 90.4mA 54.4mA 0
1 0 0 0 1
N/A N/A 0 1 N/A
Off Off Off Off On
N/A = Not applicable.
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
If drawn, the simplified dominant highpass network would look like Figure 3. The highpass pole in this case is at fP = 1/(2 x pi x RC) ~ 5Hz. Note that this low highpass corner frequency is required to filter the downconverted clutter tone, which appears at DC, but not interfere with CWD imaging at frequencies as low as 400Hz. For example, if one wanted to use CWD down to 400Hz, then a good choice for the highpass pole would be at least a decade below this (< 40Hz) as not to incur rolloff due to the pole. Remember, if the highpass pole is set to 400Hz, the response is 3dB down at that corner frequency. The placement of the highpass pole at 5Hz in the above example is between the DC and 40Hz limitations just discussed. The bottom line is that any reasonably sized DC block between the output of the mixer and the instrumentation amplifier poses a significant time constant that slows the mode select switching speed. An alternative solution to the approach in Figure 2, which enables faster mode select response time, is shown in Figure 4. In Figure 4, the outputs of the CWD mixers are DC-coupled into the inputs of the instrumentation amplifiers. Therefore, the op amps must be able to accommodate the full compliance range of the mixer outputs, which is a maximum of 11V when the mixers are disabled, down to the 5V supply of the MAX2078 when the mixers are enabled. The op amps can be powered from 11V for the high rail and 5V for the low rail, requiring a 6V op amp.
MAX2078
Figure 3. Simplified Circuit of Highpass Pole
+11V
+5V
Serial Interface
The MAX2078 is programmed using a serial shift register arrangement. This greatly simplifies the complexity of the program circuitry, reduces the number of IC pins necessary for programming, and reduces the PCB layout complexity. See Table 5 for the programming bit order. The data in (DIN) and data out (DOUT) can be daisy-chained from device to device and all front-ends can run off a single programming clock. The data can be entered after CS goes low. Once a whole word is entered, CS needs to rise. When programming the part, enter LSB first and MSB last.
Figure 4. Improved Mode Select Response Time Achieved with DC-Coupled Input to Instrumentation Amplifier
Programming the Beamformer
During the normal CWD mode, the mixer clock (LO+, LO-) is on and the programming signals (DIN, CLK, CS) are off (CS = high, CLK = low, and DIN = don't care, but fixed to a high or a low). To start the programming sequence, turn off the mixer clock. Data is shifted into
the shift register at a recommended 10MHz programming rate or 100ns minimum data clock period/time. Assuming a 64-channel CWD receiver, this takes about 30ms for 5 bits per channel. See Figure 5 for timing details. After the shift registers are programmed, pulling CS high loads the internal counters into I/Q phase divider/selectors with the proper values. The mixer clock needs to be off when this occurs or there may be timing issues between the load line timing and the mixer clock timing. The user turns on the mixer clock to start beamforming. The clock must turn on so that it starts at the beginning of a mixer clock cycle. A narrow glitch on the mixer clock is not acceptable and could cause metastability in the I/Q phase dividers.
20
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Table 5. Programming Bit Order
47 REGISTER BITS MSB CHANNEL 1 (i = 1) D46 D45 D44 D43 D42 D41 D40 D39 D38 D37 D36 D35 Di D46 D45 D44 D43 D42 D41 D40 Di + 4 Di + 3 Di + 2 Di + 1 ... ... ... D4 Di + 4 CHANNEL 8 (i = 8) D3 Di + 3 D2 Di + 2 D1 Di + 1 D0 Di LSB
MAX2078
tCS
tCW
tCH
tCLH
DIN
CLK tCWS CS tCSBMIX MIXER CLOCK ON
MIXER CLOCK OFF
MIXER CLOCK ON
LO+ LO-
MIXER CLOCK ON
MIXER CLOCK OFF
LO+ LO-
MIXER CLOCK OFF
MIXER CLOCK ON
Figure 5. Shift Register Timing Diagram
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21
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Ultrasound Front-End CWD Beamformer
The user provides an LO frequency of 16MHz to 120MHz. This high clock frequency requires a differential LVDS input. Note that the LVDS CWD LO clocks are DCcoupled. This is to ensure immediate synchronization when the clock is first turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the input impedance of the pin results in a period of time (related to the RC time constant) when the DC level on the chip side of the capacitor is outside the acceptable common-mode range and the LO swing cannot overcome both of the logic thresholds required for proper operation. This problem associated with AC coupling would cause an inability to ensure synchronization among beamforming channels. The LVDS signal is terminated differentially with an external 100 resistor on the board. The LO input is divided internally by 16 to produce 16 phases at a frequency of 1MHz to 7.5MHz. There is one divider per channel. Each channel has a corresponding 5-bit shift register (4 bits for phase programming and 1 bit for channel enable) that is used to program the output phase of the divide-by-16 circuit. The first 4 bits of the shift register are for programming the 16 phases, and the fifth bit can be used to turn on/off each channel individually through the serial bus.
Table 6. Noise Figure vs. Source and Input Impedances
RS () 50 100 200 1000 RIN () 50 100 200 1000 NF (dB) 4.5 3.4 2.4 2.1
amplifier (A) being defined with a differential output. For common input impedances, the internal digitally programmed impedances can be used (see Table 1). For other input impedances, program the impedance for external resistor operation, and then use an externally supplied resistor to set the input impedance according to the above formula.
Noise Figure
The MAX2078 is designed to provide maximum input sensitivity with exceptionally low noise figure. The input active devices are selected for very-low-equivalent input noise voltage and current, optimized for source impedances from 50 to 1000. Additionally, the noise contribution of the matching resistor is effectively divided by 1 + (A/2). Using this scheme, typical noise figure of the amplifier is approximately 2.4dB for RIN = RS = 200. Table 6 illustrates the noise figure for other input impedances.
CW Mixer Output Summation
The maximum differential current output is typically 3mA P-P and the mixer output-compliance voltage ranges from 4.5V to 12V per mixer channel. The mixer common-mode current in each of the differential mixer outputs is typically 2.83mA. The total summed current would equal N x 2.83mA in each of the 162 load resistors (where N = number of channels). In this case, the quiescent output voltage at +VSUM and -VSUM outputs would be 11V - (N x 2.83mA x 162) = 11 - (8 x 2.83mA x 162) = 7.34V. The voltage swing at each output, with one channel driven at maximum output current (differential 2.8mAP-P) while the other channels are not driven, would be 1.4mAP-P x 162 or 226mVP-P and the differential voltage would be 452mVP-P. The voltage compliance range is defined as the valid range for +VSUM and -VSUM in this example.
Input Clamp
The MAX2078 includes configurable integrated inputclamping diodes. The diodes are clamped to ground at 0.8V. The input-clamping diodes can be used to prevent large transmit signals from overdriving the inputs of the amplifiers. Overdriving the inputs could possibly place charge on the input-coupling capacitor, causing longer transmit overload recovery times. Input signals are AC-coupled to the single-ended inputs IN1-IN8, but are clamped with the INC1-INC8 inputs. See the Typical Application Circuit. If external clamping devices are preferred, simply leave INC1-INC8 unconnected.
Analog Output Coupling
The differential outputs of the VGA are capable of driving a differential load capacitance to GND at each of the differential outputs of 25pF, and the differential capacitance across the VGA outputs is 15pF, RL = 1k. The differential outputs have a common-mode bias of approximately 1.73V. AC-couple these differential outputs if the next stage has a different commonmode input range.
Active Impedance Matching
To provide exceptional noise-figure characteristics, the input impedance of each amplifier uses a feedback topology for active impedance matching. A feedback resistor of the value (1 + (A/2)) x RS is added between the inverting output of the amplifier to the input. The input impedance is the feedback resistor (ZF) divided by 1 + (A/2). The factor of two is due to the gain of the
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Ultrasound-Specific IMD3 Specification
Unlike typical communications applications, the two input tones are not equal in magnitude for the ultrasound-specific IMD3 two-tone specification. In this measurement, f1 represents reflections from tissue and f2 represents reflections from blood. The latter reflections are typically 25dB lower in magnitude, and hence the measurement is defined with one input tone 25dB lower than the other. The IMD3 product of interest (f1 - (f2 - f1)) presents itself as an undesired Doppler error signal in ultrasound applications (see Figure 6).
MAX2078
-25dB
ULTRASOUND IMD3
PCB Layout
The pin configuration of the MAX2078 is optimized to facilitate a very compact physical layout of the device and its associated discrete components. A typical application for this device might incorporate several devices in close proximity to handle multiple channels of signal processing. The exposed pad (EP) of the MAX2078's TQFP-EP package provides a low thermal-resistance path to the die. It is important that the PCB on which the MAX2078 is mounted be designed to conduct heat from the EP. In addition, provide the EP with a low-inductance path to electrical ground. The EP MUST be soldered to a ground plane on the PCB, either directly or through an array of plated via holes.
f1 - (f2 - f1)
f1
f2
f2 + (f2 - f1)
Figure 6. Ultrasound IMD3 Measurement Technique
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23
Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078
Typical Application Circuit
11V
R4 162 VCC2 IN1 C37 22nF C39 10nF ZF2 C1 22nF IN2 INC2 C2 10nF C3 22nF IN3 ZF3 IN3 INC3 C4 10nF C5 22nF IN4 ZF4 IN4 INC4 GND C6 10nF C7 10nF C8 22nF IN5 AG ZF5 IN5 INC5 C9 10nF C10 22nF IN6 ZF6 IN6 INC6 C11 10nF ZF7 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 *EP 17 18 IN7 19 INC7 C13 10nF C14 22nF IN8 C15 100nF 20 ZF8 21 IN8 22 INC8 23 VCC2 24 VREF 25 VCC1 26 VG+ 27 VG28 GND 29 CLP 30 PD 31 GND 32 DOUT 33 VCC2 C38 10nF ZF1 IN1 C36 100nF C35 100nF VCC1 R1 162 CS R2 162 R3 162 CSB DIN V/C NP C34 100nF CLK
VCC2
OUT1+
C33 4.7nF OUT1+ 52 51 50 49 48 47 46 45 44 OUT1OUT2+ OUT2OUT3+ OUT3OUT4+ OUT4VCC1 LO+ LOOUT5+ OUT5OUT6+ OUT6OUT7+ OUT7OUT8+ C18 4.7nF OUT8+ C20 4.7nF OUT7+ C19 4.7nF OUT7C22 4.7nF OUT6+ C21 4.7nF OUT6C24 4.7nF C25 100nF C27 4.7nF OUT4+ C26 4.7nF OUT4VCC1 C29 4.7nF OUT3+ C28 4.7nF OUT3C31 4.7nF OUT2+ C30 4.7nF OUT2VCC2 53 CQ+ CLK 54 CQV/C DIN 55 NP 57
VCC2
INC1
VCC1
CI+ 62
67
66
65
64
63
CI61
60
59
58
56
C32 4.7nF OUT1-
+
IN2
MAX2078
43 42 41 40 39 38 37 36 35 34 OUT8-
LO+ LOOUT5+
C23 4.7nF OUT5-
C12 22nF IN7
C40 4.7nF REF C16 100nF VG+ VGDOUT C17 100nF
OUT8-
*EP = EXPOSED PAD.
24
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Octal-Channel Ultrasound Front-End with CW Doppler Mixers
Chip Information
PROCESS: Complementary BiCMOS
PACKAGE TYPE 68 Thin QFN-EP
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE CODE T6800+4 DOCUMENT NO. 21-0142
MAX2078
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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