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| 16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP AD7985 FEATURES 16-bit resolution with no missing codes Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low) Low power dissipation 15.5 mW at 2.5 MSPS, with external reference 28 mW at 2.5 MSPS, with internal reference INL: 0.7 LSB typical, 1.5 LSB maximum SNR 88.5 dB, with on-chip reference 90 dB, with external reference 4.096 V internal reference: typical drift of 10 ppm/C Pseudo differential analog input voltage range 0 V to VREF with VREF up to 5.0 V Allows use of any input range No pipeline delay Logic interface: 1.8 V/2.5 V/2.7 V Serial interface: SPI-/QSPITM-/MICROWIRETM-/DSP-compatible Ability to daisy-chain multiple ADCs with busy indicator 20-lead, 4 mm x 4 mm LFCSP (QFN) APPLICATION DIAGRAM 5V 2.5V 1.8V TO 2.7V 0V TO VREF IN+ IN- VIO BVDD AVDD, DVDD TURBO VIO 3- OR 4-WIRE INTERFACE: SPI, CS, DAISY CHAIN (TURBO = LOW) AD7985 GND REF 10F SDI SCK SDO CNV NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. Figure 1. GENERAL DESCRIPTION The AD7985 is a 16-bit, 2.5 MSPS successive approximation analog-to-digital converter (SAR ADC). It contains a low power, high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. On the rising edge of CNV, the AD7985 samples an analog input, IN+, between 0 V and REF with respect to a ground sense, IN-. The AD7985 features a very high sampling rate turbo mode (TURBO is high) and a reduced power normal mode (TURBO is low) for low power applications where the power is scaled with the throughput. In normal mode (TURBO is low), the SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V supplies using the separate VIO supply. The AD7985 is available in a 20-lead LFCSP with operation specified from -40C to +85C. APPLICATIONS Battery-powered equipment Communications ATE Data acquisition systems Medical instruments Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR(R) ADCs 1 Type 14-Bit 16-Bit 100 kSPS AD7940 AD7680 AD7683 AD7684 250 kSPS AD7942 2 AD76852 AD76872 AD7694 AD76912 400 kSPS to 500 kSPS AD79462 AD76862 AD76882 AD76932 AD76902 1000 kSPS AD79802 AD79832 AD7985 3 AD79822 AD79842 AD79863 ADC Driver ADA4941-1 ADA4841-x AD8021 ADA4941-1 ADA4841-x AD8021 18-Bit 1 2 See www.analog.com for the latest selection of PulSAR ADCs and ADC drivers. Pin-for-pin compatible with all other parts marked with this endnote. 3 The AD7985 and AD7986 are pin-for-pin compatible. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. 07947-001 AD7985 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Application Diagram ........................................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 Circuit Information .................................................................... 13 Converter Operation .................................................................. 13 Conversion Modes of Operation .............................................. 13 Typical Connection Diagram ................................................... 14 Analog Inputs ............................................................................. 15 Driver Amplifier Choice ........................................................... 15 Voltage Reference Input ............................................................ 16 Power Supply............................................................................... 16 Digital Interface .............................................................................. 17 Data Reading Options ............................................................... 18 CS Mode, 3-Wire Without Busy Indicator ............................. 19 CS Mode, 3-Wire with Busy Indicator .................................... 20 CS Mode, 4-Wire Without Busy Indicator ............................. 21 CS Mode, 4-Wire with Busy Indicator .................................... 22 Chain Mode Without Busy Indicator ...................................... 23 Chain Mode with Busy Indicator ............................................. 24 Applications Information .............................................................. 25 Layout .......................................................................................... 25 Evaluating AD7985 Performance............................................. 25 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 REVISION HISTORY 9/09--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7985 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = -40C to +85C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Differential Nonlinearity Error, DNL Integral Nonlinearity Error, INL Transition Noise Gain Error, TMIN to TMAX 2 Gain Error Temperature Drift Zero Error, TMIN to TMAX2 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Signal-to-Noise Ratio, SNR Test Conditions/Comments Min 16 0 -0.1 -0.1 Typ Max Unit Bits V V V nA (IN+) - (IN-) IN+ IN- Acquisition phase VREF VREF + 0.1 +0.1 250 See the Analog Inputs section 16 -0.99 -1.50 -15 -0.99 AVDD = 2.5 V 5% 0 Full-scale step VREF = 4.096 V, internal reference VREF = 5.0 V, external reference fIN = 20 kHz, VREF = 4.096 V, internal reference fIN = 20 kHz, VREF = 5.0 V, external reference fIN = 20 kHz fIN = 20 kHz, VREF = 4.096 V, internal reference fIN = 20 kHz, VREF = 4.096 V 87.5 89.0 87.0 89.0 0.50 0.7 0.8 2 0.8 0.08 0.55 90 +0.99 +1.50 +15 +0.99 Bits LSB 1 LSB1 LSB1 LSB1 ppm/C mV ppm/C dB 3 MSPS ns dB3 dB3 dB3 dB3 dB3 dB3 dB3 2.5 100 89 90 88.5 90.0 103 -100 90.5 Spurious-Free Dynamic Range, SFDR Total Harmonic Distortion 4 , THD Signal-to-Noise-and-Distortion Ratio, SINAD SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay 1 2 3 19 0.7 MHz ns LSB means least significant bit. With the 4.096 V input range, one LSB is 62.5 V. See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Tested fully in production at fIN = 1 kHz. Rev. 0 | Page 3 of 28 AD7985 Table 3. Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Turn-On Settling Time REFIN Output Voltage REFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFIN Input Voltage Range REFIN Input Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES AVDD, DVDD BVDD VIO Standby Current 1, 2 Power Dissipation With Internal Reference With External Reference TEMPERATURE RANGE 3 Specified Performance 1 2 Test Conditions/Comments PDREF is low TA = 25C -40C to +85C AVDD = 2.5 V 5% CREF = 10 F, CREFIN = 0.1 F REFIN at 25C PDREF is high, REFIN is low Min 4.081 Typ 4.096 10 50 40 1.2 6 Max 4.111 Unit V ppm/C ppm/V ms V k V A V A 2.4 500 1.2 160 5.1 -0.3 0.9 x VIO -1 -1 0.1 x VIO VIO + 0.3 +1 +1 V V A A ISINK = +500 A ISOURCE = -500 A Serial 16 bits, straight binary Conversion results available immediately after completed conversion 0.4 VIO - 0.3 2.375 4.75 1.8 2.5 5.0 2.5 1.0 28 25 15.5 12 -40 2.625 5.25 2.7 V V V V V A mW mW mW mW C Specified performance AVDD = DVDD = VIO = 2.5 V 2.5 MSPS throughput 2.0 MSPS throughput 2.5 MSPS throughput 2.0 MSPS throughput TMIN to TMAX 33 30 17 13 +85 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. 0 | Page 4 of 28 AD7985 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = -40C to +85C, unless otherwise noted. 1 Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width Data Read During Conversion Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay CNV or SDI Low to SDO D15 MSB Valid CNV or SDI High or Last SCK Falling Edge to SDO High Impedance SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge SCK Valid Setup Time from CNV Rising Edge SCK Valid Hold Time from CNV Rising Edge SDI Valid Setup Time from SCK Falling Edge SDI Valid Hold Time from SCK Falling Edge SDI High to SDO High 1 Symbol tCONV tACQ tCYC tCNVH tDATA tQUIET tSCK tSCK tSCKL tSCKH tHSDO tDSDO tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI Test Conditions/Comments Turbo mode/normal mode Min 320/420 80 400/500 10 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Turbo mode/normal mode CS mode Turbo mode/normal mode 190/290 20 CS mode Chain mode 9 11 3.5 3.5 2 4 5 8 4 0 0 5 5 2 3 15 CS mode CS mode Chain mode Chain mode Chain mode Chain mode Chain mode Chain mode with busy indicator See Figure 2 and Figure 3 for load conditions. 500A IOL 10% VIO 90% VIO tDELAY TO SDO CL 20pF 500A IOH 07947-002 tDELAY VIH1 VIL1 VIH1 VIL1 07947-003 1.4V 1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. 0 | Page 5 of 28 AD7985 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN- to GND 1 Supply Voltage REF, BVDD to GND, REFGND AVDD, DVDD, VIO to GND AVDD, DVDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance 20-Lead LFCSP (QFN) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating -0.3 V to VREF + 0.3 V or 130 mA -0.3 V to +6.0 V -0.3 V to +2.7 V -6 V to +3 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 30.4C/W 215C 220C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION See the Analog Inputs section for an explanation of IN+ and IN-. Rev. 0 | Page 6 of 28 AD7985 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 19 18 17 16 REFIN BVDD AGND AGND AVDD REF REF REFGND REFGND IN- 1 2 3 4 5 PIN 1 INDICATOR AD7985 TOP VIEW (Not to Scale) 15 14 13 12 11 TURBO SDI CNV SCK DVDD Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 2 Mnemonic REF Type 1 AI Description Reference Output/Input Voltage. When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin. When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V. Decoupling is required with or without the internal reference and buffer. This pin is referred to the REFGND pins and should be decoupled closely to the REFGND pins with a 10 F capacitor. Reference Input Analog Ground. Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense. Analog Input. This pin is referred to IN-. The voltage range, that is, the difference between IN+ and IN-, is 0 V to VREF. Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When this pin is high, the internal reference is powered down and an external reference must be used. Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface (1.8 V, 2.5 V, or 2.7 V). Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Digital Power Ground. Digital Power. Nominally at 2.5 V. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved, and the ADC does not power down between conversions. When TURBO is low, the maximum throughput is lower (2.0 MSPS), and the ADC powers down between conversions. Input Analog Power. Nominally at 2.5 V. Analog Power Ground. 3, 4 5 6 7 8 9 10 11 12 13 REFGND IN- IN+ PDREF VIO SDO DGND DVDD SCK CNV AI AI AI DI P DO P P DI DI 14 SDI DI 15 TURBO DI 16 17, 18 AVDD AGND P P Rev. 0 | Page 7 of 28 07947-004 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. IN+ PDREF VIO SDO DGND 6 7 8 9 10 AD7985 Pin No. 19 Mnemonic BVDD Type 1 P Description Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 F typical). When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin. When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 20 REFIN AI/O 21 1 Exposed Pad EP AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power. Rev. 0 | Page 8 of 28 AD7985 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF is high, REFIN is low), unless otherwise noted. 1.25 1.00 0.75 0.50 0.50 DNL (LSB) INL (LSB) POSITIVE INL = +0.38LSB NEGATIVE INL = -0.46LSB 1.00 0.75 POSITIVE DNL = +0.19LSB NEGATIVE DNL = -0.20LSB 0.25 0 -0.25 -0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 07947-105 -0.75 -1.00 0 16,384 32,768 CODE 49,152 65,536 0 16,384 32,768 CODE 49,152 65,536 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 60,000 57,138 60,000 53,522 48,730 50,000 50,000 40,000 COUNTS 38,843 40,000 COUNTS 30,000 26,249 30,000 20,000 20,000 11,888 15,645 10,000 0 122 6150 2537 07947-106 10,000 33 0 0 2 479 800 6 0 07947-109 07947-110 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX CODE IN HEX Figure 6. Histogram of DC Input at Code Center (External Reference) Figure 9. Histogram of DC Input at Code Transition (External Reference) 60,000 49,585 50,000 45,000 40,000 35,000 31,957 46,649 43,622 50,000 40,000 COUNTS COUNTS 33,064 30,000 25,000 20,000 15,000 20,474 15,598 30,000 20,000 10,000 0 11 565 8455 10,000 7024 5000 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 CODE IN HEX 07947-107 2947 0 90 0 403 8 0 1662 0 30 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 CODE IN HEX Figure 7. Histogram of DC Input at Code Center (Internal Reference) Figure 10. Histogram of DC Input at Code Transition (Internal Reference) Rev. 0 | Page 9 of 28 07947-108 -1.25 AD7985 0 -20 -40 AMPLITUDE (dB) fS = 2.5MSPS fIN = 20kHz 0 -20 -40 AMPLITUDE (dB) SNR = 89.87dB THD = -102.76dB SINAD = 89.66dB fS = 2.5MSPS fIN = 20kHz SNR = 88.45dB THD = -103.42dB SINAD = 88.32dB -60 -80 -100 -120 -140 -160 07947-111 -60 -80 -100 -120 -140 -160 07947-114 -180 0 250 500 750 1000 1250 -180 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. FFT Plot (External Reference) Figure 14. FFT Plot (Internal Reference) 100 16 -90 100 95 SNR, SINAD (dB) 15 ENOB THD (dB) -95 SFDR 95 90 SINAD 85 14 -100 90 13 -105 THD 85 07947-112 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD and SFDR vs. Reference Voltage 95 -85 90 -90 85 SINAD (dB) THD (dB) -95 80 -100 75 -105 70 07947-113 1 10 100 1000 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 13. SINAD vs. Frequency Figure 16. THD vs. Frequency Rev. 0 | Page 10 of 28 07947-116 65 -110 07947-115 80 2.50 12 5.00 -110 2.50 80 5.00 SFDR (dB) SNR ENOB (Bits) AD7985 95 94 OPERATING CURRENT (mA) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 07947-117 93 92 SNR (dB) IAVDD 91 90 89 88 87 86 85 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IBVDD IREF -35 -15 5 25 45 65 85 105 125 INPUT LEVEL (dBFS) TEMPERATURE (C) Figure 17. SNR vs. Input Level Figure 19. Operating Current vs. Temperature 2.0 1.8 OPERATING CURRENT (mA) 14 IAVDD IDVDD IVIO 12 SUPPLY CURRENT (A) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 07947-118 10 8 6 4 IAVDD + IDVDD + IVIO 2 0 -55 IBVDD IREF 2.425 2.475 2.525 2.575 2.625 -35 -15 5 25 45 65 85 105 125 AVDD AND DVDD VOLTAGE (V) TEMPERATURE (C) Figure 18. Operating Current vs. Supply Voltage Figure 20. Power-Down Current vs. Temperature Rev. 0 | Page 11 of 28 07947-120 0 2.375 07947-119 0 -55 AD7985 TERMINOLOGY Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is measured with a signal at -60 dBFS so that it includes all noise sources and DNL artifacts. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is expressed in bits and is related to SINAD as follows: ENOB = (SINADdB - 1.76)/6.02 Effective Resolution Effective resolution is expressed in bits and is calculated as follows: Effective Resolution = log2(2N/RMS Input Noise) Gain Error The last transition (from 111 ... 10 to 111 ... 11) should occur for an analog voltage 11/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is expressed in bits and is calculated as follows: Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Rev. 0 | Page 12 of 28 AD7985 THEORY OF OPERATION IN+ MSB LSB 32,768C REF COMP REFGND 32,768C 16,384C MSB 4C 2C C C LSB SW- CNV 16,384C 4C 2C C C CONTROL LOGIC OUTPUT CODE SWITCHES CONTROL SW+ BUSY IN- Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7985 is a fast, low power, single-supply, precise, 16-bit ADC using a successive approximation architecture. The AD7985 features different modes to optimize performance according to the application. In turbo mode, the AD7985 is capable of converting 2,500,000 samples per second (2.5 MSPS). The AD7985 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7985 can be interfaced to any 1.8 V to 2.7 V digital logic family. It is available in a space-saving 20-lead LFCSP that allows flexible configurations. It is pin-for-pin compatible with the 18-bit AD7986. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the analog inputs and connected to the REFGND input. Therefore, the differential voltage between the IN+ and IN- inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4, ... VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7985 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. CONVERTER OPERATION The AD7985 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors that are connected to the two comparator inputs. During the acquisition phase, the terminals of the array tied to the input of the comparator are connected to AGND via SW+ and SW-. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is completed and the CNV input goes high, a conversion phase is initiated. CONVERSION MODES OF OPERATION The AD7985 features two conversion modes of operation: turbo and normal. Turbo conversion mode (TURBO is high) allows the fastest conversion rate of up to 2.5 MSPS and does not power down between conversions. The first conversion in turbo mode should be ignored because it contains meaningless data. For applications that require lower power and slightly slower sampling rates, the normal mode (TURBO is low) allows a maximum conversion rate of 2.0 MSPS and powers down between conversions. The first conversion in normal mode contains meaningful data. Rev. 0 | Page 13 of 28 07947-005 AD7985 Transfer Functions The ideal transfer characteristic for the AD7985 is shown in Figure 22 and Table 7. ADC CODE (STRAIGHT BINARY) Table 7. Output Codes and Ideal Input Voltages Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 1 111 ... 111 111 ... 110 111 ... 101 Analog Input, VREF = 4.096 V 4.095938 V 2.048063 V 2.048 V 2.047938 V 62.5 V 0V Digital Output Code (Hex) 0xFFFF1 0x8001 0x8000 0x7FFF 0x0001 0x00002 2 This is also the code for an overranged analog input (VIN+ - VIN- above VREF - REFGND). This is also the code for an underranged analog input (VIN+ - VIN- below REFGND). 000 ... 010 000 ... 001 000 ... 000 -FSR TYPICAL CONNECTION DIAGRAM -FSR + 1 LSB +FSR - 1 LSB +FSR - 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function 07947-006 -FSR + 0.5 LSB Figure 23 shows an example of the recommended connection diagram for the AD7985 when multiple supplies are available. 5V V+ 15 0V TO VREF V- 2.7nF IN+ IN- REF 10F NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. 2.5V 1.8V TO 2.7V BVDD AVDD, DVDD VIO TURBO SDI SCK SDO CNV VIO 3- OR 4-WIRE INTERFACE: SPI, CS, DAISY CHAIN (TURBO = LOW) AD7985 GND Figure 23. Typical Application Diagram with Multiple Supplies Rev. 0 | Page 14 of 28 07947-007 AD7985 ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7985. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN-. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the V+ and V- supplies of the buffer amplifier in Figure 23) are different from those of REF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. REF D1 IN+ OR IN- CPIN REFGND D2 07947-008 DRIVER AMPLIFIER CHOICE Although the AD7985 is easy to drive, the driver amplifier must meet the following requirements: * The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7985. The noise from the driver is filtered by the AD7985 analog input circuit's one-pole, lowpass filter, made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD7985 is 50 V rms, the SNR degradation due to the amplifier is 50 = 20 log 2 50 + f -3dB (Ne N ) 2 2 SNR LOSS RIN CIN Figure 24. Equivalent Analog Input Circuit where: f-3dB is the input bandwidth, in megahertz, of the AD7985 (20 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz. * * For ac applications, the driver should have a THD performance commensurate with that of the AD7985. For multichannel multiplexed applications, the driver amplifier and the AD7985 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the data sheet of the driver amplifier, settling at 0.1% to 0.01% is more commonly specified. This value may differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The analog input structure allows the sampling of the true differential signal between IN+ and IN-. By using these differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs (IN+ and IN-) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. When the source impedance of the driving circuit is low, the AD7985 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Table 8. Recommended Driver Amplifiers Amplifier AD8021 AD8022 ADA4899-1 AD8014 Typical Application Very low noise and high frequency Low noise and high frequency Ultralow noise and high frequency Low power and high frequency Rev. 0 | Page 15 of 28 AD7985 VOLTAGE REFERENCE INPUT The AD7985 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. The internal reference of the AD7985 provides excellent performance and can be used in almost all applications. Reference Decoupling The AD7985 voltage reference input, REF, has a dynamic input impedance that requires careful decoupling between the REF and REFGND pins. The Layout section describes how this can be done. When using an external reference, a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605) and a 10 F (X5R, 0805 size) ceramic chip capacitor are appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For example, a 22 F (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference decoupling capacitor with a value as small as 2.2 F can be used with minimal impact on performance, especially DNL. In any case, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and REFGND pins. Internal Reference, REF = 4.096 V (PDREF Low) To use the internal reference, the PDREF input must be low. This enables the on-chip band gap reference and buffer, resulting in a 4.096 V reference on the REF pin (1.2 V on REFIN). The internal reference is temperature compensated to 4.096 V 15 mV. The reference is trimmed to provide a typical drift of 10 ppm/C. The output resistance of REFIN is 6 k when the internal reference is enabled. It is necessary to decouple this pin with a ceramic capacitor of at least 100 nF. The output resistance of REFIN and the decoupling capacitor form an RC filter, which helps to reduce noise. Because the output impedance of REFIN is typically 6 k, relative humidity (among other industrial contaminants) can directly affect the drift characteristics of the reference. A guard ring is typically used to reduce the effects of drift under such circumstances. However, the fine pitch of the AD7985 makes this difficult to implement. One solution, in these industrial and other types of applications, is to use a conformal coating, such as Dow Corning(R) 1-2577 or HumiSeal(R) 1B73. POWER SUPPLY The AD7985 has four power supply pins: an analog supply (AVDD), a buffer supply (BVDD), a digital supply (DVDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic from 1.8 V to 2.7 V. To reduce the number of supplies needed, VIO, DVDD, and AVDD can be tied together. The power supplies do not need to be started in a particular sequence. In addition, the AD7985 is very insensitive to power supply variations over a wide frequency range. In normal mode, the AD7985 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. This makes the part ideal for low sampling rates (even a few SPS) and battery-powered applications. 10 External 1.2 V Reference and Internal Buffer (PDREF High) To use an external reference along with the internal buffer, PDREF must be high. This powers down the internal reference and allows the 1.2 V reference to be applied to REFIN, producing 4.096 V (typically) on the REF pin. External Reference (PDREF High, REFIN Low) To apply an external reference voltage directly to the REF pin, PDREF should be tied high and REFIN should be tied low. BVDD should also be driven to the same potential as REF. For example, if REF = 2.5 V, BVDD should be tied to 2.5 V. The advantages of directly using an external voltage reference are as follows: * SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a larger reference voltage (5 V) instead of a typical 4.096 V reference when the internal reference is used. This is calculated by OPERATING CURRENT (mA) 1 0.1 1 SAMPLING RATE (MSPS) * Power savings when the internal reference is powered down (PDREF high). Figure 25. Operating Current vs. Sampling Rate in Normal Mode Rev. 0 | Page 16 of 28 07947-121 4.096 SNR = 20 log 5.0 0.01 0.1 IBVDD IAVDD IDVDD IVIO IVREF AD7985 DIGITAL INTERFACE Although the AD7985 has a reduced number of pins, it offers flexibility in its serial interface modes. In CS mode, the AD7985 is compatible with SPI, MICROWIRE, QSPI, and digital hosts. In CS mode, the AD7985 can use either a 3-wire or a 4-wire interface. A 3-wire interface that uses the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for example, in isolated applications. A 4-wire interface that uses the SDI, CNV, SCK, and SDO signals allows CNV, which initiates conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. In chain mode, the AD7985 provides a daisy-chain feature that uses the SDI input for cascading multiple ADCs on a single data line similar to a shift register. Chain mode is available only in normal mode (TURBO is low). The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, chain mode is always selected. In normal mode operation, the AD7985 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 29 and Figure 33). TURBO must be kept low for both digital interfaces. When CNV is low, readback can occur during conversion or acquisition, or it can be split across acquisition and conversion, as described in the following sections. A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to clock out data. Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, SDI, and SDO) during the conversion. However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading time, tDATA, because the AD7985 provides error correction circuitry that can correct for an incorrect bit decision during this time. From tDATA to tCONV, there is no error correction, and conversion results may be corrupted. Similarly, tQUIET, the time from the last falling edge of SCK to the rising edge of CNV, must remain free of digital activity. The user should configure the AD7985 and initiate the busy indicator (if desired in normal mode) prior to tDATA. It is also possible to corrupt the sample by having SCK near the sampling instant. Therefore, it is recommended that the digital pins be kept quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation. Rev. 0 | Page 17 of 28 AD7985 DATA READING OPTIONS There are three different data reading options for the AD7985. There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 28 and Figure 29), and, in normal mode, to read during acquisition. The desired SCK frequency largely determines which reading option to use. To determine how to split the read for a particular SCK frequency, follow these examples to read data from conversion (n - 1). For turbo mode (2.5 MSPS): fSCK = 70 MHz; tDATA = 190 ns Number_SCK_Edges = 70 MHz x 190 ns = 13.3 Thirteen bits are read during conversion (n), and three bits are read during acquisition (n). For normal mode (2.0 MSPS): fSCK = 45 MHz; tDATA = 290 ns Number_SCK_Edges = 45 MHz x 290 ns = 13.05 Thirteen bits are read during conversion (n), and three bits are read during acquisition (n). For slow throughputs, the time restriction is dictated by the throughput required by the user; the host is free to run at any speed. Similar to reading during acquisition, data access for slow hosts must take place during the acquisition phase with additional time into the conversion. Note that data access spanning conversion requires the CNV pin to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method. Reading During Conversion, Fast Host (Turbo or Normal Mode) When reading during conversion (n), conversion results are for the previous (n - 1) conversion. Reading should occur only up to tDATA and, because this time is limited, the host must use a fast SCK. The required SCK frequency is calculated by f SCK Number _ SCK _ Edges t DATA To determine the minimum SCK frequency, follow these examples to read data from conversion (n - 1). For turbo mode (2.5 MSPS): Number_SCK_Edges = 16; tDATA = 190 ns fSCK = 16/190 ns = 84.2 MHz For normal mode (2.0 MSPS): Number_SCK_Edges = 16; tDATA = 290 ns fSCK = 16/290 ns = 55.2 MHz The time between tDATA and tCONV is an I/O quiet time during which digital activity should not occur, or sensitive bit decisions may be corrupted. Reading During Acquisition, Any Speed Host (Turbo or Normal Mode) When reading during acquisition (n), conversion results are for the previous (n - 1) conversion. Maximum throughput is achievable in normal mode (2.0 MSPS); however, in turbo mode, 2.5 MSPS throughput is not achievable. For the maximum throughput, the only time restriction is that reading take place during the tACQ (minimum) time. For slow throughputs, the time restriction is dictated by the throughput required by the user; the host is free to run at any speed. Thus, for slow hosts, data access must take place during the acquisition phase. Split-Reading, Any Speed Host (Turbo or Normal Mode) To allow for a slower SCK, there is the option of a split read, where data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n - 1) conversion. Similar to reading during conversion, split-reading should occur only up to tDATA. For the maximum throughput, the only time restriction is that split-reading take place during the tACQ (minimum) + (tDATA - tQUIET) time. The time between the falling edge of SCK and CNV rising is an acquisition quiet time, tQUIET. Rev. 0 | Page 18 of 28 AD7985 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 26, and the corresponding timing is given in Figure 27. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. When a conversion is initiated, it continues until completion, irrespective of the state of CNV. This can be useful, for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7985 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CONVERT CNV VIO SDI DIGITAL HOST SDO DATA IN AD7985 SCK CLK Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) tCYC >tCONV tCONV 07947-009 SDI = 1 CNV tDATA tCNVH tCONV tDATA tACQ ACQUISITION (n - 1) CONVERSION (n - 1) (I/O QUIET TIME) ACQUISITION (n) (I/O QUIET TIME) CONVERSION (n) (I/O QUIET TIME) ACQUISITION (n + 1) tQUIET SCK 14 15 16 1 2 14 15 16 tHSDO tEN SDO 2 1 0 tSCK tEN 15 14 13 tDSDO tDIS END DATA (n - 1) tDIS 07947-010 2 1 0 tDIS END DATA (n - 2) tDIS BEGIN DATA (n - 1) Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. 0 | Page 19 of 28 AD7985 CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host that has an interrupt input. It is available only in normal conversion mode (TURBO is low). The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCK falling edge, SDO returns to high impedance. If multiple AD7985 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. CONVERT VIO CNV VIO SDI 47k DIGITAL HOST DATA IN IRQ AD7985 SCK SDO TURBO CLK 07947-011 Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) TURBO = 0 SDI = 1 tCYC tCNVH CNV tCONV ACQUISITION CONVERSION tACQ ACQUISITION (I/O QUIET TIME) tSCK tSCKL SCK 1 2 3 15 16 17 tQUIET tHSDO tDSDO SDO D15 D14 tSCKH tDIS D1 D0 07947-012 Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. 0 | Page 20 of 28 AD7985 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR This mode is usually used when multiple AD7985 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7985 devices is shown in Figure 30, and the corresponding timing is given in Figure 31. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7985 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCK falling edge, SDO returns to high impedance and another AD7985 can be read. CS2 CS1 CONVERT CNV SDI CNV SDO SDI AD7985 SCK AD7985 SCK SDO DIGITAL HOST DATA IN CLK Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram tCYC tCONV tDATA CNV tCONV tDATA tACQ ACQUISITION (n - 1) 07947-013 CONVERSION (n - 1) (I/O QUIET TIME) ACQUISITION (n) (I/O QUIET TIME) CONVERSION (n) (I/O QUIET TIME) ACQUISITION (n + 1) tHSDICNV SDI tSSDICNV tQUIET SCK 14 15 16 1 2 14 15 16 tHSDO tEN SDO 2 1 0 tSCK tEN 15 14 13 tDSDO tDIS END DATA (n - 1) tDIS 07947-014 2 1 0 END DATA (n - 2) tHSDO BEGIN DATA (n - 1) Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. 0 | Page 21 of 28 AD7985 CS MODE, 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. This mode is available only in normal conversion mode (TURBO is low). The connection diagram is shown in Figure 32, and the corresponding timing is given in Figure 33. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance. CS1 CONVERT VIO CNV 47k SDI DIGITAL HOST DATA IN IRQ 07947-015 AD7985 SCK SDO TURBO CLK Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram TURBO = 0 tCYC CNV tCONV ACQUISITION CONVERSION tACQ ACQUISITION (I/O QUIET TIME) tSSDICNV SDI tHSDICNV tSCKL SCK 1 2 3 15 tSCK tQUIET 16 17 tHSDO tDSDO tEN SDO D15 D14 tSCKH tDIS D1 D0 07947-016 Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. 0 | Page 22 of 28 AD7985 CHAIN MODE WITHOUT BUSY INDICATOR This mode can be used to daisy-chain multiple AD7985 devices on a 3-wire serial interface. It is available only in normal conversion mode (TURBO is low). This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7985 devices is shown in Figure 34, and the corresponding timing is given in Figure 35. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD7985 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7985 devices in the chain, provided that the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. CONVERT CNV SDI CNV SDO TURBO SDI DIGITAL HOST SDO TURBO 07947-017 AD7985 A SCK AD7985 B SCK DATA IN CLK Figure 34. Chain Mode Without Busy Indicator Connection Diagram TURBO = 0 SDIA = 0 tCYC CNV tCONV ACQUISITION CONVERSION tACQ ACQUISITION tQUIET SCK 1 2 3 tSCKL 14 15 tSCK 16 17 18 30 31 32 tHSCKCNV tEN SDOA = SDIB tSSDISCK tHSDISCK DA15 DA14 DA13 DA1 tSCKH DA0 tHSDO tDSDO SDOB DB15 DB14 DB13 DB1 DB0 DA15 DA14 DA1 DA0 07947-018 Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing Rev. 0 | Page 23 of 28 AD7985 CHAIN MODE WITH BUSY INDICATOR This mode can be used to daisy-chain multiple AD7985 devices on a 3-wire serial interface while providing a busy indicator. It is available only in normal conversion mode (TURBO is low). This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7985 devices is shown in Figure 36, and the corresponding timing is given in Figure 37. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7985 ADC labeled C in Figure 36) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7985 devices in the chain, provided that the digital host has an acceptable hold time. CONVERT CNV SDI CNV SDO TURBO SDI CNV SDO TURBO SDI DIGITAL HOST SDO TURBO DATA IN IRQ 07947-019 AD7985 A SCK AD7985 B SCK AD7985 C SCK CLK Figure 36. Chain Mode with Busy Indicator Connection Diagram TURBO = 0 tCYC CNV = SDIA tCONV CONVERSION tACQ ACQUISITION ACQUISITION tSSCKCNV SCK 1 2 3 tSCKH 4 tSCK 15 16 17 18 19 31 32 33 34 35 47 48 49 tHSCKCNV SDOA = SDIB tEN tSSDISCK tHSDISCK DA1 tSCKL DA0 tDSDOSDI DA15 DA14 DA13 SDOB = SDIC SDOC tDSDOSDI tDSDOSDI tHSDO tDSDO DB15 DB14 DB13 DC15 DC14 DC13 DB1 DC1 DB0 DA15 DA14 DC0 DB15 DB14 DA1 DB1 DA0 DB0 DA15 DA14 tDSDOSDI tDSDOSDI DA1 DA0 Figure 37. Chain Mode with Busy Indicator Serial Interface Timing Rev. 0 | Page 24 of 28 07947-020 AD7985 APPLICATIONS INFORMATION LAYOUT The printed circuit board (PCB) that houses the AD7985 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7985, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD7985 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7985 devices. The AD7985 voltage reference inputs (REF) have a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and REFGND pins and connecting them with wide, low impedance traces. Finally, the power supplies, VDD and VIO of the AD7985, should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7985 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. EVALUATING AD7985 PERFORMANCE Other recommended layouts for the AD7985 are outlined in the documentation for the AD7985 evaluation board (EVAL-AD7985EBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CED1Z board. Rev. 0 | Page 25 of 28 AD7985 BVDD AVDD REF REF REF 1 2 3 4 5 PADDLE GND GND GND GND DVDD GND GND GND 6 VIO Figure 38. Example Layout of the AD7985 (Top Layer) 5V EXTERNAL REFERENCE (ADR435 OR ADR445) CBVDD BVDD AVDD CAVDD REF REF REF GND CREF GND GND GND GND CDVDD DVDD GND GND GND VIO VIO CVIO Figure 39. Example Layout of the AD7985 (Bottom Layer) Rev. 0 | Page 26 of 28 07947-031 07947-030 AD7985 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 15 16 20 1 0.60 MAX PIN 1 INDICATOR PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 5 2.65 2.50 SQ 2.35 TOP VIEW 0.80 MAX 0.65 TYP 0.50 0.40 0.30 11 10 6 0.25 MIN 1.00 0.85 0.80 SEATING PLANE 12 MAX COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Model AD7985BCPZ 1 AD7985BCPZ-RL71 EVAL-AD7985EBZ1, 2 EVAL-CED1Z 3 1 2 3 090408-B 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Temperature Range -40C to +85C -40C to +85C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel Evaluation Board Converter Evaluation and Development Board Package Option CP-20-4 CP-20-4 Ordering Quantity 490 1,500 Z = RoHS Compliant Part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the EB designator. Rev. 0 | Page 27 of 28 AD7985 NOTES (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07947-0-9/09(0) Rev. 0 | Page 28 of 28 |
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